# Power MOSFET, N Channel, 30 V, 10.8 A, 0.0092 ohm, SOIC, Surface Mount

![Product image](https://novapart.co/image/farnell:2630357/)

**URL**: https://novapart.co/products/NTMFS4823NT1G/power-mosfet-n-channel-30-v-108-a-00092-ohm-soic
**SKU**: NTMFS4823NT1G
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.3180
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Power Dissipation | 2.1W |
| Transistor Mounting | Surface Mount |
| Transistor Polarity | N Channel |
| Power Dissipation Pd | 2.1W |
| Rds(On) Test Voltage | 10V |
| On Resistance Rds(On) | 0.0092ohm |
| Transistor Case Style | SOIC |
| Drain Source Voltage Vds | 30V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 10.8A |
| Drain Source On State Resistance | 0.0092ohm |
| Gate Source Threshold Voltage Max | 1.9V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2630357/)

## NTMFS4823N 

## Power MOSFET 

## **30 V, 30 A, Single N−Channel, SO−8 FL** 

## **Features** 

- Low R to Minimize Conduction Losses DS(on) 

- Low Capacitance to Minimize Driver Losses 

- Optimized Gate Charge to Minimize Switching Losses 

- These are Pb−Free Device 

## **Applications** 

- Refer to Application Note AND8195/D 

- CPU Power Delivery 

- DC−DC Converters 

**==> picture [190 x 78] intentionally omitted <==**

**----- Start of picture text -----**<br>
http://onsemi.com<br>V(BR)DSS RDS(ON) MAX ID MAX<br>10.5 m  @ 10 V<br>30 V 30 A<br>18.0 m  @ 4.5 V<br>CT<br>**----- End of picture text -----**<br>


- High Side Switching 

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MAXIMUM RATINGS  (TJ = 25 ° C unless otherwise stated) D (5,6)<br>ee Parameter Ge Symbol Value ee Unit<br>a Drain−to−Source Voltage Gs VDSS 30 V<br>Gate−to−Source Voltage VGS ± 20 V G (4)<br>Continuous Drain TA = 25 ° C ID 10.8 A<br>|. Current R(Note 1) JA He TA = 85 ° C 7.8 S (1,2,3)<br>Power Dissipation TA = 25 ° C PD 2.1 W N−CHANNEL MOSFET<br>a R JA (Note 1) eeee ee<br>Continuous Drain TA = 25 ° C ID 17.4 A<br>Current R10 sec JA TA = 85 ° C 12.5 MARKINGDIAGRAM<br>=<br>Power Dissipation TA = 25 ° C PD 5.43 W D<br>R JA, t   10 sec Steady | | a S D<br>Continuous Drain State TA = 25 ° C ID 6.9 A 1 S 4823N<br>P| Current R(Note 2) JA TS TA = 85 ° C 5.0 SO−8 FLAT LEADCASE 488AA GS | AYWZZ D<br>Power Dissipation TA = 25 ° C PD 0.86 W STYLE 1 D<br>R JA (Note 2)<br>Py Continuous Drain EY TC = 25 ° C ID 30 A A = Assembly Location<br>Pe. Current R(Note 1) JC pf TC = 85 ° C ff 22 YW = Year= Work Week<br>Power Dissipation | T EY C = 25 ° C PD ee 32.5 W ZZ = Lot Traceability<br>ee R JC (Note 1) ee<br>Pulsed Drain tp=10 s TA = 25 ° C IDM 85 A<br>Current<br>a eee<br>en Current limited by package TA = 25 ° C IDmaxpkg 90 A ORDERING INFORMATION<br>Operating Junction and Storage TJ, −55 to ° C Device Package Shipping [[†]]<br>Temperature TSTG +150 NTMFS4823NT1G SO−8FL 1500 /<br>Source Current (Body Diode) IS 32.5 A (Pb−Free) Tape & Reel<br>Drain to Source dV/dt dV/dt 6.0 V/ns<br>a NTMFS4823NT3G SO−8FL 5000 /<br>Single Pulse Drain−to−Source Avalanche EAS 28.8 mJ (Pb−Free) Tape & Reel<br>ee Energy (VDD = 50 V, VGS = 10 V, ee eee T+<br>ee IL =  24 Apk, L = 0.1 mH, RG = 25  †For information on tape and reel specifications,<br>Lead Temperature for Soldering Purposes ee TL 260 ° C including part orientation and tape sizes, please<br>refer to our Tape and Reel Packaging Specifications<br>ee (1/8” from case for 10 s)<br>**----- End of picture text -----**<br>


**==> picture [191 x 122] intentionally omitted <==**

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ORDERING INFORMATION<br>Device Package Shipping [[†]]<br>NTMFS4823NT1G SO−8FL 1500 /<br>(Pb−Free) Tape & Reel<br>NTMFS4823NT3G SO−8FL 5000 /<br>(Pb−Free) Tape & Reel<br>T+<br>†For information on tape and reel specifications,<br>including part orientation and tape sizes, please<br>refer to our Tape and Reel Packaging Specifications<br>Brochure, BRD8011/D.<br>**----- End of picture text -----**<br>


Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2012 **May, 2012 − Rev. 3** 

**NTMFS4823N/D** 

**NTMFS4823N** 

## **THERMAL RESISTANCE MAXIMUM RATINGS** 

|**THERMAL RESISTANCE MAXIMUM RATINGS**||||
|---|---|---|---|
|**Parameter**|**Symbol**|**Value**|**Unit**|
|Junction−to−Case (Drain)|R�JC|3.8|°C/W|
|Junction−to−Ambient – Steady State (Note 1)|R�JA|59.4||
|Junction−to−Ambient – Steady State (Note 2)|R�JA|146||
|Junction−to−Ambient − t�10 sec|R�JA|23||



1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu. 

2. Surface−mounted on FR4 board using the minimum recommended pad size. 

**ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) 

|**Parameter**|**Symbol**|**Test Condition**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|30|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/<br>TJ||||24||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 24 V|TJ= 25°C|||1.0|�A|
||||TJ= 125°C|||10||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS|=±20 V|||±100|nA|
|**ON CHARACTERISTICS**(Note 3)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID=|250�A|1.5|1.9|2.5|V|
|Negative Threshold Temperature Coefficient|VGS(TH)/TJ||||5.1||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 10 V to<br>11.5 V|ID= 30 A||9.2|10.6|m�|
||||ID= 15 A||9.1|||
|||VGS= 4.5 V|ID= 30 A||15.6|18.0||
||||ID= 15 A||15.1|||
|Forward Transconductance|gFS|VDS= 1.5 V, ID= 15 A|||26||S|
|**CHARGES AND CAPACITANCES**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1 MHz, VDS= 15 V|||795||pF|
|Output Capacitance|COSS||||163|||
|Reverse Transfer Capacitance|CRSS||||85|||
|Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 15 V; ID= 30 A|||6.0|11|nC|
|Threshold Gate Charge|QG(TH)||||1.0|||
|Gate−to−Source Charge|QGS||||2.6|||
|Gate−to−Drain Charge|QGD||||2.5|||
|Total Gate Charge|QG(TOT)|VGS= 11.5 V, VDS= 15 V,<br>ID= 30 A|||13||nC|
|**SWITCHING CHARACTERISTICS**(Note 4)||||||||
|Turn−On Delay Time|td(ON)|VGS= 4.5 V, VDS= 15 V,<br>ID= 15 A, RG= 3.0�|||10.8||ns|
|Rise Time|tr||||29|||
|Turn−Off Delay Time|td(OFF)||||12.7|||
|Fall Time|tf||||3.8|||



3. Pulse Test: pulse width � 300 � s, duty cycle � 2%. 

4. Switching characteristics are independent of operating junction temperatures. 

**http://onsemi.com** 

**2** 

## **NTMFS4823N** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) 

|**ELECTRICAL CHARACTERISTICS**(TJ=|25°C unless|otherwise specified)|otherwise specified)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**SWITCHING CHARACTERISTICS**(Note 4)||||||||
|Turn−On Delay Time|td(ON)|VGS= 11.5 V, VDS= 15 V,<br>ID= 15 A, RG= 3.0�|||6.65||ns|
|Rise Time|tr||||15.3|||
|Turn−Off Delay Time|td(OFF)||||17.6|||
|Fall Time|tf||||3.0|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 30 A|TJ= 25°C||0.95|1.2|V|
||||TJ= 125°C||0.8|||
|Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt = 100 A/�s,<br>IS= 30 A|||7.9||ns|
|Charge Time|ta||||5.8|||
|Discharge Time|tb||||2.1|||
|Reverse Recovery Charge|QRR||||0.6||nC|
|**PACKAGE PARASITIC VALUES**||||||||
|Source Inductance|LS|TA= 25°C|||1.3||nH|
|Drain Inductance|LD||||0.005|||
|Gate Inductance|LG||||1.84|||
|Gate Resistance|RG||||1.0|3.0|�|



3. Pulse Test: pulse width � 300 � s, duty cycle � 2%. 

4. Switching characteristics are independent of operating junction temperatures. 

**http://onsemi.com** 

**3** 

**NTMFS4823N** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [490 x 591] intentionally omitted <==**

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90 60<br>VGS = 10 V 5.5 V TJ = 25 ° C<br>80 VDS ≥  −10 V<br>7.0 V 50<br>70<br>6.5 V 4.5 V<br>60 40<br>6.0 V 4.2 V<br>50<br>4.0 V 30<br>40 3.8 V<br>30 3.6 V 20<br>3.4 V TJ = 25 ° C<br>20 3.2 V<br>10<br>10 3.0 V TJ = 100 ° C TJ = −55 ° C<br>0 2.8 V 0<br>0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1 2 3 4 5 6<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>0.045 0.022<br>0.040 TIDJ = 30 A = 25 ° C 0.020 TJ = 25 ° C<br>0.018<br>0.035 VGS = 4.5 V<br>0.016<br>0.030<br>0.014<br>0.025<br>0.012<br>0.020 VGS = 10 V<br>0.010<br>0.015<br>0.008<br>0.010 0.006<br>0.005 0.004<br>0 0.002<br>2 3 4 5 6 7 8 9 10 3 6 9 12 15 18 21 24 27 30<br>VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>1.8 1000<br>ID = 30 A VGS = 0 V<br>1.6 VGS = 10 V<br>TJ = 150 ° C<br>1.4 100<br>1.2<br>TJ = 100 ° C<br>1.0 10<br>0.8<br>0.6 1<br>−50 −25 0 25 50 75 100 125 150 5 10 15 20 25 30<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A) , DRAIN CURRENT (A)<br>ID ID<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (nA)<br>, DRAIN−TO−SOURCE RES- IDSS<br>ISTANCE (NORMALIZED)<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


**Figure 5. On−Resistance Variation with Temperature** 

**Figure 6. Drain−to−Source Leakage Current vs. Voltage** 

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**4** 

**NTMFS4823N** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [244 x 591] intentionally omitted <==**

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1400<br>V GS  = 0 V<br>1200 T J  = 25 ° C<br>1000<br>C iss<br>800<br>600<br>400 C oss<br>200 C rss<br>0<br>0 5 10 15 20 25 30<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>Figure 7. Capacitance Variation<br>1000<br>VDD = 15 V<br>ID = 30 A<br>VGS = 11.5 V<br>100<br>tr<br>td(off)<br>10 td(on)<br>tf<br>1<br>1 10 100<br>RG, GATE RESISTANCE ( � )<br>Figure 9. Resistive Switching Time Variation<br>vs. Gate Resistance<br>100<br>10  � s<br>100  � s<br>10 1 ms<br>R � JA = 22 ° C/W<br>10 ms<br>Single Pulse<br>1 TC = 25 ° C<br>Surface−mounted on FR4 board<br>using 1 in sq. pad size, 1 oz Cu, t < 10 s dc<br>0.1<br>RDS(on) Limit<br>Thermal Limit<br>Package Limit<br>0.01<br>0.1 1 10 100<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>C, CAPACITANCE (pF)<br>t, TIME (ns)<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

**==> picture [239 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
12<br>QT<br>10<br>8<br>6 VGS<br>4 Qgs Qgd<br>2 ID = 30 A<br>TJ = 25 ° C<br>0<br>0 2 4 6 8 10 12 14<br>Qg, TOTAL GATE CHARGE (nC)<br>, GATE−TO−SOURCE VOLTAGE (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge** 

**==> picture [239 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
30<br>25 VTJGS = 25= 0 V ° C<br>20<br>15<br>10<br>5<br>0<br>0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0<br>VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>, SOURCE CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 10. Diode Forward Voltage vs. Current** 

**==> picture [245 x 172] intentionally omitted <==**

**----- Start of picture text -----**<br>
30<br>ID = 24 A<br>25<br>20<br>15<br>10<br>5<br>0<br>25 50 75 100 125 150<br>TJ, STARTING JUNCTION TEMPERATURE ( ° C)<br>, SINGLE PULSE DRAIN−TO−<br>AS<br>E<br>SOURCE AVALANCHE ENERGY (mJ)<br>**----- End of picture text -----**<br>


**Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature** 

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**5** 

**NTMFS4823N** 

## **PACKAGE DIMENSIONS** 

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**----- Start of picture text -----**<br>
DFN5 5x6, 1.27P<br>(SO−8FL)<br>CASE 488AA<br>ISSUE G<br>2 X NOTES:<br>1. DIMENSIONING AND TOLERANCING PER<br>0.20 C ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETER.<br>a D A 3. DIMENSION D1 AND E1 DO NOT INCLUDE<br>MOLD FLASH PROTRUSIONS OR GATE<br>2 B 2 X BURRS.<br>D1 MILLIMETERS<br>0.20 C<br>DIM MIN NOM MAX<br>f o fe t —= A 0.90 1.00 1.10<br>A1 0.00 −−− 0.05<br>E1 4 X b 0.33 0.41 0.51<br>c 0.23 0.28 0.33<br>E D 5.15 BSC<br>2 D1 4.50 4.90 5.10<br>c D2 3.50 −−− 4.22<br>A1 E 6.15 BSC<br>HH a E1 5.50 5.80 6.10<br>P 1 2 3 T 4 ify) EEE E2 3.45 −−− 4.30<br>e 1.27 BSC<br>TOP VIEW G 0.51 0.61 0.71<br>3 X C K 1.20 1.35 1.50<br>0.10 C e SEATINGPLANE L1L 0.510.05 0.610.17 0.710.20<br>ma g , E e M 3.00 3.40 3.80<br>A DETAIL A 0  −−− 12<br>0.10 C Fae STYLE 1:<br>PIN 1. SOURCE<br>SIDE VIEW a DETAIL A SOLDERING FOOTPRINT* if}  2. 3. SOURCESOURCE —_ +<br> 4. GATE<br>3X 4X  5. DRAIN<br>8X b 1.270 0.750<br>4X<br>0.10 C A B 1.000<br>0.05 c L e/2<br>1 fe 4 0.965 b oo ts<br>K<br>1.330 2X<br>ft an a 0.905<br>E2 2X<br>PIN 5 M 0.495 4.530<br>(EXPOSED PAD) L1<br>3.200<br>0.475<br>G ac D2 and<br>2X<br>BOTTOM VIEW 1.530<br>rah Lo 4.560  eS<br>*For additional information on our Pb−Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>ON Semiconductor  and          are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).  SCILLC reserves the right to make changes without further notice<br>to any products herein.  SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability<br>arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.<br>“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.  All<br>operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.  SCILLC does not convey any license under its patent rights<br>nor the rights of others.  SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications<br>intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.  Should<br>Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,<br>and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death<br>associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.  SCILLC is an Equal<br>Opportunity/Affirmative Action Employer.  This literature is subject to all applicable copyright laws and is not for resale in any manner.<br>**----- End of picture text -----**<br>


## **PUBLICATION ORDERING INFORMATION** 

## **LITERATURE FULFILLMENT** : 

Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA **Phone** : 303−675−2175 or 800−344−3860 Toll Free USA/Canada **Fax** : 303−675−2176 or 800−344−3867 Toll Free USA/Canada **Email** : orderlit@onsemi.com 

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**NTMFS4823N/D** 

**6** 



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