# Dual MOSFET, N Channel, 30 V, 30.3 A, 2350 µohm ![Product image](https://novapart.co/image/farnell:3616923/) **URL**: https://novapart.co/products/NTMFD4901NFT3G/dual-mosfet-n-channel-30-v-303-a-2350-ohm **SKU**: NTMFD4901NFT3G **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Dual MOSFETs **Price**: €0.7920 **Stock**: 10+ ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | No SVHC (15-Jan-2018) | | No. Of Pins | 8Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | - | | Transistor Case Style | DFN | | Operating Temperature Max | 150°C | | Power Dissipation N Channel | 3.45W | | Power Dissipation P Channel | - | | Drain Source Voltage Vds N Channel | 30V | | Drain Source Voltage Vds P Channel | - | | Continuous Drain Current Id N Channel | 30.3A | | Continuous Drain Current Id P Channel | - | | Drain Source On State Resistance N Channel | 2350µohm | | Drain Source On State Resistance P Channel | - | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:3616923/) ## NTMFD4901NF ## MOSFET – Power, Dual, N-Channel with Integrated Schottky, SO8FL ## 30 V, High Side 18 A / Low Side 30 A **http://onsemi.com** ## **Features** **==> picture [476 x 484] intentionally omitted <==** **----- Start of picture text -----**
• Co−Packaged Power Stage Solution to Minimize Board Space V(BR)DSS RDS(ON) MAX ID MAX
• Low Side MOSFET with Integrated Schottky Q1 Top FET 6.5 m @ 10 V
18 A
• Minimized Parasitic Inductances 30 V 10 m @ 4.5 V
• Optimized Devices to Reduce Power Losses Q2 Bottom 2.35 m @ 10 V
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS FET 30 A
Compliant 30 V 3.5 m @ 4.5 V
Applications D1 (2, 3, 4, 9)
• DC−DC Converters
• System Voltage Rails
• Point of Load
(1) G1
S1/D2 (10)
(8) G2
S2 (5, 6, 7)
PIN CONNECTIONS
D1 4 5 S2
D1 3 9 10 6 S2
D1 2 D1 S1/D2 7 S2
G1 1 8 G2
lt
(Bottom View)
MARKING
DIAGRAM
1
DFN8 4901NF
CASE 506BX AYWZZ
ad
1
4901NF = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
**----- End of picture text -----**
## **ORDERING INFORMATION** See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Publication Order Number: **NTMFD4901NF/D** **1** © Semiconductor Components Industries, LLC, 2014 **May, 2019 − Rev. 6** ## **NTMFD4901NF** ## **MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise stated) |**MAXIMUM RATINGS**(TJ= 25°C unless otherwise stated)|**MAXIMUM RATINGS**(TJ= 25°C unless otherwise stated)|||||| |---|---|---|---|---|---|---| |**Parameter**||||**Symbol**|**Value**|**Unit**| |Drain−to−Source Voltage|||Q1|VDSS|30|V| |Drain−to−Source Voltage|||Q2|||| |Gate−to−Source Voltage|||Q1|VGS|±20|V| |Gate−to−Source Voltage|||Q2|||| |Continuous Drain Current R�JA(Note 1)|Steady
State|TA= 25°C|Q1|ID|13.5|A| |||TA= 85°C|||9.7|| |||TA= 25°C|Q2||23.4|| |||TA= 85°C|||16.9|| |Power Dissipation R�JA(Note 1)||TA= 25°C|Q1|PD|1.90|W| ||||Q2||2.07|| |Continuous Drain Current R�JA ≤10 s (Note 1)||TA= 25°C|Q1|ID|18.2|A| |||TA= 85°C|||13.1|| |||TA= 25°C|Q2||30.3|| |||TA= 85°C|||21.8|| |Power Dissipation R�JA ≤10 s (Note 1)||TA= 25°C|Q1|PD|3.45|W| ||||Q2||3.45|| |Continuous Drain Current R�JA(Note 2)||TA= 25°C|Q1|ID|10.3|A| |||TA= 85°C|||7.4|| |||TA= 25°C|Q2||17.9|| |||TA= 85°C|||12.9|| |Power Dissipation R�JA(Note 2)||TA= 25°C|Q1|PD|1.10|W| ||||Q2||1.20|| |Pulsed Drain Current||TA= 25°C
tp= 10�s|Q1|IDM|60|A| ||||Q2||100|| |Operating Junction and Storage Temperature|||Q1|TJ, TSTG|−55 to +150|°C| ||||Q2|||| |Source Current (Body Diode)|||Q1|IS|3.4|A| ||||Q2||4.9|| |Drain to Source dV/dt||||dV/dt|6|V/ns| |Single Pulse Drain−to−Source Avalanche Energy (TJ= 25C, VDD
= 50 V, VGS= 10 V, IL= XX Apk, L = 0.1 mH, RG= 25�)||24 A|Q1|EAS|28.8|mJ| |||48 A|Q2|EAS|115|| |Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)||||TL|260|°C| Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface−mounted on FR4 board using 1 sq−in pad, 2 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size of 100 mm[2] . **http://onsemi.com** **2** **NTMFD4901NF** ## **THERMAL RESISTANCE MAXIMUM RATINGS** |**THERMAL RESISTANCE MAXIMUM RATINGS**||||| |---|---|---|---|---| |**Parameter**|**FET**|**Symbol**|**Value**|**Unit**| |Junction−to−Ambient – Steady State (Note 3)|Q1|R�JA|65.9|°C/W| ||Q2||60.5|| |Junction−to−Ambient – Steady State (Note 4)|Q1|R�JA|113.2|| ||Q2||104|| |Junction−to−Ambient – (t≤10 s) (Note 3)|Q1|R�JA|36.2|| ||Q2||36.2|| 3. Surface−mounted on FR4 board using 1 sq−in pad, 2 oz Cu. 4. Surface−mounted on FR4 board using the minimum recommended pad size of 100 mm[2] . ## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) |**ELECTRICAL CHARACTE**|**RISTIC**|**S**(TJ= 25°C|unless otherwise specified)|unless otherwise specified)||||| |---|---|---|---|---|---|---|---|---| |**Parameter**|**FET**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**| |**OFF CHARACTERISTICS**||||||||| |Drain−to−Source Break-
down Voltage|Q1|V(BR)DSS|VGS= 0 V, ID= 250�A||30|||V| ||Q2||VGS= 0 V, ID= 1 mA||30|||| |Drain−to−Source Break-
down Voltage Temperature
Coefficient|Q1|V(BR)DSS
/ TJ||||18||mV /
°C| ||Q2|||||15||| |Zero Gate Voltage Drain
Current|Q1|IDSS|VGS= 0 V,
VDS= 24 V|TJ= 25°C|||1|�A| |||||TJ= 125°C|||10|| ||Q2||VGS= 0 V,
VDS= 24 V|TJ= 25°C|||500|| |Gate−to−Source Leakage
Current|Q1|IGSS|VGS= 0 V, VDS =±20 V||||±100|nA| ||Q2||||||±100|| |**ON CHARACTERISTICS**(Note 5)||||||||| |Gate Threshold Voltage|Q1|VGS(TH)|VGS= VDS, ID= 250�A||1.2||2.2|V| ||Q2||||1.2||2.2|| |Negative Threshold Temper-
ature Coefficient|Q1|VGS(TH)/
TJ||||4.5||mV /
°C| ||Q2|||||4.0||| |Drain−to−Source On Resist-
ance|Q1|RDS(on)|VGS= 10 V|ID= 10 A||5.2|6.5|m�| ||||VGS= 4.5 V|ID= 10 A||8.0|10|| ||Q2||VGS= 10 V|ID= 20 A||1.9|2.35|| ||||VGS= 4.5 V|ID= 20 A||2.8|3.5|| |Forward Transconductance|Q1|gFS|VDS= 1.5 V, ID= 10 A|||28||S| ||Q2|||||45||| 5. Pulse Test: pulse width ≤ 300 � s, duty cycle ≤ 2%. 6. Switching characteristics are independent of operating junction temperatures. **http://onsemi.com** **3** ## **NTMFD4901NF** **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) |**ELECTRICAL CHARACTE**|**RISTIC**|**S**(TJ= 25°C|unless otherwise specified)||||| |---|---|---|---|---|---|---|---| |**Parameter**|**FET**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**| |**CHARGES, CAPACITANCES**|**& GATE RESISTANCE**||||||| |Input Capacitance|Q1|CISS|VGS= 0 V, f = 1 MHz, VDS= 15 V||1150||pF| ||Q2||||2950||| |Output Capacitance|Q1|COSS|||360||| ||Q2||||1100||| |Reverse Capacitance|Q1|CRSS|||105||| ||Q2||||82||| |Total Gate Charge|Q1|QG(TOT)|VGS= 4.5 V, VDS= 15 V; ID= 10 A||9.7||nC| ||Q2||||20||| |Threshold Gate Charge|Q1|QG(TH)|||1.1||| ||Q2||||2.7||| |Gate−to−Source Charge|Q1|QGS|||3.3||| ||Q2||||7.3||| |Gate−to−Drain Charge|Q1|QGD|||3.7||| ||Q2||||5.3||| |Total Gate Charge|Q1|QG(TOT)|VGS= 10 V, VDS= 15 V; ID= 10 A||19.1||nC| ||Q2||||42.7||| |**SWITCHING CHARACTERISTICS**(Note 6)|||||||| |Turn−On Delay Time|Q1|td(ON)|VGS= 4.5 V, VDS= 15 V,
ID= 10 A, RG= 3.0�||9.0||ns| ||Q2||||14||| |Rise Time|Q1|tr|||15||| ||Q2||||16||| |Turn−Off Delay Time|Q1|td(OFF)|||14||| ||Q2||||25||| |Fall Time|Q1|tf|||4.0||| ||Q2||||7.0||| |**SWITCHING CHARACTERISTICS**(Note 6)|||||||| |Turn−On Delay Time|Q1|td(ON)|VGS= 10 V, VDS= 15 V,
ID= 10 A, RG= 3.0�||6.0||ns| ||Q2||||10||| |Rise Time|Q1|tr|||14||| ||Q2||||15||| |Turn−Off Delay Time|Q1|td(OFF)|||17||| ||Q2||||32||| |Fall Time|Q1|tf|||3.0||| ||Q2||||5.0||| 5. Pulse Test: pulse width ≤ 300 � s, duty cycle ≤ 2%. 6. Switching characteristics are independent of operating junction temperatures. **http://onsemi.com** **4** **NTMFD4901NF** **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) |**ELECTRICAL CHARACTE**|**RISTIC**|**S**(TJ= 25°C|unless otherwise specified)|unless otherwise specified)||||| |---|---|---|---|---|---|---|---|---| |**Parameter**|**FET**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**| |**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||| |Forward Voltage|Q1|VSD|VGS= 0 V,
IS= 3 A|TJ= 25°C||0.75|1.0|V| |||||TJ= 125°C||0.62||| ||Q2||VGS= 0 V,
IS= 2 A|TJ= 25°C||0.45|0.70|| |||||TJ= 125°C||0.37||| |Reverse Recovery Time|Q1|tRR|VGS= 0 V, dIS/dt=|100 A/�s, IS= 3 A||23||ns| ||Q2|||||40||| |Charge Time|Q1|ta||||12||| ||Q2|||||21||| |Discharge Time|Q1|tb||||11||| ||Q2|||||19||| |Reverse Recovery Charge|Q1|QRR||||12||nC| ||Q2|||||40||| |**PACKAGE PARASITIC VALUES**||||||||| |Source Inductance|Q1|LS|TA=|25°C||0.38||nH| ||Q2|||||0.65||| |Drain Inductance|Q1|LD||||0.054||nH| ||Q2|||||0.007||| |Gate Inductance|Q1|LG||||1.5||nH| ||Q2|||||1.5||| |Gate Resistance|Q1|RG||||0.8||�| ||Q2|||||0.8||| 5. Pulse Test: pulse width ≤ 300 � s, duty cycle ≤ 2%. 6. Switching characteristics are independent of operating junction temperatures. ## **ORDERING INFORMATION** |**ORDERING INFORMATION**||| |---|---|---| |**Device**|**Package**|**Shipping**†| |NTMFD4901NFT1G|DFN8
(Pb−Free)|1500 / Tape & Reel| |NTMFD4901NFT3G|DFN8
(Pb−Free)|5000 / Tape & Reel| - †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. **http://onsemi.com** **5** **NTMFD4901NF** ## **TYPICAL CHARACTERISTICS − Q1** **==> picture [239 x 158] intentionally omitted <==** **----- Start of picture text -----**
40
3.8 V 3.6 V 3.4 V
35
4.5 V
30
10 V TJ = 25 ° C
25 3.2 V
20
15 3.0 V
10
5 2.8 V
VGS = 2.4 V
0
0 1 2 3 4 5
, DRAIN CURRENT (A)
ID
**----- End of picture text -----**
**==> picture [150 x 9] intentionally omitted <==** **----- Start of picture text -----**
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
**----- End of picture text -----**
**Figure 1. On−Region Characteristics** **==> picture [238 x 158] intentionally omitted <==** **----- Start of picture text -----**
50
45 VDS ≥ 5 V
40
35
30
TJ = 125 ° C
25
20
15
10 TJ = 25 ° C
5 TJ = −55 ° C
0
0 1 2 3 4
, DRAIN CURRENT (A)
ID
**----- End of picture text -----**
VGS, GATE−TO−SOURCE VOLTAGE (V) **Figure 2. Transfer Characteristics** **==> picture [490 x 397] intentionally omitted <==** **----- Start of picture text -----**
0.020 0.010
0.018 TIDJ = 10 A = 25 ° C 0.009 T = 25 ° C
0.016
0.008
0.014
VGS = 4.5 V
0.012 0.007
0.010 0.006
0.008
0.005
0.006 VGS = 10 V
0.004
0.004
0.002 0.003
2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 35 40
VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and
Resistance Gate Voltage
1.8 10,000
1.6 VIDGS = 10 A = 10 V TJ = 150 ° C
1.4 1,000
1.2 TJ = 125 ° C
1.0 100
0.8
VGS = 0 V
0.6 10
−50 −25 0 25 50 75 100 125 150 0 5 10 15 20 25 30
TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
) � ) �
, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (
DS(on) DS(on)
R R
, LEAKAGE (nA)
, DRAIN−TO−SOURCE
IDSS
DS(on)
R RESISTANCE (NORMALIZED)
**----- End of picture text -----**
**Figure 5. On−Resistance Variation with Temperature** **==> picture [187 x 20] intentionally omitted <==** **----- Start of picture text -----**
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
**----- End of picture text -----**
**http://onsemi.com** **6** **NTMFD4901NF** ## **TYPICAL CHARACTERISTICS − Q1** **==> picture [241 x 173] intentionally omitted <==** **----- Start of picture text -----**
1600
TJ = 25 ° C
1400 Ciss V GS = 0 V
1200
1000
800
Coss
600
400
Crss
200
0
0 5 10 15 20 25 30
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
**----- End of picture text -----**
**==> picture [241 x 156] intentionally omitted <==** **----- Start of picture text -----**
11
QT
10
9
8
7
6
5
4 Qgs Qgd
3
2
1 TIDJ = 10 A = 25 ° C
0
0 2 4 6 8 10 12 14 16 18 20
, GATE−TO−SOURCE VOLTAGE (V)
GS
V
**----- End of picture text -----**
**==> picture [119 x 9] intentionally omitted <==** **----- Start of picture text -----**
Qg, TOTAL GATE CHARGE (nC)
**----- End of picture text -----**
**Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge** **Figure 7. Capacitance Variation** **==> picture [240 x 174] intentionally omitted <==** **----- Start of picture text -----**
10
9 VGS = 0 VGS = 0 V = 0 V
8
7
6
5
4
3
2 TJ = 25 ° C
1
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
, SOURCE CURRENT (A)
ISS
**----- End of picture text -----**
**==> picture [356 x 397] intentionally omitted <==** **----- Start of picture text -----**
1000
VGS = 10 V 9 VGS = 0 VGS = 0 V = 0 V
VDD = 15 V
ID = 10 A 8
td(off) 7
100
6
tr 5
4
10 td(on) 3
2
tf
1
1 0
1 10 100 0.0 0.1 0.2 0.3
RG, GATE RESISTANCE ( � )
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
1000
100
10 10 � s
100 � s
0 V ≤ VGS ≤ 20 V 1 ms
1 SINGLE PULSE
10 ms
TA = 25 ° C
Single Pulse
0.1
RDS(on) LIMIT dc
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.01 0.1 1 10 100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
t, TIME (ns)
, SOURCE CURRENT (A)
ISS
, DRAIN CURRENT (A)
ID
**----- End of picture text -----**
**Figure 10. Diode Forward Voltage vs. Current** **Figure 11. Maximum Rated Forward Biased Safe Operating Area** **http://onsemi.com** **7** **NTMFD4901NF** ## **TYPICAL CHARACTERISTICS − Q1** **==> picture [492 x 184] intentionally omitted <==** **----- Start of picture text -----**
100
D = 0.5
0.2
10 0.1
0.05
0.02
1
0.01
0.1
SINGLE PULSE
0.01
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
t, TIME (s)
Figure 12. Thermal Response
JA
�
C/W)
( °
Thermal Resistance, R
**----- End of picture text -----**
**http://onsemi.com** **8** **NTMFD4901NF** ## **TYPICAL CHARACTERISTICS − Q2** **==> picture [491 x 594] intentionally omitted <==** **----- Start of picture text -----**
50 60
45 3.4 V 3.2 V TJ = 25 ° C VDS ≥ 5 V
3.0 V 50
40 4.5 V
10 V
35
40
30
TJ = 125 ° C
25 30
20 2.8 V
20
15
10 10 TJ = 25 ° C
5 VGS = 2.4 V TJ = −55 ° C
0 0
0 1 2 3 4 5 0 0.5 1 1.5 2 2.5 3 3.5
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 13. On−Region Characteristics Figure 14. Transfer Characteristics
0.020 0.0040
ID = 10 A
TJ = 25 ° C 0.0035
0.015
0.0030 V GS = 4.5 V
0.010 0.0025
0.0020
0.005
VGS = 10 V
0.0015
0 0.0010
2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 35 40 45 50
VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 15. On−Resistance vs. Gate−to−Source Figure 16. On−Resistance vs. Drain Current
Resistance and Gate Voltage
1.8 1E−2
ID = 20 A
1.6 VGS = 10 V TJ = 150 ° C
1E−3 TJ = 125 ° C
1.4
1.2 1E−4
1.0
1E−5
0.8
TJ = 25 ° C
VGS = 0 V
0.6 1E−6
−50 −25 0 25 50 75 100 125 150 0 5 10 15 20 25 30
TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
, DRAIN CURRENT (A) , DRAIN CURRENT (A)
ID ID
) � ) �
, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (
DS(on) DS(on)
R R
, LEAKAGE (A)
, DRAIN−TO−SOURCE
IDSS
DS(on)
R RESISTANCE (NORMALIZED)
**----- End of picture text -----**
**Figure 17. On−Resistance Variation with Temperature** **Figure 18. Drain−to−Source Leakage Current vs. Voltage** **http://onsemi.com** **9** **NTMFD4901NF** ## **TYPICAL CHARACTERISTICS − Q2** **==> picture [241 x 156] intentionally omitted <==** **----- Start of picture text -----**
4000
TJ = 25 ° C
3500 Ciss V GS = 0 V
3000
2500
2000
Coss
1500
1000
500 C rss
0
0 5 10 15 20 25 30
C, CAPACITANCE (pF)
**----- End of picture text -----**
**==> picture [151 x 9] intentionally omitted <==** **----- Start of picture text -----**
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
**----- End of picture text -----**
**Figure 19. Capacitance Variation** **==> picture [244 x 172] intentionally omitted <==** **----- Start of picture text -----**
1000
VGS = 10 V
VDD = 15 V
ID = 10 A td(off)
100
tr
td(on)
10
tf
1
1 10 100
RG, GATE RESISTANCE ( � )
t, TIME (ns)
**----- End of picture text -----**
**Figure 21. Resistive Switching Time Variation vs. Gate Resistance** **==> picture [239 x 156] intentionally omitted <==** **----- Start of picture text -----**
11
QT
10
9
8
7
6
5
4 Qgd
Qgs
3
2
1 TIDJ = 10 A = 25 ° C
0
0 5 10 15 20 25 30 35 40 45
, GATE−TO−SOURCE VOLTAGE (V)
GS
V
**----- End of picture text -----**
**==> picture [119 x 9] intentionally omitted <==** **----- Start of picture text -----**
Qg, TOTAL GATE CHARGE (nC)
**----- End of picture text -----**
**Figure 20. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge** **==> picture [240 x 174] intentionally omitted <==** **----- Start of picture text -----**
10
9 VGS = 0 V
TJ = 25 ° C
8
7
6
5
4
3
2
1
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
, SOURCE CURRENT (A)
IS
**----- End of picture text -----**
**Figure 22. Diode Forward Voltage vs. Current** **==> picture [243 x 171] intentionally omitted <==** **----- Start of picture text -----**
1000
100
10 10 � s
100 � s
0 V ≤ VGS ≤ 20 V 1 ms
1 SINGLE PULSE
TA = 25 ° C 10 ms
Single Pulse
0.1
RDS(on) LIMIT dc
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.01 0.1 1 10 100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
, DRAIN CURRENT (A)
ID
**----- End of picture text -----**
**Figure 23. Maximum Rated Forward Biased Safe Operating Area** **http://onsemi.com** **10** ## **NTMFD4901NF** ## **TYPICAL CHARACTERISTICS − Q2** **==> picture [492 x 184] intentionally omitted <==** **----- Start of picture text -----**
100
D = 0.5
0.2
10
0.1
0.05
0.02
1
0.01
0.1
SINGLE PULSE
0.01
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
t, TIME (s)
Figure 24. Thermal Response
JA
�
C/W)
( °
Thermal Resistance, R
**----- End of picture text -----**
**http://onsemi.com** **11** MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual−Asymmetrical)** CASE 506BX ISSUE D 1 ## DATE 24 JUN 2014 **==> picture [42 x 7] intentionally omitted <==** **----- Start of picture text -----**
SCALE 2:1
**----- End of picture text -----**
NOTES: **==> picture [484 x 348] intentionally omitted <==** **----- Start of picture text -----**
2X
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
0.20 C 2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
D A BETWEEN 0.15 AND 0.25 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PADS AS WELL AS THE
TERMINALS.
D1 B 2X 5. DIMENSIONS b AND L ARE MEASURED AT THE PACKAGE SUR-
NOTE 6 FACE
8 7 6 5 0.20 C 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
7. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
PIN ONE E1 E 4X MILLIMETERS
IDENTIFIER h DIM MIN MAX
ÉÉ A 0.90 1.10
A1 0.00 0.05
ÉÉ c A1 b 0.41 0.61
1 2 3 4 NOTE 7 b1 0.41 0.61
c 0.23 0.33
TOP VIEW D 5.00 5.30
D1 4.50 5.10 GENERIC
0.10 C D2 3.50 4.22 MARKING DIAGRAM*
DETAIL A E 6.00 6.30
A E1 5.50 6.10 1
0.10 C E2 2.27 2.67
NOTE 4 SIDE VIEW DETAIL AC [SEATING] PLANE E3he 0.82−−−1.27 BSC1.2212 � XXXXXXAYWZZ
k 0.39 0.59
k1 0.56 0.76
e
DETAIL B k2 0.73 0.93 XXXXXX = Specific Device Code
e/2 L 0.35 0.55 A = Assembly Location
8X b
1 4 Y = Year
E3
0.10 C A B
W = Work Week
k 0.05 C NOTE 3 ZZ = Lot Traceability
k1 *This information is generic. Please refer
E2
0.10 to device data sheet for actual part
REF 6X b1 marking.
NOTE 3
k2 8 5 DETAIL B RECOMMENDED
8X L
D2 SOLDERING FOOTPRINT*
BOTTOM VIEW
NOTE 6
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**==> picture [169 x 135] intentionally omitted <==** **----- Start of picture text -----**
5.35 8X
PACKAGEOUTLINE 8X 0.69
0.64
1.97
2.68
6.45
2.33
1.22
4X 0.69 1.27
PITCH
DIMENSION: MILLIMETERS
**----- End of picture text -----**
- STYLE 1: PIN 1. GATE 1 2. DRAIN 1 3. DRAIN 1 4. DRAIN 1 5. SOURCE 2 6. SOURCE 2 7. SOURCE 2 8. GATE 2 9. DRAIN 1 - 10. SOURCE 1/DRAIN 2 - *For additional information on our Pb−Free strategy and soldering details, please download the **onsemi** Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. **==> picture [493 x 37] intentionally omitted <==** **----- Start of picture text -----**
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON54291E Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL−ASYMMETRICAL) PAGE 1 OF 1
**----- End of picture text -----**
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