# Power MOSFET, N Channel, 30 V, 7.8 A, 0.035 ohm, WDFN, Surface Mount

![Product image](https://novapart.co/image/farnell:2317891/)

**URL**: https://novapart.co/products/NTLJS4114NT1G/power-mosfet-n-channel-30-v-78-a-0035-ohm-wdfn
**SKU**: NTLJS4114NT1G
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.2580
**Stock**: 10+

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:7.8A; Drain Source Voltage Vds:30V; On Resistance Rds(on):0.0203ohm; Rds(on) Test Voltage Vgs:4.5V; Threshold Voltage Vgs:550mV;

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 6Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 3.3W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 4.5V |
| Transistor Case Style | WDFN |
| Drain Source Voltage Vds | 30V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 7.8A |
| Drain Source On State Resistance | 0.035ohm |
| Gate Source Threshold Voltage Max | 550mV |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2317891/)

## NTLJS4114N MOSFET – Power, Single, N-Channel, Cool, WDFN, UL ~~—~~ 2X2 mm 30 V, 7.8 A 

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## **Features** 

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|||||
|---|---|---|---|
|V(BR)DSS|RDS(on) MAX|ID MAX|(Note 1)|
|35 m|@ 4.5 V|
|30 V|45 m|@ 2.5 V|7.8 A|
|55 m|@ 1.8 V|
|=|

**----- End of picture text -----**<br>


- WDFN Package Provides Exposed Drain Pad for Excellent Thermal Conduction 

- 2x2 mm Footprint Same as SC−88 

- Lowest RDS(on) in 2x2 mm Package 

- 1.8 V RDS(on) Rating for Operation at Low Voltage Logic Level Gate Drive 

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S<br>G<br>D<br>**----- End of picture text -----**<br>


- Low Profile (< 0.8 mm) for Easy Fit in Thin Environments 

- This is a Pb−Free Device 

## **Applications** 

- DC−DC Conversion 

- Boost Circuits for LED Backlights 

- Optimized for Battery and Load Management Applications in Portable Equipment such as, Cell Phones, PDA’s, Media Players, etc. 

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N−CHANNEL MOSFET<br>**----- End of picture text -----**<br>


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S MARKING<br>D<br>DIAGRAM<br>WDFN6 1 6<br>JAM<br>CASE 506AP 2 5<br>Pin 1 STYLE 1 3 4<br>JA = Specific Device Code<br>M = Date Code<br>. = Pb−Free Package<br>(Note: Microdot may be in either location)<br>**----- End of picture text -----**<br>


- Low Side Load Switch for Noisy Environment 

## **MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) 

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|||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
|Parameter|Symbol|Value|Unit|Pin 1|
|Drain−to−Source Voltage|VDSS|30|V|JA|= Specific Device Code|
|M|= Date Code|
|e|Gate−to−Source Voltage|s|V|es|GS|±|es|12|V|.|= Pb−Free Package|
|Continuous Drain|Steady|TA = 25|°|C|ID|6.0|A|(Note: Microdot may be in either location)|
|Current (Note 1)|State|TA = 85|°|C|4.4|
|PIN CONNECTIONS|
||Leo|t|≤|5 s|TA = 25|°|C|7.8|
|Power Dissipation|Steady|PD|1.92|W|
|(Note 1)|State|TA = 25|°|C|D|1|6|
|t|≤|5 s|3.3|
|Continuous Drain|TA = 25|°|C|ID|3.6|A|D|2|D|5|
|Current (Note 2)|SteadyState|TA = 85|°|C|2.6|G|3|S|4|
|Power Dissipation(Note 2)|TA = 25|°|C|PD|0.70|W|
|a|eee|eeeee|
|(Top View)|
|ee|Pulsed Drain Current|ee|tp = 10 s|Oe|IDM|es Gs|28|A|
|Operating Junction and Storage Temperature|TJ, TSTG|−55 to|°|C|ORDERING INFORMATION|
|150|
|ee|Device|Package|
|Source Current (Body Diode) (Note 2)|IS|3.0|A|
|esee|Ge|NTLJS4114NT1G|WDFN6|
|Lead Temperature for Soldering Purposes(1/8|″|from case for 10 s)|TL|260|°|C|NTLJS4114NTAG|(Pb−FreeWDFN6Pb−FreeWDFN6WDFN6|)|
|Stresses exceeding Maximum Ratings may damage the device. Maximum|(Pb−Free)|
|eee —|
|Ratings are stress ratings only. Functional operation above the Recommended|
|†For information on tape and reel specifications,|
|Operating Conditions is not implied. Extended exposure to stresses above the|
|including part orientation and tape sizes, please|
|Recommended Operating Conditions may affect device reliability.|

**----- End of picture text -----**<br>


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PIN CONNECTIONS<br>D 1 6 D<br>D 2 D 5 D<br>G 3 S 4 S<br>(Top View)<br>ORDERING INFORMATION<br>Device Package Shipping [†]<br>NTLJS4114NT1G WDFN6 3000/Tape & Reel<br>NTLJS4114NTAG (Pb−FreeWDFN6Pb−FreeWDFN6WDFN6 ) 3000/Tape & Reel<br>(Pb−Free)<br>+<br>†For information on tape and reel specifications,<br>including part orientation and tape sizes, please<br>refer to our Tape and Reel Packaging Specification<br>Brochure, BRD8011/D.<br>**----- End of picture text -----**<br>


Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2012 **May, 2019 − Rev. 3** 

**NTLJS4114N/D** 

## **NTLJS4114N** 

1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 

2. Surface Mounted on FR4 Board using the minimum recommended pad size of 30 mm2, 2 oz Cu. 

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**NTLJS4114N** 

## **THERMAL RESISTANCE RATINGS** 

|**THERMAL RESISTANCE RATINGS**||||
|---|---|---|---|
|**Parameter**|**Symbol**|**Max**|**Unit**|
|Junction−to−Ambient – Steady State (Note 3)|R�JA|65|°C/W|
|Junction−to−Ambient – t≤5 s (Note 3)|R�JA|38||
|Junction−to−Ambient – Steady State Min Pad (Note 4)|R�JA|180||



3. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 

4. Surface Mounted on FR4 Board using the minimum recommended pad size (30 mm[2] , 2 oz Cu). 

## **MOSFET ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) 

|**Parameter**|**Symbol**|**Test Conditions**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID= 250�A||30|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/TJ|ID= 250�A, Ref to 25°C|||20||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VDS= 24 V, VGS= 0 V|TJ= 25°C|||1.0|�A|
||||TJ= 85°C|||10||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS=±12 V||||±100|nA|
|**ON CHARACTERISTICS**(Note 5)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 250�A||0.4|0.55|1.0|V|
|Negative Gate Threshold<br>Temperature Coefficient|VGS(TH)/TJ||||3.18||mV/°C|
|Drain−to−Source On−Resistance|RDS(on)|VGS= 4.5 V, ID= 2.0 A|||20.3|35|m�|
|||VGS= 2.5 V, ID= 2.0 A|||25.8|45||
|||VGS= 1.8 V, ID= 1.8 A|||35.2|55||
|Forward Transconductance|gFS|VDS= 16 V, ID= 2.0 A|||8||S|
|**CHARGES, CAPACITANCES AND GATE RESISTANCE**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1.0 MHz,<br>VDS= 15 V|||650||pF|
|Output Capacitance|COSS||||115.5|||
|Reverse Transfer Capacitance|CRSS||||70|||
|Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 15 V,<br>ID= 2.0 A|||8.5|13|nC|
|Threshold Gate Charge|QG(TH)||||0.6|||
|Gate−to−Source Charge|QGS||||0.9|||
|Gate−to−Drain Charge|QGD||||2.1|||
|Gate Resistance|RG||||3.0||�|
|**SWITCHING CHARACTERISTICS**(Note 6)||||||||
|Turn−On Delay Time|td(ON)|VGS= 4.5 V, VDD= 15 V,<br>ID= 2.0 A, RG= 3.0�|||5||ns|
|Rise Time|tr||||9|||
|Turn−Off Delay Time|td(OFF)||||20|||
|Fall Time|tf||||4|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Recovery Voltage|VSD|VGS= 0 V, IS = 2.0 A|TJ= 25°C||0.71|1.2|V|
||||TJ= 85°C||0.58|||
|Reverse Recovery Time|tRR|VGS= 0 V, dISD/dt= 100 A/�s,<br>IS= 1.0 A|||14|35|ns|
|Charge Time|ta||||8.0|||
|Discharge Time|tb||||6.0|||
|Reverse Recovery Time|QRR||||5.0||nC|



5. Pulse Test: Pulse Width � 300 � s, Duty Cycle � 2%. 

6. Switching characteristics are independent of operating junction temperatures. 

**http://onsemi.com** 

**3** 

**NTLJS4114N** 

## **TYPICAL PERFORMANCE CURVES** (TJ = 25 ° C unless otherwise noted) 

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7 8<br>6 VGS = 1.6 V to 8 V 1.5 V TJ = 25 ° C VDS ≥  10 V<br>6<br>5<br>1.4 V<br>4<br>4<br>3<br>1.3 V TJ = 25 ° C<br>2<br>2<br>1.2 V<br>1 TJ = 100 ° C TJ = −55 ° C<br>0 0<br>0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 0 0.5 1 1.5 2 2.5 3<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>0.03 0.05<br>VGS = 4.5 V TJ = 25 ° C<br>TJ = 100 ° C<br>0.025 0.04<br>VGS = 1.8 V<br>TJ = 25 ° C<br>0.02 0.03<br>VGS = 2.5 V<br>0.015 T J  = −55 ° C 0.02<br>VGS = 4.5 V<br>0.01 0.01<br>0.005 0<br>1.0 1.5 2.0 2.5 3.0 1 2 3 4 5 6<br>ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance versus Drain Current Figure 4. On−Resistance versus Drain Current<br>and Gate Voltage<br>1.6 1.0E−04<br>ID = 2 A VGS = 0 V<br>1.4 VGS = 4.5 V TJ = 150 ° C<br>1.0E−05<br>1.2 TJ = 125 ° C<br>1.0<br>1.0E−06<br>0.8 TJ = 85 ° C<br>0.6 1.0E−07<br>−50 −25 0 25 50 75 100 125 150 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current<br>Temperature versus Voltage<br>, DRAIN CURRENT (A) , DRAIN CURRENT (A)<br>ID ID<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (A)<br>(NORMALIZED) IDSS<br>, DRAIN−TO−SOURCE RESISTANCE<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


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**4** 

**NTLJS4114N** 

## **TYPICAL PERFORMANCE CURVES** (TJ = 25 ° C unless otherwise noted) 

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5 20<br>1600 VDS = 0 V QT<br>VTJGS = 25 = 0 V ° C 4 VDS VGS 16<br>Ciss<br>1000 3 12<br>QGD<br>2 QGS 8<br>400<br>Coss<br>1 4<br>Crss TIDJ = 2 A = 25 ° C<br>−200 0 0<br>5 0 5 10 15 20 25 30 0 4 8<br>VGS VDS QG, TOTAL GATE CHARGE (nC)<br>C, CAPACITANCE (pF)<br>VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)<br>**----- End of picture text -----**<br>


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GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)<br>**----- End of picture text -----**<br>


**Figure 7. Capacitance Variation** 

**Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge** 

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1000<br>V DD  = 15 V<br>I D  = 3.0 A<br>VGS = 4.5 V td(off)<br>100 tf<br>tr<br>td(on)<br>10<br>1<br>1 10 100<br>RG, GATE RESISTANCE (OHMS)<br>t, TIME (ns)<br>**----- End of picture text -----**<br>


**Figure 9. Resistive Switching Time Variation versus Gate Resistance** 

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4<br>VGS = 0 V<br>T J  = 25 ° C<br>3<br>2<br>1<br>0<br>0.3 0.4 0.5 0.6 0.7 0.8<br>VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>IS, SOURCE CURRENT (AMPS)<br>**----- End of picture text -----**<br>


**Figure 10. Diode Forward Voltage versus Current** 

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100<br>See Note 2 on Page 1<br>10  � s<br>10<br>100  � s<br>1 ms<br>1<br>10 ms<br>SINGLE PULSE<br>TC = 25 ° C<br>TJ = 150 ° C<br>0.1<br>RDS(on) LIMIT<br>THERMAL LIMIT<br>dc<br>PACKAGE LIMIT<br>0.01<br>0.1 1 10 100<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>ID, DRAIN CURRENT (AMPS)<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

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**5** 

**NTLJS4114N** 

## **TYPICAL PERFORMANCE CURVES** (TJ = 25 ° C unless otherwise noted) 

**==> picture [475 x 186] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000<br>D = 0.5<br>100<br>0.2<br>0.1<br>0.05<br>10<br>0.02 P(pk) See Note 2 on Page 2<br>0.01 D CURVES APPLY FOR POWER<br>PULSE TRAIN SHOWN<br>1<br>t1 READ TIME AT t1<br>t2 TJ(pk) − TA = P(pk) R � JA(t)<br>SINGLE PULSE DUTY CYCLE, D = t1/t2<br>0.1<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>t, TIME (s)<br>EFFECTIVE TRANSIENT THERMAL RESISTANCE<br>**----- End of picture text -----**<br>


**Figure 12. Thermal Response** 

� Cool is a trademark of Semiconductor Components Industries, LLC (SCILLC). 

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**6** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

## **WDFN6 2x2** 

CASE 506AP−01 ISSUE B 

## DATE 26 APR 2006 

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SCALE 4:1 NOTES:<br>1. DIMENSIONING AND TOLERANCING PER ASME<br>Y14.5M, 1994.<br>D A 2. CONTROLLING DIMENSION: MILLIMETERS.<br>B 3. DIMENSION b APPLIES TO PLATED TERMINAL AND<br>IS MEASURED BETWEEN 0.15 AND 0.20mm FROM<br>TERMINAL.<br>4. COPLANARITY APPLIES TO THE EXPOSED PAD AS<br>WELL AS THE TERMINALS.<br>1. CENTER TERMINAL LEAD IS OPTIONAL. TERMINAL<br>LEAD IS CONNECTED TO TERMINAL LEAD # 4.<br>oT<br>PIN ONE ÍÍÍ E 2. PINS 1, 2, 5 AND 6 ARE TIED TO THE FLAG. MILLIMETERS<br>REFERENCE DIM MIN MAX<br>ÍÍÍ A 0.70 0.80<br>A1 0.00 0.05<br>2X 0.10 ÍÍÍ C ff A3 0.20 REF<br>b 0.25 0.35<br>b1 0.51 0.61<br>D 2.00 BSC<br>2X 0.10 C D2 1.00 1.20<br>E 2.00 BSC<br>E2 1.10 1.30<br>A3 e 0.65 BSC<br>0.10 C K 0.15 REF<br>L 0.20 0.30<br>A L2 0.20 0.30<br>J 0.27 REF<br>an J1 0.65 REF<br>7X 0.08 C<br>A1<br>GENERIC<br>os C SEATINGPLANE MARKING DIAGRAM*<br>D2 4X<br>1 6<br>e<br>2 XX M 5<br>6X L 1 3 L2 3 ; 4<br>b1 6X XX = Specific Device Code<br>M = Date Code<br>0.10 C A B<br>E2 *This information is generic. Please refer to<br>0.05 C device data sheet for actual part marking.<br>Pb−Free indicator, “G” or microdot “ ”,<br>NOTE 5 may or may not be present.<br>K 6 4 b 6X SOLDERMASK DEFINED<br>J 0.10 C A B MOUNTING FOOTPRINT<br>J1 0.05 C NOTE 3<br>{4 e o 2.30<br>**----- End of picture text -----**<br>


4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 

1. CENTER TERMINAL LEAD IS OPTIONAL. TERMINAL LEAD IS CONNECTED TO TERMINAL LEAD # 4. 

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SOLDERMASK DEFINED<br>MOUNTING FOOTPRINT<br>2.30<br>1.10<br>6X 6X<br>0.43 0.35<br>1<br>0.60<br>1.25<br>| r a n 0.35<br>0.34<br>0.66<br>S 0.65 ion<br>PITCH<br>**----- End of picture text -----**<br>


## **BOTTOM VIEW** 

STYLE 1: STYLE 2: PIN 1. DRAIN PIN 1. COLLECTOR 2. DRAIN 2. COLLECTOR 3. GATE 3. BASE 4. SOURCE 4. EMITTER 5. DRAIN 5. COLLECTOR 6. DRAIN 6. COLLECTOR 

PITCH DIMENSIONS: MILLIMETERS Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON20860D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: 6 PIN WDFN 2X2, 0.65P PAGE 1 OF 1** ~~—~~ ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

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© Semiconductor Components Industries, LLC, 2019 

**onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi’s** product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

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