# Power MOSFET, N Channel, 20 V, 5.2 A, 0.025 ohm, ChipFET, Surface Mount

![Product image](https://novapart.co/image/farnell:1611275/)

**URL**: https://novapart.co/products/NTHS5404T1G/power-mosfet-n-channel-20-v-52-a-0025-ohm-chipfet
**SKU**: NTHS5404T1G
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.1700
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Power Dissipation | 1.3W |
| Transistor Mounting | Surface Mount |
| Transistor Polarity | N Channel |
| Power Dissipation Pd | 1.3W |
| Rds(On) Test Voltage | 4.5V |
| On Resistance Rds(On) | 0.025ohm |
| Transistor Case Style | ChipFET |
| Drain Source Voltage Vds | 20V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 5.2A |
| Drain Source On State Resistance | 0.025ohm |
| Gate Source Threshold Voltage Max | 600mV |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:1611275/)

NTHS5404T1 

## Power MOSFET 

## **20 V, 7.2 A, N−Channel ChipFET** 

## **Features** 

- Low RDS(on) for Higher Efficiency 

## **http://onsemi.com** 

- Logic Level Gate Drive 

- Miniature ChipFET Surface Mount Package Saves Board Space 

**==> picture [484 x 377] intentionally omitted <==**

**----- Start of picture text -----**<br>
• Pb−Free Package is Available V(BR)DSS RDS(on) TYP ID MAX<br>20 V 25 m  @ 4.5 V 7.2 A<br>Applications<br>• Power Management in Portable and Battery−Powered Products; i.e.,<br>Cellular and Cordless Telephones and PCMCIA Cards D<br>MAXIMUM RATINGS  (TA = 25 ° C unless otherwise noted)<br>Steady G<br>Rating Symbol 5 Secs State Unit<br>Drain−Source Voltage VDS 20 V<br>: S<br>Gate−Source Voltage VGS 12 V N−Channel MOSFET<br>Continuous Drain Current ID A<br>(TJ = 150 ° C) (Note 1)<br>TA = 25 ° C 7.2 5.2 ChipFET<br>TA = 85 ° C 5.2 3.8 CASE 1206A<br>STYLE 1<br>Pulsed Drain Current IDM 20 A<br>fet =<br>Continuous Source Current IS 7.2 5.2 A<br>(Diode Conduction) (Note 1) PIN MARKING<br>CONNECTIONS DIAGRAM<br>Maximum Power Dissipation PD W<br>ee ee —<br>(Note 1)<br>TA = 25 ° C 2.5 1.3 D 8 1 D 1 8<br>° 1.3 0.7<br>TA = 85 C<br>Operating Junction and Storage TJ, Tstg −55 to +150 ° C D 7 2 D 2 7<br>Temperature Range D 6 3 D 3 6<br>Stresses exceeding Maximum Ratings may damage the device. Maximum<br>Ratings are stress ratings only. Functional operation above the Recommended S 5 4 G 4 5<br>Operating Conditions is not implied. Extended exposure to stresses above the Te:<br>Recommended Operating Conditions may affect device reliability.<br>1. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq A2 = Specific Device Code<br>[1 oz] including traces). M = Month Code<br>= Pb−Free Package<br>A2 M<br>**----- End of picture text -----**<br>


(Note: Microdot may be in either location) **ORDERING INFORMATION Device Package Shipping**[†] NTHS5404T1 ChipFET 3000/Tape & Reel NTHS5404T1G ChipFET 3000/Tape & Reel (Pb−Free) ~~a~~ †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2008 **June, 2008 − Rev. 5** 

**NTHS5404T1/D** 

**NTHS5404T1** 

## **THERMAL CHARACTERISTICS** 

|**THERMAL CHARACTERISTICS**|||||
|---|---|---|---|---|
|**Characteristic**|**Symbol**|**Typ**|**Max**|**Unit**|
|Maximum Junction−to−Ambient (Note 2)<br>t�5 sec<br>Steady State|R�JA|40<br>80|50<br>95|°C/W|
|Maximum Junction−to−Foot (Drain)<br>Steady State|R�JF|15|20|°C/W|



## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) 

|**Characteristic**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**DYNAMIC**(Note 4)|||||||
|Total Gate Charge|QG|VDS= 10 V, VGS= 4.5 V,<br>ID= 5.2 A||12|18|nC|
|Gate−Source Charge|QGS|||2.4|||
|Gate−Drain Charge|QGD|||3.2|||
|Input Capacitance|CISS|VDS= 16 V, VGS= 0 V,<br>f = 1.0 MHz||740||pF|
|Output Capacitance|COSS|||337|||
|Reverse Transfer Capacitance|CRSS|||88|||
|Turn−On Delay Time|td(on)|VDD= 10 V, RL= 10�<br>ID �1.0 A, VGEN= 4.5 V,<br>RG= 6�||8.0|15|ns|
|Rise Time|tr|||7.0|15||
|Turn−Off Delay Time|td(off)|||50|60||
|Fall Time|tf|||28|40||
|**STATIC**|||||||
|Drain−to−Source Breakdown Voltage<br>(Note 3)|V(BR)DSS|VDS= VGS, ID= 250�A|20|25.1||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/TJ|||18.4||mV/°C|
|Gate Threshold Voltage|VGS(th)|VDS= VGS, ID= 250�A|0.6|||V|
|Gate−Body Leakage|IGSS|VDS= 0 V, VGS=�12 V|||�100|nA|
|Zero Gate Voltage Drain Current|IDSS|VDS= 16 V, VGS= 0 V|||1.0|�A|
|||VDS= 16 V, VGS= 0 V,<br>TJ= 85°C|||5.0||
|On−State Drain Current (Note 3)|ID(on)|VDS �5.0 V, VGS= 4.5 V|20|||A|
|Drain−Source On−State Resistance<br>(Note 3)|rDS(on)|VGS= 4.5 V, ID= 5.2 A||0.025|0.030|�|
|||VGS= 2.5 V, ID= 4.3 A||0.038|0.045||
|Forward Transconductance (Note 3)|gfs|VDS= 10 V, ID= 5.2 A||20||S|
|**DRAIN−SOURCE DIODE CHARACTERISTICS**|||||||
|Forward Diode Voltage (Note 3)|VSD|VGS= 0 V, IS= 5.2 A||0.8|1.2|V|
|Reverse Recovery Time|trr|VGS= 0 V, IS= 5.2 A,<br>diS/dt = 100 A/�s||20.9||ns|
|Charge Time|ta|||10.2|||
|Discharge Time|tb|||10.6|||
|Reverse Recovery Time|Qrr|||11||nC|



2. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 

3. Pulse Test: Pulse Width � 300 � s, Duty Cycle � 2%. 

4. Guaranteed by design, not subject to production testing. 

**http://onsemi.com** 

**2** 

**NTHS5404T1** 

## **TYPICAL ELECTRICAL CHARACTERISTICS** 

**==> picture [491 x 605] intentionally omitted <==**

**----- Start of picture text -----**<br>
12 12<br>5 V 2 V 1.8 V<br>10 10<br>VGS = 2 V − 5 V TJ = 25 ° C<br>8 8<br>1.6 V<br>6 6<br>4 4<br>1.4 V 125 ° C<br>2 2 25 ° C<br>VGS = 1.2 V TC = −55 ° C<br>0 0<br>0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5<br>VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>0.06 0.040<br>TJ = 25 ° C<br>0.05 TIDJ = 5.2 A = 25 ° C 0.038<br>0.036<br>0.04 VGS = 2.5 V<br>0.034<br>0.03 0.032<br>0.030<br>0.02 VGS = 4.5 V<br>0.028<br>0.01 0.026 V GS = 6 V<br>0 0.024<br>0 1 2 3 4 5 2 3 4 5 6 7 8 9 10<br>VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)<br>Figure 3. On−Resistance versus Figure 4. On−Resistance versus Drain Current<br>Gate−to−Source Voltage and Gate Voltage<br>1.6 1E−05<br>VIDGS = 5.2 A = 4.5 V VGS = 0 V<br>1.4<br>1E−06<br>1.2<br>TJ = 150 ° C<br>1<br>1E−07<br>TJ = 100 ° C<br>0.8<br>0.6 1E−08<br>−50 −25 0 25 50 75 100 125 150 0 4 8 12 16 20<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>DRAIN CURRENT (AMPS) DRAIN CURRENT (AMPS)<br>ID,  ID,<br>) � ) �<br>DRAIN−TO−SOURCE RESISTANCE ( DRAIN−TO−SOURCE RESISTANCE (<br>DS(on),  DS(on),<br>R R<br>DRAIN−TO−SOURCE<br>, LEAKAGE (AMPS)<br>IDSS<br>DS(on),<br>R RESISTANCE (NORMALIZED)<br>**----- End of picture text -----**<br>


**Figure 5. On−Resistance Variation with Temperature** 

**Figure 6. Drain−to−Source Leakage Current versus Voltage** 

**http://onsemi.com** 

**3** 

**NTHS5404T1** 

## **TYPICAL ELECTRICAL CHARACTERISTICS** 

**==> picture [491 x 615] intentionally omitted <==**

**----- Start of picture text -----**<br>
5 11<br>VDS = 0 V VGS = 0 V QG 10<br>1800 C iss T J  = 25 ° C 4 9<br>1500 8<br>7<br>3<br>1200 Crss 6<br>5<br>900 2 QGD QGS 4<br>600 ID = 5.2 A 3<br>300 Coss 1 TQ J GD= 25/QGS ° C = 1.33 2<br>1<br>0 0 0<br>12 8 4 0 4 8 12 16 20 0 1 2 3 4 5 6 7 8 9 10 11 12<br>VGS VDS<br>QG, TOTAL GATE CHARGE (nC)<br>GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 8. Gate−to−Source and<br>Figure 7. Capacitance Variation Drain−to−Source Voltage versus Total Charge<br>100 5<br>td(off)<br>4 V GS  = 0 V<br>tf T J  = 25 ° C<br>3<br>10 td(on)<br>2<br>tr<br>VDD = 10 V 1<br>ID = +1.0 A<br>VGS = 4.5 V<br>1 0<br>1 10 100 0 0.2 0.4 0.6 0.8<br>RG, GATE RESISTANCE (OHMS) VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)<br>Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage versus<br>versus Gate Resistance Current<br>1<br>Duty Cycle = 0.5<br>0.2<br>0.1 0.1 PDM PER UNIT BASE = R � JA = 80 ° C/W<br>TJM − TA = PDMZ � JA(t)<br>0.05 SURFACE MOUNTED<br>0.02 t1<br>t2<br>DUTY CYCLE, D = t 1 /t 2<br>Single Pulse<br>0.01<br>0.0001 0.001 0.01 0.1 1 10 100 1000<br>SQUARE WAVE PULSE DURATION (sec)<br>(V)<br>C, CAPACITANCE (pF)<br>GATE−TO−SOURCE VOLTAGE<br>DRAIN−TO−SOURCE VOLTAGE (V)<br>GS,<br>V DS,<br>V<br>t, TIME (ns)<br>, SOURCE CURRENT (AMPS)<br>IS<br>THERMAL IMPEDANCE<br>NORMALIZED EFFECTIVE TRANSIENT<br>**----- End of picture text -----**<br>


**Figure 11. Normalized Thermal Transient Impedance, Junction−to−Ambient** 

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**4** 

**NTHS5404T1** 

## **SOLDERING FOOTPRINT*** 

**==> picture [204 x 207] intentionally omitted <==**

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2.032<br>0.08<br>1<br>1.727<br>0.068<br>2.362<br>0.093<br>2X<br>0.4570.018 0.66<br>2X<br>0.018 0.0260.66<br>� inches [[mm]] �<br>**----- End of picture text -----**<br>


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2.032<br>0.08<br>0.08 1<br>1<br>1.727<br>0.068<br>2.362<br>2.362<br>0.635 0.093<br>0.093<br>0.025<br>PITCH<br>8X 2X<br>8X 0.4570.018 0.0260.66 2X 0.4570.018 0.0260.66<br>� inches [mm] � � inches [[mm]] �<br>Figure 12. Basic Figure 13. Style 1 and 4<br>ADDITIONAL SOLDERING FOOTPRINTS*<br>2.032 2.032<br>0.08 0.08 2X<br>1 0.66<br>0.457 1 0.026<br>4X<br>0.018<br>2X<br>1.092<br>0.043 1.092<br>0.043<br>2.362<br>0.093<br>2.362<br>0.093<br>0.635<br>0.025<br>0.635<br>PITCH<br>0.025<br>PITCH<br>4X 2X<br>0.66 1.118<br>0.026 0.044 1.118<br>� inches [mm] � 2X 0.457 0.044<br>0.018<br>Style 2 Style 3 � inches [mm] �<br>**----- End of picture text -----**<br>


*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

## **BASIC PAD PATTERNS** 

The basic pad layout with dimensions is shown in Figure 12. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. 

The minimum recommended pad pattern shown in Figure 13 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the 

confines of the basic footprint. The drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper lead−frame) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. 

**http://onsemi.com** 

**5** 

**NTHS5404T1** 

## **PACKAGE DIMENSIONS** 

**==> picture [489 x 197] intentionally omitted <==**

**----- Start of picture text -----**<br>
ChipFET ™<br>CASE 1206A−03<br>ISSUE J<br>D NOTES:<br>1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.<br>2. CONTROLLING DIMENSION: MILLIMETER.<br>8 7 6 5 L 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.<br>4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL<br>res p i 5 6 7 8 AND VERTICAL SHALL NOT EXCEED 0.08 MM.<br>HE E 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.<br>4 3 2 1 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD<br>1 2 3 4 SURFACE.<br>MILLIMETERS INCHES<br>DIM MIN NOM MAX MIN NOM MAX<br>e1 b c A 1.00 1.05 1.10 0.039 0.041 0.043<br>e b 0.25 0.30 0.35 0.010 0.012 0.014<br>STYLE 1: c 0.10 0.15 0.20 0.004 0.006 0.008<br>PIN 1. DRAIN D 2.95 3.05 3.10 0.116 0.120 0.122<br>Ldqo  2. DRAIN  ======— E 1.55 1.65 1.70 0.061 0.065 0.067<br> 3. DRAIN e 0.65 BSC 0.025 BSC<br>A  4. GATE e1 0.55 BSC 0.022 BSC<br> 5. SOURCE L 0.28 0.35 0.42 0.011 0.014 0.017<br> 6. DRAIN H E 1.80 1.90 2.00 0.071 0.075 0.079<br>a 0.05 (0.002)  7. 8. DRAINDRAIN 5° NOM 5° NOM<br>**----- End of picture text -----**<br>


## **SOLDERING FOOTPRINT** 

**==> picture [237 x 217] intentionally omitted <==**

**----- Start of picture text -----**<br>
2.032<br>0.08<br>1<br>=e<br>2.362<br>‘ oo . 0.635<br>0.093<br>0.025<br>PITCH<br>L I Et<br>8X<br>8X Le 0.457 y+ 0.66<br>0.018 0.026<br>mm<br>7 7 7 f = inches<br>Basic Style<br>**----- End of picture text -----**<br>


## ChipFET is a trademark of Vishay Siliconix. 

**ON Semiconductor** and          are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).  SCILLC reserves the right to make changes without further notice to any products herein.  SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.  All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.  SCILLC does not convey any license under its patent rights nor the rights of others.  SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.  Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.  SCILLC is an Equal Opportunity/Affirmative Action Employer.  This literature is subject to all applicable copyright laws and is not for resale in any manner. 

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**NTHS5404T1/D** 

**6** 



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