# Power MOSFET, P Channel, 20 V, 4.8 A, 0.034 ohm, ChipFET, Surface Mount

![Product image](https://novapart.co/image/farnell:2533190/)

**URL**: https://novapart.co/products/NTHS4101PT1G/power-mosfet-p-channel-20-v-48-a-0034-ohm-chipfet
**SKU**: NTHS4101PT1G
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.3750
**Stock**: 1000+
**Lead Time**: 106 days (indicative)

## Description

Transistor Polarity:P Channel; Continuous Drain Current Id:-4.8A; Drain Source Voltage Vds:-20V; On Resistance Rds(on):0.021ohm; Rds(on) Test Voltage Vgs:-4.5V; Threshold Voltage Vgs

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | P Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 1.3W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 4.5V |
| Transistor Case Style | ChipFET |
| Drain Source Voltage Vds | 20V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 4.8A |
| Drain Source On State Resistance | 0.034ohm |
| Gate Source Threshold Voltage Max | 1.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2533190/)

NTHS4101P 

## MOSFET ~~a~~ – Power, P-Channel, ChipFET -20 V, 6.7 A 

## **Features** 

- Offers an Ultra Low RDS(on) Solution in the ChipFET Package 

- Miniature ChipFET Package 40% Smaller Footprint than TSOP−6 making it an Ideal Device for Applications where Board Space is at a Premium 

- Low Profile (<1.1 mm) Allows it to Fit Easily into Extremely Thin Environments such as Portable Electronics 

- Designed to Provide Low RDS(on) at Gate Voltage as Low as 1.8 V, the Operating Voltage used in many Logic ICs in Portable Electronics 

- Simplifies Circuit Design since Additional Boost Circuits for Gate Voltages are not Required 

- Operated at Standard Logic Level Gate Drive, Facilitating Future Migration to Lower Levels using the same Basic Topology 

- Pb−Free Package is Available 

## **Applications** 

- Optimized for Battery and Load Management Applications in Portable Equipment such as MP3 Players, Cell Phones, Digital Cameras, Personal Digital Assistant and other Portable Applications 

- Charge Control in Battery Chargers 

- Buck and Boost Converters 

## **http://onsemi.com** 

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**----- Start of picture text -----**<br>
V(BR)DSS RDS(on) TYP ID MAX<br>eeee eee<br>21 m  @ −4.5 V<br>−20 V 30 m  @ −2.5 V −6.7 A<br>42 m  @ −1.8 V<br>S<br>G<br>D<br>P−Channel MOSFET<br>**----- End of picture text -----**<br>


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8 ChipFET<br>CASE 1206A<br>STYLE 1<br>1<br>**----- End of picture text -----**<br>


**MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) 

**==> picture [493 x 287] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|ee|Rating|Symbol|Value|Unit|PIN|MARKING|
|CONNECTIONS|DIAGRAM|
|Drain−to−Source Voltage|VDSS|−20|Vdc|
|ee|ee|
|Gate−to−Source Voltage − Continuous|VGS|8.0|Vdc|D|8|1|D|1|8|
|ee|ee|ee|ee|—|
|Drain Current|− Continuous|ID|−4.8|A|D|7|2|D|2|7|
|− 5 seconds|ID|−6.7|
|eo|Total Power Dissipation|ee|PD|ee|ee|W|D|6|3|D|3||1.||||6|
|(5 sec) @ TContinuous @ TA = 25A = 25|°|C|°|C|1.32.5|S|5|4|G|4|l|I|5|
|Continuous @ 85|°|C|0.7|
|(5 sec) @ 85|°|C|1.3|
|C6 = Specific Device Code|
|Pulsed Drain Current − tp = 10 s|IDM|−190|A|M|= Month Code|
|ee|Operating Junction and Storage|ee|TJ, TSTG|−55 to|ee|°|C|;|= Pb−Free Package|
|Temperature Range|+150|
|ORDERING INFORMATION|
|Continuous Source Current|Is|−4.8|A|
|ee|Thermal Resistance (Note 1)|ee|ee|°|C/W|Device|Package|Shipping|[†]|
|Junction−to−Ambient, 5 sec|R|JA|50|NTHS4101PT1|ChipFET|3000 Tape / Reel|
|Junction−to−Ambient, Continuous|R|(3)|JA|95|
|Maximum Lead Temperature for Soldering|″|TL|260|°|C|NTHS4101PT1G|(Pb−free)ChipFET|3000 Tape / Reel|
|ns|Purposes, 1/8|from case for 10 seconds|———|
|Stresses exceeding Maximum Ratings may damage the device. Maximum|†For information on tape and reel specifications,|
|Ratings are stress ratings only. Functional operation above the Recommended|including part orientation and tape sizes, please|
|Operating Conditions is not implied. Extended exposure to stresses above the|refer to our Tape and Reel Packaging Specifications|
|Recommended Operating Conditions may affect device reliability.|Brochure, BRD8011/D.|

**----- End of picture text -----**<br>


Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2012 **May, 2019 − Rev. 4** 

**NTHS4101P/D** 

**NTHS4101P** 

1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). 

**http://onsemi.com** 

**2** 

## **NTHS4101P** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) 

|**ELECTRICAL CHARACTERISTICS **(TJ= 25|°C unless oth|erwise noted)|||||
|---|---|---|---|---|---|---|
|**Characteristic**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**|||||||
|Drain−to−Source Breakdown Voltage (Note 2)<br>Temperature Coefficient (Positive)|V(Br)DSS|VGS= 0 Vdc, ID= −250�Adc|−20|||Vdc|
|Gate−Body Leakage Current Zero|IGSS|VDS= 0 Vdc, VGS=�8.0 Vdc|||�100|nAdc|
|Zero Gate Voltage Drain Current|IDSS|VDS= −16 Vdc, VGS= 0 Vdc<br>VDS= −16 Vdc, VGS= 0 Vdc,<br>TJ= 85°C|||−1.0<br>−5.0|�Adc|
|**ON CHARACTERISTICS**(Note 2)|||||||
|Gate Threshold Voltage|VGS(th)|VDS= VGS, ID= −250�Adc|−0.45||−1.5|Vdc|
|Static Drain−to−Source On−Resistance|RDS(on)|VGS= −4.5 Vdc, ID= −4.8 Adc<br>VGS= −2.5 Vdc, ID= −4.2 Adc<br>VGS= −1.8 Vdc, ID= −1.0 Adc||21<br>30<br>42|34<br>40<br>52|m�|
|Forward Transconductance|gFS|VDS= −5.0 Vdc, ID= −4.8 Adc||15||S|
|Diode Forward Voltage|VSD|IS= −4.8 Adc, VGS= 0 Vdc||−0.8|−1.2|V|
|**DYNAMIC CHARACTERISTICS**|||||||
|Input Capacitance|Ciss|VDS= −16 Vdc<br>VGS= 0 V<br>f = 1.0 MHz||2100||pF|
|Output Capacitance|Coss|||290|||
|Transfer Capacitance|Crss|||200|||
|**SWITCHING CHARACTERISTICS**(Note 3)|||||||
|Turn−On Delay Time|td(on)|VDD= −16 Vdc<br>VGS= −4.5 Vdc<br>ID= −4.5 Adc<br>RG= 2.5�||8.0||ns|
|Rise Time|tr|||28|||
|Turn−Off Delay Time|td(off)|||75|||
|Fall Time|tf|||60|||
|Gate Charge|Qg|VGS= −4.5 Vdc<br>ID= −4.5 Adc<br>VDS= −16 Vdc(Note 3)||25|35|nC|
||Qgs|||4.0|||
||Qgd|||7.0|||



2. Pulse Test: Pulse Width = 250 � s, Duty Cycle = 2%. 

3. Switching characteristics are independent of operating junction temperatures. 

**http://onsemi.com** 

**3** 

**NTHS4101P** 

## **TYPICAL PERFORMANCE CURVES** (TJ = 25 ° C unless otherwise noted) 

**==> picture [491 x 384] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 VGS = −10 V to −2.4 V TJ = 25 ° C 10<br>9 9<br>−1.8 V<br>8 8<br>7 7<br>6 6<br>5 5<br>−1.6 V<br>4 4 125 ° C<br>3 3 25 ° C<br>2 2<br>1 −1.4 V 1 TJ = −55 ° C<br>−1.2 V<br>0 0<br>0 1 2 3 4 5 6 7 8 0 0.5 1 1.5 2 2.5 3<br>−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>0.1 1.5<br>VGS = −1.8 V VGS = −4.5 V<br>0.08 1.3<br>0.06 1.1<br>0.04 0.9<br>VGS = −2.5 V<br>0.02 0.7<br>VGS = −4.5 V<br>0 0.5<br>2 4 6 8 10 12 14 16 −50 −25 0 25 50 75 100 125 150<br>−ID, DRAIN CURRENT (AMPS) TJ, JUNCTION TEMPERATURE ( ° C)<br>DRAIN CURRENT (AMPS) DRAIN CURRENT (AMPS)<br>D,  D,<br>−I −I<br>) �<br>DRAIN−TO−SOURCE<br>DS(on),<br>R RESISTANCE (NORMALIZED)<br>DRAIN−TO−SOURCE RESISTANCE (<br>DS(on),<br>R<br>**----- End of picture text -----**<br>


**Figure 3. On−Resistance vs. Drain Current and Gate Voltage** 

**Figure 4. On−Resistance Variation with Temperature** 

**==> picture [236 x 177] intentionally omitted <==**

**----- Start of picture text -----**<br>
10000<br>VGS = 0 V<br>TJ = 125 ° C<br>1000<br>TJ = 100 ° C<br>100<br>10<br>TJ = 25 ° C<br>1<br>0.1<br>0 2 4 6 8<br>−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>, LEAKAGE (nA)<br>DSS<br>−I<br>**----- End of picture text -----**<br>


**Figure 5. Drain−to−Source Leakage Current vs. Voltage** 

**http://onsemi.com** 

**4** 

**NTHS4101P** 

## **TYPICAL PERFORMANCE CURVES** (TJ = 25 ° C unless otherwise noted) 

**==> picture [244 x 398] intentionally omitted <==**

**----- Start of picture text -----**<br>
5000<br>VDS = 0 V VGS = 0 V TJ = 25 ° C<br>4500<br>4000<br>3500<br>3000<br>2500 Crss Ciss<br>2000<br>1500<br>1000<br>500 Coss<br>0<br>−6 −4 −2 0 2 4 6 8 10 12 14 16 18 20<br>−VGS −VDS<br>GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 6. Capacitance Variation<br>1000<br>VDD = −16 V<br>ID = −4.5 A<br>VGS = −4.5 V<br>100 td(off)<br>tf<br>tr<br>10<br>td(on)<br>1<br>1 10 100<br>RG, GATE RESISTANCE (OHMS)<br>C, CAPACITANCE (pF)<br>t, TIME (ns)<br>**----- End of picture text -----**<br>


**==> picture [244 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>**----- End of picture text -----**<br>


**Figure 8. Resistive Switching Time Variation vs. Gate Resistance** 

**==> picture [228 x 181] intentionally omitted <==**

**----- Start of picture text -----**<br>
5<br>QT<br>4<br>3<br>2<br>Q1 Q2<br>1<br>ID = −4.5 A<br>TJ = 25 ° C<br>0<br>0 3 6 9 12 15 18 21 24 27<br>Qg, TOTAL GATE CHARGE (nC)<br>GATE−TO−SOURCE VOLTAGE (VOLTS)<br>GS,<br>−V<br>**----- End of picture text -----**<br>


**Figure 7. Gate−to−Source and Drain−to−Source Voltage vs. Total Gate Charge** 

**==> picture [231 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
5<br>VGS = 0 V<br>TJ = 25 ° C<br>4<br>3<br>2<br>1<br>0<br>0.4 0.5 0.6 0.7 0.8 0.9 1.0<br>−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)<br>, SOURCE CURRENT (AMPS)<br>S<br>−I<br>**----- End of picture text -----**<br>


**Figure 9. Diode Forward Voltage vs. Current** 

**==> picture [238 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
100<br>10<br>10  � s<br>100  � s<br>1 1 ms<br>VGS = −8 V<br>SINGLE PULSE<br>TC = 25 ° C<br>0.1<br>RDS(on) LIMIT dc<br>THERMAL LIMIT<br>PACKAGE LIMIT<br>0.01<br>0.1 1 10 100<br>−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>−ID, DRAIN CURRENT (AMPS)<br>**----- End of picture text -----**<br>


**Figure 10. Maximum Rated Forward Biased Safe Operating Area** 

ChipFET is a trademark of Vishay Siliconix. 

**http://onsemi.com** 

**5** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**==> picture [489 x 549] intentionally omitted <==**

**----- Start of picture text -----**<br>
ChipFET<br>8 CASE1206A−03<br>ISSUE K<br>DATE  19 MAY 2009<br>&<br>1<br>SCALE 1:1<br>D NOTES:<br>1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.<br>2. CONTROLLING DIMENSION: MILLIMETER.<br>8 7 6 5 L 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.<br>4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL<br>5 6 7 8<br>AND VERTICAL SHALL NOT EXCEED 0.08 MM.<br>ft HE oem E O t 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.<br>4 3 2 1 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD<br>1 2 3 4 SURFACE.<br>MILLIMETERS INCHES<br>DIM MIN NOM MAX MIN NOM MAX<br>e1 b c A 1.00 1.05 1.10 0.039 0.041 0.043<br>e b 0.25 0.30 0.35 0.010 0.012 0.014<br>c 0.10 0.15 0.20 0.004 0.006 0.008<br>D 2.95 3.05 3.10 0.116 0.120 0.122<br>Lolqe RESET  ieeeeee E 1.55 1.65 1.70 0.061 0.065 0.067<br>e 0.65 BSC 0.025 BSC<br>A e1 0.55 BSC 0.022 BSC<br>L 0.28 0.35 0.42 0.011 0.014 0.017<br>H E 1.80 1.90 2.00 0.071 0.075 0.079<br>= 0.05 (0.002) 5° NOM 5° NOM<br>STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5: STYLE 6:<br>PIN 1. DRAIN PIN 1. SOURCE 1 PIN 1. ANODE PIN 1. COLLECTOR PIN 1. ANODE PIN 1. ANODE<br> 2. DRAIN  2. GATE 1  2. ANODE  2. COLLECTOR  2. ANODE  2. DRAIN<br> 3. DRAIN  3. SOURCE 2  3. SOURCE  3. COLLECTOR  3. DRAIN  3. DRAIN<br> 4. GATE  4. GATE 2  4. GATE  4. BASE  4. DRAIN  4. GATE<br> 5. SOURCE  5. DRAIN 2  5. DRAIN  5. EMITTER  5. SOURCE  5. SOURCE<br> 6. DRAIN  6. DRAIN 2  6. DRAIN  6. COLLECTOR  6. GATE  6. DRAIN<br> 7. DRAIN  7. DRAIN 1  7. CATHODE  7. COLLECTOR  7. CATHODE  7. DRAIN<br> 8. DRAIN  8. DRAIN 1  8. CATHODE  8. COLLECTOR  8. CATHODE  8. CATHODE / DRAIN<br>SOLDERING FOOTPRINT GENERIC<br>MARKING DIAGRAM*<br>2.032<br>0.08<br>1<br>xxx M<br>xxx = Specific Device Code<br>M = Month Code<br>= Pb−Free Package<br>2.362 lols 0.65 (Note: Microdot may be in either location)<br>0.093<br>0.025 *This information is generic. Please refer to<br>PITCH device data sheet for actual part marking.<br>Pb−Free indicator, “G” or microdot “ ”,<br>oa may or may not be present.<br>8X<br>8X Le 0.457 -—} 0.66 +<br>0.018 0.026<br>mm<br>7 > -b = inches<br>Basic Style<br>**----- End of picture text -----**<br>


## **OPTIONAL SOLDERING FOOTPRINTS ON PAGE 2** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON03078D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: ChipFET PAGE 1 OF 2** ~~ee~~ ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

DATE 19 MAY 2009 

**ChipFET** CASE 1206A−03 ISSUE K 

**ADDITIONAL SOLDERING FOOTPRINTS*** 

**==> picture [460 x 488] intentionally omitted <==**

**----- Start of picture text -----**<br>
2.032 2.032<br>0.08 0.08<br>1 1<br>re nm | 0.457 to<br>4X<br>0.018<br>2X<br>1.092<br>0.043<br>1.727<br>0.068<br>2.362 2.362<br>0.093 0.093<br>0.65<br>C t BEE<br>0.025<br>PITCH<br>4X 2X<br>Y o = 2X " in<br>0.66 1.118<br>0.457 0.66<br>2X 0.018 0.026 mm 0.026 0.044 inchesmm<br>— 4b inches Ara<br>Styles 1 and 4 Style 2<br>2.032 2.032<br>0.08 2X 0.08 2X<br>0.66 0.66<br>1 mp 0.026 1 eet 0.026<br>1.092 1.092<br>0.043 0.043<br>2.362 2.362<br>0.093 0.093<br>ue 0.65 0.65<br>0.025 0.025<br>PITCH PITCH<br>S l 1.118 | | | LIE 1.118 =<br>2X 0.457 0.044 0.044 2X 0.457<br>0.018 — a 0.018<br>mm mm<br>I) inches — a inches<br>Style 3 Style 5<br>**----- End of picture text -----**<br>


- *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON03078D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: ChipFET PAGE 2 OF 2** ~~a~~ ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

**onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** ’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

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**==> picture [232 x 43] intentionally omitted <==**



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---

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