# Power MOSFET, N Channel, 30 V, 7 A, 0.025 ohm, TSOP, Surface Mount

![Product image](https://novapart.co/image/farnell:2317624/)

**URL**: https://novapart.co/products/NTGS4141NT1G/power-mosfet-n-channel-30-v-7-a-0025-ohm-tsop
**SKU**: NTGS4141NT1G
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.1190
**Stock**: 1000+
**Lead Time**: 106 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:7A; Drain Source Voltage Vds:30V; On Resistance Rds(on):0.0215ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 6Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 2W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TSOP |
| Drain Source Voltage Vds | 30V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 7A |
| Drain Source On State Resistance | 0.025ohm |
| Gate Source Threshold Voltage Max | 3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2317624/)

NTGS4141N, NVGS4141N 

## Power MOSFET 

## **30 V, 7.0 A, Single N−Channel, TSOP−6** 

## **Features** 

- Low RDS(on) 

- Low Gate Charge 

- NV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable 

- Pb−Free Package is Available 

## **Applications** 

- Load Switch 

**http://onsemi.com** 

**==> picture [190 x 62] intentionally omitted <==**

**----- Start of picture text -----**<br>
V(BR)DSS RDS(on) TYP ID MAX<br>ee<br>ee<br>21.5 m  @ 10 V<br>30 V 7.0 A<br>30 m  @ 4.5 V<br>**----- End of picture text -----**<br>


- Notebook PC 

## **N−Channel** 

- Desktop PC 

**==> picture [161 x 234] intentionally omitted <==**

**----- Start of picture text -----**<br>
Drain 1 2 5 6<br>Gate 3<br>7<br>Source 4<br>MARKING<br>DIAGRAM<br>TSOP−6<br>CASE 318G<br>1 STYLE 1 XX M<br>|<br>XX = Device Code<br>M = Date Code<br>= Pb−Free Package<br>(Note: Microdot may be in either location)<br>**----- End of picture text -----**<br>


**==> picture [345 x 331] intentionally omitted <==**

**----- Start of picture text -----**<br>
MAXIMUM RATINGS  (TJ = 25 ° C unless otherwise noted)<br>Rating Symbol Value Unit<br>Drain−to−Source Voltage VDSS 30 V<br>es<br>Gate−to−Source Voltage VGS ± 20 V<br>es Continuous Drain Steady TA = 25 ° C es ID  ee 5.0 A<br>ee Current (Note 1) State TA = 85 ° C ee 3.6 es<br>t  ≤ 10 s TA = 25 ° C 7.0<br>=F<br>Power Dissipation Steady TA = 25 ° C PD 1.0 W<br>(Note 1) State<br>t  ≤ 10 s 2.0<br>| Continuous Drain Fi| Steady eT TA = 25 ° C | ID |Hi! 3.5 A »<br>Current (Note 2) State TA = 85 ° C 2.5 1<br>Power Dissipation TA = 25 ° C PD 0.5 W<br>(Note 2)<br>a= =2<br>ee ee<br>Pulsed Drain Current tp = 10 s, VGS=10V IDM 45 A XX<br>M<br>oH, Pulsed Drain Current tp = 30 s, VGS=5V ID 30 A<br>Operating Junction and Storage Temperature TJ, −55 to ° C<br>TSTG 150<br>ee<br>Source Current (Body Diode) IS 2.0 A<br>es<br>Single Pulse Drain−to−Source Avalanche Energy EAS 54 mJ<br>(VDD = 30 V, IL = 10.4 A, VGS = 10 V,<br>L = 1.0 mH, RG = 25 )<br>ee Lead Temperature for Soldering Purposes T ee L 260 ° C<br>(1/8 ″  from case for 10 s)<br>Stresses exceeding those listed in the Maximum Ratings table may damage the<br>device. If any of these limits are exceeded, device functionality should not be ee<br>assumed, damage may occur and reliability may be affected.<br>**----- End of picture text -----**<br>


## **PIN ASSIGNMENT** 

**==> picture [73 x 83] intentionally omitted <==**

**----- Start of picture text -----**<br>
Drain Drain Source<br>6 5 4<br>|<br>1 2 3<br>Drain Drain Gate<br>**----- End of picture text -----**<br>


## **THERMAL RESISTANCE RATINGS** 

|**THERMAL RESISTANCE RATINGS**||||
|---|---|---|---|
|**Rating**|**Symbol**|**Max**|**Unit**|
|Junction−to−Ambient – Steady State (Note 1)|RθJA|125|°C/W|
|Junction−to−Ambient – t≤10 s (Note 1)|RθJA|62.5||
|Junction−to−Ambient – Steady State (Note 2)|RθJA|248||



## **ORDERING INFORMATION** 

See detailed ordering and shipping information ion page 5 of this data sheet. 

1. Surface−mounted on FR4 board using 1 inch sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 

2. Surface−mounted on FR4 board using the minimum recommended pad size (Cu area = 0.0773 in sq). 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2014 **August, 2014 − Rev. 6** 

**NTGS4141N/D** 

## **NTGS4141N, NVGS4141N** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) 

|**ELECTRICAL CHARACTERISTICS **(TJ|= 25°C unless o|therwise noted)|therwise noted)|||||
|---|---|---|---|---|---|---|---|
|**Characteristic**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID= 250�A||30|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/TJ||||18.4||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 24 V|TJ= 25°C|||1.0|�A|
||||TJ= 125°C|||10||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS=±20 V||||±100|nA|
|**ON CHARACTERISTICS**(Note 3)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 250�A||1.0||3.0|V|
|Negative Threshold Temperature Coefficient|VGS(TH)/TJ||||5.7||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 10 V, ID= 7.0 A|||21.5|25|m�|
|||VGS= 4.5 V, ID= 6.0 A|||30|35||
|Forward Transconductance|gFS|VDS= 10 V, ID= 7.0 A|||30||S|
|**CHARGES, CAPACITANCES AND GATE RESISTANCE**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1.0 MHz,<br>VDS= 24 V|||560||pF|
|Output Capacitance|COSS||||115|||
|Reverse Transfer Capacitance|CRSS||||75|||
|Total Gate Charge|QG(TOT)|VGS= 10 V, VDS= 15 V,<br>ID= 7.0 A|||12||nC|
|Threshold Gate Charge|QG(TH)||||0.85|||
|Gate−to−Source Charge|QGS||||1.9|||
|Gate−to−Drain Charge|QGD||||3.0|||
|Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 15 V,<br>ID= 7.0 A|||6.0||nC|
|Threshold Gate Charge|QG(TH)||||0.8|||
|Gate−to−Source Charge|QGS||||1.85|||
|Gate−to−Drain Charge|QGD||||3.0|||
|Gate Resistance|RG||||2.8||�|
|**SWITCHING CHARACTERISTICS**(Note 4)||||||||
|Turn−On Delay Time|td(ON)|VGS= 10 V, VDS= 24 V,<br>ID= 7.0 A, RG= 3.0�|||6.0||ns|
|Rise Time|tr||||15|||
|Turn−Off Delay Time|td(OFF)||||18|||
|Fall Time|tf||||4.0|||
|**DRAIN − SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 2.0 A|TJ= 25°C||0.78|1.0|V|
||||TJ= 125°C||0.63|||
|Reverse Recovery Time|tRR|VGS= 0 V<br>dIS/dt = 100 A/�s, IS= 2.0 A|||15||ns|
|Charge Time|ta||||9.0|||
|Discharge Time|tb||||6.0|||
|Reverse Recovery Charge|QRR||||8.0||nC|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

3. Pulse Test: pulse width � 300 � s, duty cycle � 2%. 

4. Switching characteristics are independent of operating junction temperatures. 

**http://onsemi.com** 

**2** 

**NTGS4141N, NVGS4141N** 

## **TYPICAL PERFORMANCE CURVES** 

**==> picture [489 x 604] intentionally omitted <==**

**----- Start of picture text -----**<br>
15 10 V TJ = 25 ° C 15 VDS ≥  10 V<br>6 V 3.5 V<br>4.5 V<br>10 10<br>3 V<br>5 5<br>125 ° C<br>25 ° C<br>2.6 V<br>0 0 TJ = −55 ° C<br>0 2 4 6 8 10 1 2 3 4 5<br>VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>0.05 0.05<br>TJ = 25 ° C TJ = 25 ° C<br>ID = 7 A<br>0.04<br>0.04<br>0.03<br>0.03 VGS = 4.5 V<br>0.02<br>VGS = 10 V<br>0.02<br>0.01<br>0.01 0<br>0 2 4 6 8 10 0 5 10 15<br>VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>2.0 10000<br>ID = 7 A VGS = 0 V<br>V GS  = 10 V<br>1.5<br>1000<br>TJ = 150 ° C<br>1.0<br>100 TJ = 125 ° C<br>0.5<br>0 10<br>−50 −25 0 25 50 75 100 125 150 0 5 10 15 20 25 30<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>DRAIN CURRENT (AMPS) DRAIN CURRENT (AMPS)<br>ID,  ID,<br>) � ) �<br>DRAIN−TO−SOURCE RESISTANCE ( DRAIN−TO−SOURCE RESISTANCE (<br>DS(on),  DS(on),<br>R R<br>DRAIN−TO−SOURCE LEAKAGE CURRENT (nA)<br>DS(on),<br>R RESISTANCE (NORMALIZED)<br>IDSS,<br>**----- End of picture text -----**<br>


**Figure 5. On−Resistance Variation with Temperature** 

**Figure 6. Drain−to−Source Leakage Current vs. Voltage** 

**http://onsemi.com** 

**3** 

**NTGS4141N, NVGS4141N** 

## **TYPICAL PERFORMANCE CURVES** 

**==> picture [243 x 608] intentionally omitted <==**

**----- Start of picture text -----**<br>
1200<br>VDS = 0 V VGS = 0 V TJ = 25 ° C<br>1000<br>Ciss<br>800<br>600 Ciss<br>400 Crss<br>200 Coss<br>0 Crss<br>10 5 0 5 10 15 20 25<br>VGS VDS<br>GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 7. Capacitance Variation<br>1000<br>VDD = 24 V<br>ID = 7 A<br>VGS = 10 V<br>td(off)<br>100<br>tf<br>tr<br>10<br>td(on)<br>1<br>1 10 100<br>RG, GATE RESISTANCE (OHMS)<br>Figure 9. Resistive Switching Time<br>Variation vs. Gate Resistance<br>100<br>10  � s<br>10<br>100  � s<br>1 ms<br>1<br>0 V  ≤  VGS ≤  20 V<br>10 ms<br>SINGLE PULSE<br>TC = 25 ° C<br>0.1<br>RDS(on) LIMIT<br>THERMAL LIMIT dc<br>PACKAGE LIMIT<br>0.01<br>0.1 1 10 100<br>VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>C, CAPACITANCE (pF)<br>t, TIME (ns)<br>, DRAIN CURRENT (AMPS)<br>ID<br>**----- End of picture text -----**<br>


**==> picture [235 x 392] intentionally omitted <==**

**----- Start of picture text -----**<br>
10<br>QT<br>8<br>VGS<br>6<br>4 QGS QGD<br>2 ID = 7 A<br>VDD = 15 V<br>TJ = 25 ° C<br>0<br>0 2 4 6 8 10 12<br>QG, TOTAL GATE CHARGE (nC)<br>Figure 8. Gate−To−Source and<br>Drain−To−Source Voltage vs. Total Charge<br>7<br>VGS = 0 V<br>6 TJ = 25 ° C<br>5<br>4<br>3<br>2<br>1<br>0<br>0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9<br>VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)<br>VGS, GATE−TO−SOURCE VOLTAGE (V)<br>, SOURCE CURRENT (AMPS)<br>IS<br>**----- End of picture text -----**<br>


GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 

**Figure 10. Diode Forward Voltage vs. Current** 

**==> picture [243 x 170] intentionally omitted <==**

**----- Start of picture text -----**<br>
60<br>ID = 10.4 A<br>40<br>20<br>0<br>25 50 75 100 125 150<br>TJ, STARTING JUNCTION TEMPERATURE ( ° C)<br>AVALANCHE ENERGY (mJ)<br>EAS, SINGLE PULSE DRAIN−TO−SOURCE<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

**Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature** 

**http://onsemi.com** 

**4** 

**NTGS4141N, NVGS4141N** 

## **TYPICAL PERFORMANCE CURVES** 

**==> picture [494 x 409] intentionally omitted <==**

**----- Start of picture text -----**<br>
2.5 8.0<br>2.25 References is TJ- 7.5 References is TJ-<br>7.0 max [ = 150] [°] [C]<br>max [ = 150] [°] [C]<br>2.0 6.5<br>1.75 6.05.5 R � JA, 1 sq in R � JA , t < 10 s, 1 sq in<br>1.5 5.0<br>R � JA, t < 10 s, 1 sq in 4.5<br>1.25 R � JA, 1 sq in 4.0<br>3.5<br>1.0<br>3.0<br>0.75 2.5 R � JA, min pad<br>2.0<br>0.5<br>1.5<br>0.25 R � JA , min pad 1.0<br>0.5<br>0 0<br>0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160<br>TA, AMBIENT TEMPERATURE ( ° C) TA, AMBIENT TEMPERATURE ( ° C)<br>Figure 13. Maximum Power Derating Chart Figure 14. Current Derating Chart<br>1000<br>100 D = 0.5<br>0.2<br>0.1<br>10 0.05<br>0.02<br>1<br>0.01<br>0.1<br>Single Pulse<br>0.01<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>t, PULSE TIME (s)<br>, POWER DISSIPATION (W) , POWER DISSIPATION (W)<br>D D<br>P P<br>C/W)<br>°<br>, TRANSIENT THERMAL RESPONSE (<br>thja(t)<br>R<br>**----- End of picture text -----**<br>


**Figure 15. Thermal Response** 

**Table 1. ORDERING INFORMATION** 

|**Part Number**|**Marking**<br>**(XX)**|**Package**|**Shipping**†|
|---|---|---|---|
|NTGS4141NT1|S4|TSOP−6|3000 / Tape & Reel|
|NTGS4141NT1G|S4|TSOP−6<br>(Pb−Free)|3000 / Tape & Reel|
|NVGS4141NT1G|VS4|TSOP−6<br>(Pb−Free)|3000 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

**http://onsemi.com** 

**5** 

**NTGS4141N, NVGS4141N** 

## **PACKAGE DIMENSIONS** 

**TSOP−6** CASE 318G−02 ISSUE V 

## NOTES: 

**==> picture [469 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
D 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.<br>H 2. CONTROLLING DIMENSION: MILLIMETERS.<br>3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM<br>LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.<br>6 5 4 L2 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,<br>GAUGE PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR<br>E1 E PLANE GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D<br>ÉÉ AND E1 ARE DETERMINED AT DATUM H.<br>1 2 3 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.<br>NOTE 5 ÉÉ b L M C PLANESEATING DIM MIN MILLIMETERSNOM MAX<br>DETAIL Z A 0.90 1.00 1.10<br>e A1 0.01 0.06 0.10<br>Cian: === b 0.25 0.38 0.50<br>c 0.10 0.18 0.26<br>A c DE 2.902.50 3.002.75 3.103.00 STYLE 1:PIN 1. DRAIN<br>0.05 E1 1.30 1.50 1.70 2. DRAIN<br>e 0.85 0.95 1.05 3. GATE<br>L 0.20 0.40 0.60 4. SOURCE<br>ae A1 DETAIL Z a ==== L2M 0° 0.25 BSC− 1 0° 5.6. DRAINDRAIN<br>**----- End of picture text -----**<br>


**==> picture [123 x 146] intentionally omitted <==**

**----- Start of picture text -----**<br>
RECOMMENDED<br>SOLDERING FOOTPRINT*<br>6X<br>i es 0.60<br>P O U L<br>3.20 6X<br>Loud 0.95<br>0.95<br>PITCH<br>DIMENSIONS: MILLIMETERS<br>**----- End of picture text -----**<br>


**SOLDERING FOOTPRINT*** 

**==> picture [227 x 26] intentionally omitted <==**

**----- Start of picture text -----**<br>
*For additional information on our Pb−Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>**----- End of picture text -----**<br>


ON Semiconductor and the         are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf.  SCILLC reserves the right to make changes without further notice to any products herein.  SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.  All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.  SCILLC does not convey any license under its patent rights nor the rights of others.  SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.  Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.  SCILLC is an Equal Opportunity/Affirmative Action Employer.  This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **PUBLICATION ORDERING INFORMATION** 

**LITERATURE FULFILLMENT** : **N. American Technical Support** : 800−282−9855 Toll Free **ON Semiconductor Website** : **www.onsemi.com** Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA **Europe, Middle East and Africa Technical Support: Order Literature** : http://www.onsemi.com/orderlit **Phone** : 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 **Fax** : 303−675−2176 or 800−344−3867 Toll Free USA/Canada **Japan Customer Focus Center** For additional information, please contact your local **Email** : orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative 

**NTGS4141N/D** 

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## Links

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- [Supplier page](https://es.farnell.com/on-semiconductor/ntgs4141nt1g/mosfet-n-ch-30v-0-0215ohm-7a-tsop/dp/2317624)
---

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