# Power MOSFET, P Channel, 20 V, 5.1 A, 0.033 ohm, TSOP, Surface Mount

![Product image](https://novapart.co/image/farnell:2845377/)

**URL**: https://novapart.co/products/NTGS3136PT1G/power-mosfet-p-channel-20-v-51-a-0033-ohm-tsop
**SKU**: NTGS3136PT1G
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.2380
**Stock**: 1000+
**Lead Time**: 2 days (indicative)

## Description

Transistor Polarity:P Channel; Continuous Drain Current Id:-5.1A; Drain Source Voltage Vds:-20V; On Resistance Rds(on):0.025ohm; Rds(on) Test Voltage Vgs:-4.5V; Threshold Voltage Vgs:-1V;

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (15-Jan-2018) |
| No. Of Pins | 6Pins |
| Channel Type | P Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 1.25W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 4.5V |
| Transistor Case Style | TSOP |
| Drain Source Voltage Vds | 20V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 5.1A |
| Drain Source On State Resistance | 0.033ohm |
| Gate Source Threshold Voltage Max | 1V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2845377/)

NTGS3136P, NVGS3136P 

## Power MOSFET 

## **−20 V, −5.8 A, Single P−Channel, TSOP−6** 

## **Features** 

- Low RDS(on) in TSOP−6 Package 

- 1.8 V Gate Rating 

## **www.onsemi.com** 

- Fast Switching 

- NV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable 

**==> picture [191 x 62] intentionally omitted <==**

**----- Start of picture text -----**<br>
V(BR)DSS RDS(ON) TYP ID MAX<br>25 m  @ −4.5 V −5.1 A<br>−20 V 32 m  @ −2.5 V −4.5 A<br>41 m  @ −1.8 V −2.5 A<br>/ eea<br>**----- End of picture text -----**<br>


- These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant 

## **Applications** 

## **P−Channel** 

- Optimized for Battery and Load Management Applications in Portable Equipment 

1 2 5 6 

|Portable Equipment<br>• High Side Load Switch<br>• Switching Circuits for Game Consoles, Camera Phone, etc.<br>**MAXIMUM RATINGS**(TJ= 25°C unless otherwise stated)<br>**Parameter**<br>**Symbol**<br>**Value**<br>**Unit**|||||3<br>4<br>~~‘~~|||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
|Drain−to−Source Voltage<br>VDSS<br>−20<br>V<br>Gate−to−Source Voltage<br>VGS<br>8.0<br>V<br>Continuous Drain<br>Current (Note 1)<br>Steady<br>State<br>TA= 25°C<br>ID<br>−5.1<br>A<br>TA= 85°C<br>−3.6<br>t<br>5 s<br>TA= 25°C<br>−5.8<br>Power Dissipation<br>(Note 1)<br>Steady<br>State<br>TA= 25°C<br>PD<br>1.25<br>W<br>t<br>5 s<br>1.6<br>Continuous Drain<br>Current (Note 2)<br>Steady<br>State<br>TA= 25°C<br>ID<br>−3.7<br>A<br>TA= 85°C<br>−2.7<br>Power Dissipation<br>(Note 2)<br>TA= 25°C<br>PD<br>0.7<br>W<br>Pulsed Drain Current<br>tp= 10 s<br>IDM<br>−20<br>A<br>Operating Junction and Storage Temperature<br>TJ,<br>TSTG<br>−55 to<br>150<br>°C<br>Lead Temperature for Soldering Purposes<br>(1/8” from case for 10 s)<br>TL<br>260<br>°C<br>~~ee~~<br>~~= —~~<br>~~ok~~<br>~~| —~~<br>~~WH} Free~~<br>~~ee~~ ~~ee eeee~~<br>~~a~~~~**e**e~~<br>~~ee~~<br>~~e~~<br>~~ee~~||**TSOP−6**<br>**CASE 318G**<br>**STYLE 1**<br>**MARKING**<br>**DIAGRAM**<br>XXX<br>= Device Code<br>M<br>= Date Code<br>= Pb−Free Package<br>**PIN ASSIGNMENT**<br>4<br>Source<br>5<br>6<br>Drain<br>Drain<br>XXX M<br>1<br>1<br>(Note: Microdot may be in either location)<br>~~O~~e<br>e<br>f~~e~~a<br>|<br>~~_~~||||||||||
|Stresses exceeding those listed in the Maximum Ratings table may damage the|||||3<br>2<br>1|||||||
|device. If any of these limits are exceeded, device functionality should not be|||||Gate<br>Drain<br>Drain|||||||
|assumed, damage may occur and reliability may be affected.||||||||||||



1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces) 

2. Surface−mounted on FR4 board using the minimum recommended pad size (Cu area = 0.0775 in sq). 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2015 **February, 2015 − Rev. 2** 

**NTGS3136P/D** 

**NTGS3136P, NVGS3136P** 

## **THERMAL RESISTANCE MAXIMUM RATINGS** 

|**THERMAL RESISTANCE MAXIMUM RATINGS**||||
|---|---|---|---|
|**Parameter**|**Symbol**|**Value**|**Unit**|
|Junction−to−Ambient – Steady State (Note 3)|R�JA|100|°C/W|
|Junction−to−Ambient – t = 5 s (Note 3)|R�JA|77||
|Junction−to−Ambient – Steady State (Note 4)|R�JA|185||



3. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces) 

4. Surface−mounted on FR4 board using the minimum recommended pad size (Cu area = 0.0775 in sq). 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) 

|**Parameter**|**Symbol**|**Test Condition**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID= −250�A||−20|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/TJ|ID = −250�A, Reference 25°C|||−13||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= −20 V|TJ= 25°C|||−1.0|�A|
||||TJ= 85°C|||−5.0||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS=±8.0 V||||�0.1|�A|
|**ON CHARACTERISTICS**(Note 5)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= −250�A||−0.4||−1.0|V|
|Negative Threshold Temperature Coefficient|VGS(TH)/TJ||||3||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= −4.5 V, ID= −5.1 A|||25|33|m�|
|||VGS= −2.5 V, ID= −4.5 A|||32|40||
|||VGS= −1.8 V, ID= −2.5 A|||41|51||
|Forward Transconductance|gFS|VDS= −5.0 V, ID= −5.1 A|||22||S|
|**CHARGES, CAPACITANCES AND GATE RESISTANCE**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1 MHz, VDS= −10 V|||1901||pF|
|Output Capacitance|COSS||||274|||
|Reverse Transfer Capacitance|CRSS||||175|||
|Total Gate Charge|QG(TOT)|VGS= −4.5 V, VDS= −10 V;<br>ID= −5.1 A|||18|29|nC|
|Threshold Gate Charge|QG(TH)||||0.7|||
|Gate−to−Source Charge|QGS||||2.4|||
|Gate−to−Drain Charge|QGD||||4.3|||
|Gate Resistance|RG||||7.6||�|
|**SWITCHING CHARACTERISTICS**(Note 6)||||||||
|Turn−On Delay Time|td(ON)|VGS= −4.5 V, VDD= −10 V,<br>ID= −1.0 A, RG= 6.0�|||9|19|ns|
|Rise Time|Tr||||9|19||
|Turn−Off Delay Time|td(OFF)||||99|160||
|Fall Time|Tf||||48|79||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= −1.7 A|TJ= 25°C||−0.7|−1.2|V|
||||TJ= 125°C||−0.6|||
|Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt= 100 A/�s,<br>IS= −1.7 A|||37|60|ns|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

5. Pulse Test: pulse width � 300 � s, duty cycle � 2% 

6. Switching characteristics are independent of operating junction temperatures 

**www.onsemi.com** 

**2** 

**NTGS3136P, NVGS3136P** 

## **TYPICAL PERFORMANCE CURVES** (TJ = 25 ° C unless otherwise noted) 

**==> picture [492 x 629] intentionally omitted <==**

**----- Start of picture text -----**<br>
20 20<br>VGS = −4.5 V TJ = 25 ° C VDS = −5 V<br>−2 V −1.8 V<br>16<br>15<br>−2.5 V<br>12<br>10<br>−1.5 V<br>8.0<br>TJ = 25 ° C<br>5<br>4.0 TJ = 125 ° C TJ = −55 ° C<br>0 0<br>0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5<br>−VDS, DRAIN−TO−SOURCE VOLTAGE (V) −VGS, GATE−TO−SOURCE VOLTAGE (V)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>0.14 0.10<br>ID = −5.1 A 0.09 TJ = 25 ° C<br>0.12<br>0.08<br>−1.8 V<br>0.10 0.07<br>0.06<br>0.08<br>0.05<br>0.06 0.04 −2 V<br>0.04 TJ = 125 ° C 0.03 −2.5 V<br>0.02 VGS = −4.5 V<br>0.02 TJ = 25 ° C 0.01<br>0 0<br>1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 4.0 8.0 12 16 20<br>−VGS, GATE−TO−SOURCE VOLTAGE (V) −ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>1.5 2800<br>1.4 VIDGS = −4.5 A = −5.1 V 26002400 VTJGS = 25 = 0 V ° C<br>2200 C iss f = 1 MHz<br>1.3<br>2000<br>1.2 1800<br>1600<br>1.1 1400<br>1200<br>1.0 1000<br>800<br>0.9 600 Coss<br>0.8 400<br>200 Crss<br>0.7 0<br>−50 −25 0 25 50 75 100 125 150 0 2 4 6 8 10 12<br>TJ, JUNCTION TEMPERATURE ( ° C) DRAIN−TO−SOURCE VOLTAGE (V)<br>Figure 5. On−Resistance Variation with Figure 6. Capacitance Variation<br>Temperature<br>DRAIN CURRENT (A) DRAIN CURRENT (A)<br>D,  D,<br>−I −I<br>) � ) �<br>DRAIN−TO−SOURCE RESISTANCE ( DRAIN−TO−SOURCE RESISTANCE (<br>DS(on),  DS(on),<br>R R<br>DRAIN−TO−SOURCE<br>C, CAPACITANCE (pF)<br>DS(on),<br>R RESISTANCE (NORMALIZED)<br>**----- End of picture text -----**<br>


**www.onsemi.com** 

**3** 

**NTGS3136P, NVGS3136P** 

## **TYPICAL PERFORMANCE CURVES** (TJ = 25 ° C unless otherwise noted) 

**==> picture [492 x 175] intentionally omitted <==**

**----- Start of picture text -----**<br>
5 12 30<br>Q T VGS = 0 V<br>4 −VDS 10<br>8 10<br>3 −VGS<br>6 TJ = 150 ° C<br>2 QGS QGD<br>4<br>TJ = 25 ° C<br>1 VDS = −10 V 2<br>ID = −5.1 A<br>TJ = 25 ° C<br>0 0 1.0<br>0 2 4 6 8 10 12 14 16 18 0 0.2 0.4 0.6 0.8 1.0 1.2<br>QG, TOTAL GATE CHARGE (nC) −VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>−V<br>DS<br>, SOURCE CURRENT (A)<br>S<br>−I<br>, GATE−TO−SOURCE VOLTAGE (V)<br>GS<br>−V<br>, DRAIN−TO−SOURCE VOLTAGE (V)<br>**----- End of picture text -----**<br>


**Figure 7. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge** 

**Figure 8. Diode Forward Voltage vs. Current** 

**==> picture [238 x 175] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.8<br>ID = −250 D = −250  = −250  � A<br>0.7<br>0.6<br>0.5<br>0.4<br>0.3<br>0.2<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (J, JUNCTION TEMPERATURE (, JUNCTION TEMPERATURE ( ° C)<br> (V)<br>GS(th)<br>−V<br>**----- End of picture text -----**<br>


**==> picture [492 x 389] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.8 80<br>ID = −250 D = −250  = −250  � A<br>70<br>0.7<br>60<br>0.6<br>50<br>0.5 40<br>30<br>0.4<br>20<br>0.3<br>10<br>0.2 0<br>−50 −25 0 25 50 75 100 125 150 1E−3 1E−2 1E−1 1 1E+1 1E+2 1E+3<br>TJ, JUNCTION TEMPERATURE (J, JUNCTION TEMPERATURE (, JUNCTION TEMPERATURE ( ° C) SINGLE PULSE TIME (s)<br>Figure 9. Threshold Voltage Figure 10. Single Pulse Maximum Power<br>Dissipation<br>100 1<br>10 100  � s Duty Cycle =  0.5<br>1 ms<br>0.2<br>1 0.1<br>10 ms 0.1<br>VGS = −8.0 V<br>SINGLE PULSE<br>0.1 TC = 25 ° C 0.05<br>RDS(on) LIMIT dc 0.01<br>Thermal Limit<br>0.02<br>Package Limit<br>0.01 0.01<br>0.1 1 10 100 1E−04 1E−03 1E−02 1E−01 1 1E+01 1E+02 1E+03<br>−VDS, DRAIN−TO−SOURCE VOLTAGE (V) t, TIME (s)<br> (V)<br>GS(th)<br>−V POWER (W)<br>, DRAIN CURRENT (A)<br>D<br>−I RESPONSE (NORMALIZED)<br>, EFFECTIVE TRANSIENT THERMAL<br>(t)<br>R<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

**Figure 12. FET Thermal Response** 

**www.onsemi.com** 

**4** 

**NTGS3136P, NVGS3136P** 

## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**||||
|---|---|---|---|
|**Device**|**Marking**|**Package**|**Shipping**†|
|NTGS3136PT1G|SD|TSOP−6<br>(Pb−Free)|3000 / Tape & Reel|
|NVGS3136PT1G*|VSD|||



- †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

*NV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable. 

**www.onsemi.com** 

**5** 

**NTGS3136P, NVGS3136P** 

## **PACKAGE DIMENSIONS** 

**TSOP−6** CASE 318G−02 ISSUE V 

- NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 

**==> picture [469 x 321] intentionally omitted <==**

**----- Start of picture text -----**<br>
D 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.<br>H 2. CONTROLLING DIMENSION: MILLIMETERS.<br>3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM<br>LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.<br>6 5 4 L2 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,<br>GAUGE PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR<br>E1 E PLANE GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D<br>ÉÉ AND E1 ARE DETERMINED AT DATUM H.<br>1 2 3 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.<br>ÉÉ L<br>NOTE 5 b M C PLANESEATING DIM MIN MILLIMETERSNOM MAX<br>DETAIL Z A 0.90 1.00 1.10<br>e A1 0.01 0.06 0.10<br>Cian: === b 0.25 0.38 0.50<br>c 0.10 0.18 0.26<br>D 2.90 3.00 3.10<br>A c E 2.50 2.75 3.00 STYLE 1:PIN 1. DRAIN<br>0.05 E1 1.30 1.50 1.70 2. DRAIN<br>e 0.85 0.95 1.05 3. GATE<br>en A1 === L 0.20 0.40 0.60 4. SOURCE<br>DETAIL Z L2M 0° 0.25 BSC− 1 0° 5.6. DRAINDRAIN<br>RECOMMENDED<br>SOLDERING FOOTPRINT*<br>6X<br>is 0.60<br>P O U L<br>3.20 6X<br>0.95<br>Loud<br>0.95<br>PITCH<br>DIMENSIONS: MILLIMETERS<br>**----- End of picture text -----**<br>


*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

ON Semiconductor and the         are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf.  SCILLC reserves the right to make changes without further notice to any products herein.  SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.  All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.  SCILLC does not convey any license under its patent rights nor the rights of others.  SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.  Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.  SCILLC is an Equal Opportunity/Affirmative Action Employer.  This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **PUBLICATION ORDERING INFORMATION** 

**LITERATURE FULFILLMENT** : **N. American Technical Support** : 800−282−9855 Toll Free **ON Semiconductor Website** : **www.onsemi.com** Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA **Europe, Middle East and Africa Technical Support: Order Literature** : http://www.onsemi.com/orderlit **Phone** : 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 **Fax** : 303−675−2176 or 800−344−3867 Toll Free USA/Canada **Japan Customer Focus Center** For additional information, please contact your local **Email** : orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative 

## **LITERATURE FULFILLMENT** : 

**NTGS3136P/D** 

**www.onsemi.com** 

**==> picture [5 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
6<br>**----- End of picture text -----**<br>




## Links

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