# Power MOSFET, N Channel, 60 V, 91 A, 3400 µohm, TO-252 (DPAK), Surface Mount ![Product image](https://novapart.co/image/farnell:2895670/) **URL**: https://novapart.co/products/NTD5C648NLT4G/power-mosfet-n-channel-60-v-91-a-3400-ohm-to-252 **SKU**: NTD5C648NLT4G **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €1.6900 **Stock**: 10+ **Lead Time**: 127 days (indicative) ## Description Transistor Polarity:N Channel; Continuous Drain Current Id:91A; Drain Source Voltage Vds:60V; On Resistance Rds(on):0.0034o; Available until stocks are exhausted Alternative available ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | No SVHC (15-Jan-2018) | | No. Of Pins | 3Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | AEC-Q101 | | Power Dissipation | 76W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | TO-252 (DPAK) | | Drain Source Voltage Vds | 60V | | Operating Temperature Max | 175°C | | Continuous Drain Current Id | 91A | | Drain Source On State Resistance | 3400µohm | | Gate Source Threshold Voltage Max | 2.1V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2895670/) ## NTD5C648NL MOSFET – Power, Single, N-Channel ~~———~~ 60 V, 4.1 m 91 A ## **Features** - Low R to Minimize Conduction Losses DS(on) - Low QG and Capacitance to Minimize Driver Losses - These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant ## **www.onsemi.com** ~~ee~~ **V(BR)DSS RDS(on)** ~~ee ee~~ **ID** 4.1 m @ 10 V 60 V 91 A 5.7 m @ 4.5 V **MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) **==> picture [442 x 353] intentionally omitted <==** **----- Start of picture text -----**
||||||||||||||| |---|---|---|---|---|---|---|---|---|---|---|---|---|---| |es|Parameter|Symbol|Value|Unit|D| |Drain−to−Source Voltage|VDSS|60|V| |Gate−to−Source Voltage|VGS|20|V| |Continuous Drain Cur-|TC = 25|°|C|ID|91|A|G| |rent R|JC (Notes 1 & 3)|Steady|||TC = 100|°|C|||64| |————|Power Dissipation R|JC|State|TC = 25|°|C|P|es|D|76|W|re|S| |(Note 1)|TC = 100|°|C|38|N−CHANNEL MOSFET| |Continuous Drain Cur-|TA = 25|°|C|ID|22|A| |rent R3)|JA (Notes 1, 2 &|Steady|TA = 100|°|C|16|4| |Power Dissipation R|JA|State|TA = 25|°|C|PD|4.4|W|1|[2]| |——a)|(Notes 1 & 2)|F|TA = 100|°|C|eee|2.2|2|3| |ee|Pulsed Drain Current|TA = 25|°|C, t|ed|p = 10 s|IDM|550|A|DPAK| |Operating Junction and Storage Temperature|TJ, Tstg|−55 to|°|C|CASE 369C| |175|STYLE 2| |ee|eee| |Source Current (Body Diode)|IS|85|A| |Single Pulse Drain−to−Source Avalanche|EAS|223|mJ|MARKING DIAGRAM| |a|Energy (IL(pk) = 7.0 A)|& PIN ASSIGNMENT| |Lead Temperature for Soldering Purposes|TL|260|°|C|4| |(1/8|″|from case for 10 s)|Drain| |ee|eee| |Stresses exceeding those listed in the Maximum Ratings table may damage the| |device. If any of these limits are exceeded, device functionality should not be| |assumed, damage may occur and reliability may be affected.| |THERMAL RESISTANCE MAXIMUM RATINGS| |Parameter|Symbol|Value|Unit|2| |a|m1|1|Drain|3| |Junction−to−Case (Drain) (Note 1)|R|JC|2.0|°|C/W|Gate|Source| |Junction−to−Ambient − Steady State (Note 2)|R|JA|34|A| **----- End of picture text -----**
**==> picture [105 x 176] intentionally omitted <==** **----- Start of picture text -----**
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
2
m1 1 Drain 3
Gate Source
A = Assembly Location
Y = Year
WW = Work Week
5C648L = Device Code
G = Pb−Free Package
AYWW 5C 648LG
**----- End of picture text -----**
1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm[2] , 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. ## **ORDERING INFORMATION** See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Publication Order Number: **NTD5C648NL/D** **1** © Semiconductor Components Industries, LLC, 2017 **May, 2019− Rev. 0** **NTD5C648NL** ## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) |**ELECTRICAL CHARACTERISTICS **(TJ|= 25°C unless|otherwise noted)|otherwise noted)||||| |---|---|---|---|---|---|---|---| |**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**| |**OFF CHARACTERISTICS**|||||||| |Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|60|||V| |Drain−to−Source Breakdown Voltage
Temperature Coefficient|V(BR)DSS/TJ||||24||mV/°C| |Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,
VDS= 60 V|TJ= 25°C|||10|�A| ||||TJ= 125°C|||250|| |Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS= 20 V||||100|nA| |**ON CHARACTERISTICS**(Note 4)|||||||| |Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 250�A||1.2||2.1|V| |Negative Threshold Temperature Coefficient|VGS(TH)/TJ||||5.2||mV/°C| |Drain−to−Source On Resistance|RDS(on)|VGS= 10 V, ID= 45 A|||3.4|4.1|m�| |||VGS= 4.5 V, ID= 45 A|||4.6|5.7|| |Forward Transconductance|gFS|VDS= 5.0 V, ID= 45 A|||120||S| |**CHARGES, CAPACITANCES AND GATE RESISTANCES**|||||||| |Input Capacitance|Ciss|VGS= 0 V, f = 1.0 MHz,
VDS= 30 V|||2900||pF| |Output Capacitance|Coss||||1300||| |Reverse Transfer Capacitance|Crss||||28||| |Total Gate Charge|QG(TOT)|VDS= 30 V,
ID= 45 A|VGS= 4.5 V||17||nC| ||||VGS= 10 V||39||| |Threshold Gate Charge|QG(TH)|VGS= 4.5 V, VDS= 30 V,
ID= 45 A|||4.8||nC| |Gate−to−Source Charge|QGS||||8.8||| |Gate−to−Drain Charge|QGD||||3.5||| |Plateau Voltage|VGP||||3.2||V| |**SWITCHING CHARACTERISTICS**(Note 5)|||||||| |Turn−On Delay Time|td(on)|VGS= 4.5 V, VDS= 30 V,
ID= 45 A, RG= 2.5�|||21||ns| |Rise Time|tr||||91||| |Turn−Off Delay Time|td(off)||||47||| |Fall Time|tf||||68||| |**DRAIN−SOURCE DIODE CHARACTERISTICS**|||||||| |Forward Diode Voltage|VSD|VGS= 0 V,
IS= 45 A|TJ= 25°C||0.9|1.2|V| ||||TJ= 125°C||0.8||| |Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt
IS= 45|= 100 A/�s,
A||47||ns| |Charge Time|ta||||23||| |Discharge Time|tb||||24||| |Reverse Recovery Charge|QRR||||30||nC| 4. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperatures. **www.onsemi.com** **2** **NTD5C648NL** ## **TYPICAL CHARACTERISTICS** **==> picture [491 x 591] intentionally omitted <==** **----- Start of picture text -----**
180 180
VGS = 10 V to 4.5 V VDS = 5 V
3.6 V
150 150
3.4 V
120 120
90 3.2 V 90
60 3.0 V 60 TJ = 25 ° C
2.8 V
30 30
2.6 V
0 2.4 V 0 TJ = 125 ° C TJ = −55 ° C
0 0.5 1.0 1.5 2.0 2.5 0 1 2 3 4 5
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
45 8
40 ITDJ = 45 A = 25 ° C 7 TJ = 25 ° C
35
6
30 5 VGS = 4.5 V
25
4
20
15 3 V GS = 10 V
2
10
5 1
0 0
3 4 5 6 7 8 9 10 10 30 50 70 90 110 130 150 170
VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and
Voltage Gate Voltage
2.0 100K
VGS = 10 V TJ = 150 ° C
1.8 ID = 45 A 10K
1.6 1K TJ = 125 ° C
1.4 100 TJ = 85 ° C
1.2 10
1.0 1
0.8 0.1 TJ = 25 ° C
0.6 0.01
−50 −25 0 25 50 75 100 125 150 175 5 10 15 20 25 30 35 40 45 50 55
TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
, DRAIN CURRENT (A) , DRAIN CURRENT (A)
ID ID
) � ) �
, DRAIN−TO−SOURCE RESISTANCE (m , DRAIN−TO−SOURCE RESISTANCE (m
DS(on) DS(on)
R R
, LEAKAGE (nA)
, NORMALIZED DRAIN−TO− IDSS
SOURCE RESISTANCE
DS(on)
R
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**Figure 5. On−Resistance Variation with Temperature** **Figure 6. Drain−to−Source Leakage Current vs. Voltage** **www.onsemi.com** **3** **NTD5C648NL** ## **TYPICAL CHARACTERISTICS** **==> picture [242 x 382] intentionally omitted <==** **----- Start of picture text -----**
10K
CISS
1K
COSS
100
10 CRSS
VGS = 0 V
TJ = 25 ° C
f = 1 MHz
1
0 10 20 30 40 50 60
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
1000
100 tr
tf
td(off)
td(on)
10
VGS = 4.5 V
VDS = 30 V
ID = 45 A
1
1 10 100
RG, GATE RESISTANCE ( � )
C, CAPACITANCE (pF)
t, TIME (ns)
**----- End of picture text -----**
**Figure 9. Resistive Switching Time Variation vs. Gate Resistance** **==> picture [241 x 382] intentionally omitted <==** **----- Start of picture text -----**
10
9 V DS = 30 V
ID = 45 A
8 T J = 25 ° C
7
6
5
4 QGS QGD
3
2
1
0
0 5 10 15 20 25 30 35 40
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source vs. Total Charge
100
VGS = 0 V
10
1
T J = 125 ° C T J = 25 ° C T J = −55 ° C
0.1
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
, GATE−TO−SOURCE VOLTAGE (V)
GS
V
, SOURCE CURRENT (A)
IS
**----- End of picture text -----**
**Figure 10. Diode Forward Voltage vs. Current** **==> picture [492 x 173] intentionally omitted <==** **----- Start of picture text -----**
1000 100
100
TJ(initial) = 25 ° C
10 10
VSingle PulseGS ≤ 10 V 10 � s TJ(initial) = 100 ° C
1 TC = 25 ° C 0.5 ms
RDS(on) Limit 1 ms
Thermal Limit 10 ms
Package Limit
0.1 1
0.1 1 10 100 1000 0.00001 0.0001 0.001 0.01
VDS, DRAIN−TO−SOURCE VOLTAGE (V) TIME IN AVALANCHE (s)
, (A)
IPEAK
, DRAIN CURRENT (A)
ID
**----- End of picture text -----**
**Figure 11. Maximum Rated Forward Biased Safe Operating Area** **Figure 12. Maximum Drain Current vs. Time in Avalanche** **www.onsemi.com** **4** **NTD5C648NL** ## **TYPICAL CHARACTERISTICS** **==> picture [491 x 173] intentionally omitted <==** **----- Start of picture text -----**
10
Duty Cycle = 50%
1
20%
10%
5%
0.1
2%
1%
0.01 Single Pulse
0.001
1E−06 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
PULSE TIME (sec)
C/W)
°
R(t) (
**----- End of picture text -----**
**Figure 13. Thermal Response** ## **ORDERING INFORMATION** |**ORDERING INFORMATION**||| |---|---|---| |**Order Number**|**Package**|**Shipping**†| |NTD5C648NLT4G|DPAK
(Pb−Free)|2500 / Tape & Reel| †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. **www.onsemi.com** **5** MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **==> picture [487 x 115] intentionally omitted <==** **----- Start of picture text -----**
4 DPAK (SINGLE GAUGE)
CASE 369C
ISSUE G
1 [2]
3 DATE 31 MAY 2023
SCALE 1:1
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**==> picture [482 x 257] intentionally omitted <==** **----- Start of picture text -----**
GENERIC
MARKING DIAGRAM*
XXXXXXG AYWW
ALYWW XXX
XXXXXG
IC Discrete
XXXXXX = Device Code
A = Assembly Location
L = Wafer Lot
STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5: Y = Year
PIN 1. BASE PIN 1. GATE PIN 1. ANODE PIN 1. CATHODE PIN 1. GATE WW = Work Week
2. COLLECTOR 2. DRAIN 2. CATHODE 2. ANODE 2. ANODE
3. EMITTER 3. SOURCE 3. ANODE 3. GATE 3. CATHODE G = Pb−Free Package
4. COLLECTOR 4. DRAIN 4. CATHODE 4. ANODE 4. ANODE
*This information is generic. Please refer to
STYLE 6: STYLE 7: STYLE 8: STYLE 9: STYLE 10: device data sheet for actual part marking.
PIN 1. MT1 PIN 1. GATE PIN 1. N/C PIN 1. ANODE PIN 1. CATHODE Pb−Free indicator, “G” or microdot “ � ”, may
2.3. MT2GATE 2.3. COLLECTOREMITTER 2.3. CATHODEANODE 2.3. RESISTOR ADJUSTCATHODE 2.3. ANODECATHODE or may not be present. Some products may
4. MT2 4. COLLECTOR 4. CATHODE 4. CATHODE 4. ANODE not follow the Generic Marking.
**----- End of picture text -----**
## **DOCUMENT NUMBER:** ## **98AON10527D** **DESCRIPTION: DPAK (SINGLE GAUGE)** Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **PAGE 1 OF 1** **onsemi** and are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2018 **onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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