# Power MOSFET, N Channel, 60 V, 46 A, 0.016 ohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:1879962/)

**URL**: https://novapart.co/products/NTD5865NLT4G/power-mosfet-n-channel-60-v-46-a-0016-ohm-to-252
**SKU**: NTD5865NLT4G
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.6230
**Stock**: 1000+
**Lead Time**: 2 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:46A; Drain Source Voltage Vds:60V; On Resistance Rds(on):0.016ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:1V; P

## Specifications

| Parameter | Value |
|---|---|
| Msl | - |
| Svhc | Lead (17-Jan-2022) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 52W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 60V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 46A |
| Drain Source On State Resistance | 0.016ohm |
| Gate Source Threshold Voltage Max | 1V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:1879962/)

## NTD5865NL N-Channel Power MOSFET 60 V, 46 A, 16 m . 

## **Features** 

- Low Gate Charge 

- Fast Switching 

- High Current Capability 

- 100% Avalanche Tested 

- These Devices are Pb−Free, Halogen Free and are RoHS Compliant 

## **MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) 

**Parameter Symbol Value Unit** Drain−to−Source Voltage VDSS 60 V Gate−to−Source Voltage − Continuous VGS ± 20 V Gate−to−Source Voltage VGS ± 30 V − Non−Repetitive (tp < 10 s) ~~r~~ Continuous Drain ~~e~~ TC = 25 ° C ~~ee~~ ID 46 A ~~ee~~ Current (R JC) Steady TC = 100 ° C 33 Power Dissipation State TC = 25 ° C PD 71 W (R JC) ~~pf Ft~~ Pulsed Drain Current tp = 10 s IDM 203 A Operating Junction and Storage Temperature TJ, Tstg −55 to ° C ~~> 4~~ 175 Source Current (Body Diode) IS 46 A ~~ee~~ Single Pulse Drain−to−Source (L = EAS 36 mJ Avalanche Energy 0.1 mH) ~~a eeOO~~ IAS 27 A Lead Temperature for Soldering Purposes TL 260 ° C (1/8 ″ from case for 10 s) ~~reee ee~~ Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

## **THERMAL RESISTANCE MAXIMUM RATINGS** 

|**Parameter**|**Symbol**|**Value**|**Unit**|
|---|---|---|---|
|Junction−to−Case (Drain)|R JC|2.1|°C/W|
|Junction−to−Ambient − SteadyState(Note 1)|R JA|49||



1. Surface−mounted on FR4 board using a 650 mm[2] , 2 oz. Cu pad. 

## **http://onsemi.com** 

|**V(BR)DSS**|**RDS(on) MAX**|**ID MAX**|
|---|---|---|
|60 V|16 m @ 10 V<br>19 m @ 4.5 V|46 A|



**==> picture [159 x 401] intentionally omitted <==**

**----- Start of picture text -----**<br>
D<br>N−Channel<br>G<br>rey S<br>4<br>4<br>1<br>1 [2] ®<br>3 2 3<br>DPAK IPAK<br>CASE 369AA CASE 369D<br>(Surface Mount) (Straight Lead)<br>STYLE 2 STYLE 2<br>MARKING DIAGRAMS<br>& PIN ASSIGNMENT<br>4<br>Drain<br>4<br>Drain<br>a 2 Oy<br>1 Drain 3 1 2 3<br>Gate Source Gate Drain Source<br>A = Assembly Location*<br>Y = Year<br>WW = Work Week<br>5865NL = Device Code<br>G = Pb−Free Package<br>AYWW 58 65NLG<br>AYWW 58 65NLG<br>**----- End of picture text -----**<br>


* The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information on page 5 of this data sheet. 

Publication Order Number: **NTD5865NL/D** 

**1** 

© Semiconductor Components Industries, LLC, 2014 **September, 2014 − Rev. 4** 

## **NTD5865NL** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) 

|**ELECTRICAL CHARACTERISTIC**|**S **(TJ= 25°C un|less otherwise noted)|less otherwise noted)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|60|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/TJ||||55||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 60 V|TJ= 25°C|||1.0|�A|
||||TJ= 150°C|||100||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS=±20 V||||±100|nA|
|**ON CHARACTERISTICS**(Note 2)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 250�A||1.0||2.0|V|
|Negative Threshold Temperature Co-<br>efficient|VGS(TH)/TJ||||5.6||mV/°C|
|Drain−to−Source on Resistance|RDS(on)|VGS= 10 V, ID= 20 A|||13|16|m�|
|Drain−to−Source on Resistance|RDS(on)|VGS= 4.5 V, ID= 20 A|||16|19|m�|
|Forward Transconductance|gFS|VDS= 15 V, ID= 20 A|||15||S|
|**CHARGES, CAPACITANCES AND GATE RESISTANCES**||||||||
|Input Capacitance|Ciss|VGS= 0 V, f = 1.0 MHz,<br>VDS= 25 V|||1400||pF|
|Output Capacitance|Coss||||137|||
|Reverse Transfer Capacitance|Crss||||95|||
|Total Gate Charge|QG(TOT)|VGS= 10 V, VDS= 48 V,<br>ID= 40 A|||29||nC|
|Threshold Gate Charge|QG(TH)||||1.1|||
|Gate−to−Source Charge|QGS||||4|||
|Gate−to−Drain Charge|QGD||||8|||
|Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 48 V,<br>ID= 40 A|||15||nC|
|Gate Resistance|RG||||1.3||�|
|**SWITCHING CHARACTERISTICS**(Note 3)||||||||
|Turn−On Delay Time|td(on)|VGS= 10 V, VDD= 48 V,<br>ID= 40 A, RG= 2.5�|||8.4||ns|
|Rise Time|tr||||12.4|||
|Turn−Off Delay Time|td(off)||||26|||
|Fall Time|tf||||4.4|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 40 A|TJ= 25°C||0.95|1.2|V|
||||TJ= 125°C||0.85|||
|Reverse Recovery Time|tRR|VGS= 0 V, dIs/dt<br>IS= 40|= 100 A/�s,<br>A||20||ns|
|Charge Time|ta||||13|||
|Discharge Time|tb||||7|||
|Reverse Recovery Charge|QRR||||13||nC|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 

3. Switching characteristics are independent of operating junction temperatures. 

**http://onsemi.com** 

**2** 

**NTD5865NL** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [243 x 159] intentionally omitted <==**

**----- Start of picture text -----**<br>
80<br>70 VGS = 10 V 4 V 3.8 V TJ = 25 ° C<br>4.5 V<br>60<br>3.6 V<br>50<br>3.4 V<br>40<br>3.2 V<br>30<br>20 3 V<br>10 2.8 V<br>2.6 V<br>0<br>0 1 2 3 4 5<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


VDS, DRAIN−TO−SOURCE VOLTAGE (V) 

**Figure 1. On−Region Characteristics** 

**==> picture [237 x 174] intentionally omitted <==**

**----- Start of picture text -----**<br>
80<br>VDS ≥  10 V<br>70<br>60<br>50<br>40<br>30 TJ = 25 ° C<br>20<br>10 T J  = 125 ° C TJ = −55 ° C<br>0<br>1 2 3 4 5<br>VGS, GATE−TO−SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 2. Transfer Characteristics** 

**==> picture [493 x 423] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.030 0.018<br>ID = 40 A TJ = 25 ° C<br>TJ = 25 ° C VGS = 4.5 V<br>0.025 0.016<br>0.020 0.014<br>VGS = 10 V<br>0.015 0.012<br>0.010 0.010<br>2 3 4 5 6 7 8 9 10 5 10 15 20 25 30 35 40<br>VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance vs. Gate Voltage Figure 4. On−Resistance vs. Drain Current<br>2.2 10000<br>2.0 ID = 38 A VGS = 0 V<br>VGS = 10 V TJ = 150 ° C<br>1.8<br>1.6<br>1.4 1000<br>TJ = 125 ° C<br>1.2<br>1.0<br>0.8<br>0.6 100<br>−50 −25 0 25 50 75 100 125 150 175 10 20 30 40 50 60<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current<br>Temperature vs. Voltage<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (nA)<br>IDSS<br>, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


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**3** 

**NTD5865NL** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [492 x 174] intentionally omitted <==**

**----- Start of picture text -----**<br>
1800 10<br>1600 VTJGS = 25 = 0 V ° C QT<br>1400 Ciss 8<br>1200<br>6<br>1000<br>800<br>600 4 Qgs Q gd<br>400<br>2 VDS = 48 V<br>200 Coss ID = 40 A<br>0 Crss 0 TJ = 25 ° C<br>0 10 20 30 40 50 60 0 5 10 15 20 25 30<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)<br>C, CAPACITANCE (pF)<br>, GATE−TO−SOURCE VOLTAGE (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 7. Capacitance Variation** 

**Figure 8. Gate−to−Source vs. Total Charge** 

**==> picture [493 x 174] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000 40<br>VIDDD = 40 A = 48 V 35 VTJGS = 25 = 0 V ° C<br>VGS = 10 V 30<br>100<br>25<br>td(off) 20<br>10 tr td(on) 15<br>10<br>tf<br>5<br>1 0<br>1 10 100 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00<br>RG, GATE RESISTANCE ( � ) VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>t, TIME (ns)<br>, SOURCE CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 9. Resistive Switching Time Variation vs. Gate Resistance** 

**Figure 10. Diode Forward Voltage vs. Current** 

**==> picture [245 x 175] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000<br>VGS = 10 V<br>SINGLE PULSE<br>100 TC = 25 ° C 100  � s<br>10 ms 1 ms 10  � s<br>10<br>dc<br>1<br>RDS(on) LIMIT<br>THERMAL LIMIT<br>PACKAGE LIMIT<br>0.1<br>0.1 1 10 100<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

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**4** 

**NTD5865NL** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [488 x 186] intentionally omitted <==**

**----- Start of picture text -----**<br>
10<br>Duty Cycle = 0.5<br>1<br>0.2<br>0.1<br>0.05<br>0.02<br>0.1<br>0.01<br>SINGLE PULSE<br>0.01<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1<br>t, PULSE TIME (s)<br>Figure 12. Thermal Response<br>C/W) EFFECTIVE TRANSIENT<br> ( ° THERMAL RESISTANCE<br>JC(t)<br>�<br>R<br>**----- End of picture text -----**<br>


## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**|||
|---|---|---|
|**Order Number**|**Package**|**Shipping**†|
|NTD5865NL−1G|IPAK (Straight Lead)<br>(Pb−Free)|75 Units / Rail|
|NTD5865NLT4G|DPAK<br>(Pb−Free)|2500 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

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**5** 

**NTD5865NL** 

## **PACKAGE DIMENSIONS** 

**DPAK (SINGLE GUAGE)** CASE 369AA ISSUE B 

**==> picture [466 x 369] intentionally omitted <==**

**----- Start of picture text -----**<br>
NOTES:<br>C 1. DIMENSIONING AND TOLERANCING PER ASME<br>A Y14.5M, 1994.<br>E A 2.3. CONTROLLING DIMENSION: INCHES.THERMAL PAD CONTOUR OPTIONAL WITHIN DI-<br>MENSIONS b3, L3 and Z.<br>b3 B c2 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD<br>FLASH, PROTRUSIONS, OR BURRS. MOLD<br>FLASH, PROTRUSIONS, OR GATE BURRS SHALL<br>NOT EXCEED 0.006 INCHES PER SIDE.<br>L3 4 Z 5. DIMENSIONS D AND E ARE DETERMINED AT THEOUTERMOST EXTREMES OF THE PLASTIC BODY.<br>1 2 3 D DETAIL A H 6. DATUMS A AND B ARE DETERMINED AT DATUMPLANE H.<br>INCHES MILLIMETERS<br>DIM MIN MAX MIN MAX<br>L4 A 0.086 0.094 2.18 2.38<br>b2 A1 0.000 0.005 0.00 0.13<br>b c b 0.025 0.035 0.63 0.89<br>b2 0.030 0.045 0.76 1.14<br>e 0.005 (0.13) M C H b3 0.180 0.215 4.57 5.46<br>c 0.018 0.024 0.46 0.61<br>L2 [GAUGE] PLANE C SEATINGPLANE c2D 0.0180.235 0.0240.245 0.465.97 0.616.22<br>E 0.250 0.265 6.35 6.73<br>e 0.090 BSC 2.29 BSC<br>H 0.370 0.410 9.40 10.41<br>L A1 L 0.055 0.070 1.40 1.78<br>L1 L1 0.108 REF 2.74 REF<br>L2 0.020 BSC 0.51 BSC<br>DETAIL A L3 0.035 0.050 0.89 1.27<br>ROTATED 90  CW � L4 −−− 0.040 −−− 1.01<br>Z 0.155 −−− 3.93 −−−<br>SOLDERING FOOTPRINT* STYLE 2:<br>PIN 1. GATE<br>2. DRAIN<br>6.20 3.00 3. SOURCE<br>0.244 0.118 4. DRAIN<br>2.58<br>0.102<br>5.80<br>1.60 6.17<br>0.228<br>0.063 0.243<br>SCALE 3:1<br>� inches [mm] �<br>**----- End of picture text -----**<br>


*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

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**6** 

**NTD5865NL** 

## **PACKAGE DIMENSIONS** 

**IPAK** CASE 369D ISSUE C 

**==> picture [432 x 193] intentionally omitted <==**

**----- Start of picture text -----**<br>
B C NOTES:<br>1. DIMENSIONING AND TOLERANCING PER<br>V R E ANSI Y14.5M, 1982.<br>2. CONTROLLING DIMENSION: INCH.<br>INCHES MILLIMETERS<br>4 Z DIM MIN MAX MIN MAX<br>A 0.235 0.245 5.97 6.35<br>S A B 0.250 0.265 6.35 6.73<br>HF 1 2 3 o t eee C 0.086 0.094 2.19 2.38<br>D 0.027 0.035 0.69 0.88<br>E 0.018 0.023 0.46 0.58<br>−T− F 0.037 0.045 0.94 1.14<br>SEATING G 0.090 BSC 2.29 BSC<br>PLANE K H 0.034 0.040 0.87 1.01<br>J 0.018 0.023 0.46 0.58<br>K 0.350 0.380 8.89 9.65<br>R 0.180 0.215 4.45 5.45<br>J S 0.025 0.040 0.63 1.01<br>F<br>H V 0.035 0.050 0.89 1.27<br>Z 0.155 −−− 3.93 −−−<br>D 3 PL<br>STYLE 2:<br>G 0.13 (0.005) M T PIN 1. GATE<br>2. DRAIN<br>3. SOURCE<br>4. DRAIN<br>**----- End of picture text -----**<br>


ON Semiconductor and the         are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf.  SCILLC reserves the right to make changes without further notice to any products herein.  SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.  All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.  SCILLC does not convey any license under its patent rights nor the rights of others.  SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.  Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.  SCILLC is an Equal Opportunity/Affirmative Action Employer.  This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **PUBLICATION ORDERING INFORMATION** 

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**NTD5865NL/D** 

**7** 



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