# Power MOSFET, N Channel, 40 V, 101 A, 3600 µohm, TO-252 (DPAK), Surface Mount ![Product image](https://novapart.co/image/farnell:2724410RL/) **URL**: https://novapart.co/products/NTD5802NT4G/power-mosfet-n-channel-40-v-101-a-3600-ohm-to-252 **SKU**: NTD5802NT4G **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.7660 **Stock**: 10+ **Lead Time**: 61 days (indicative) ## Description Transistor Polarity:N Channel; Continuous Drain Current Id:101A; Drain Source Voltage Vds:40V; On Resistance Rds(on):0.0036ohm; Available until stocks are exhausted Alternative available ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | Lead (10-Jun-2022) | | No. Of Pins | 3Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | - | | Power Dissipation | 93.75W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | TO-252 (DPAK) | | Drain Source Voltage Vds | 40V | | Operating Temperature Max | 175°C | | Continuous Drain Current Id | 101A | | Drain Source On State Resistance | 3600µohm | | Gate Source Threshold Voltage Max | 3.5V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2724410RL/) NTD5802N, NVD5802N ## Power MOSFET ## **40 V, Single N−Channel, 101 A DPAK** ## **Features** - Low R to Minimize Conduction Losses DS(on) - Low Capacitance to Minimize Driver Losses **www.onsemi.com** - Optimized Gate Charge to Minimize Switching Losses - MSL 1/260°C ||~~ee~~|~~ee~~| |---|---|---| |**V(BR)DSS**
~~rs~~|**RDS(on)**
~~rs~~
~~ee~~|**ID**
~~rs~~
~~ee~~| |40 V|4.4 m @ 10 V
~~ee~~|101 A
~~ee~~| ||7.8 m @ 5.0 V|50 A| - 100% Avalanche Tested - NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable |• MSL 1/260°C°CC
• 100% Avalanche Tested
• NVD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable|40 V
4.4 m @ 10 V
**RDS(on)**
101 A
**ID**
**V(BR)DSS**
7.8 m @ 5.0 V
50 A
~~rs~~
~~ee~~
~~ee~~| |---|---| |• These Devices are Pb−Free and are RoHS Compliant|D| |**Applications**|| |• CPU Power Delivery|**N−Channel**| |• DC−DC Converters
• Motor Driver|G| ||S| |**MAXIMUM RATINGS**(TJ= 25°C unless otherwise noted)
**Parameter**
**Symbol**
**Value**
**Unit**
Drain−to−Source Voltage
VDSS
40
V
Gate−to−Source Voltage
VGS
±20
V
Continuous Drain Cur-
rent (R JC) (Note 1)
Steady
State
TC= 25°C
ID
101
A
TC= 85°C
78
Power Dissipation
(R JC) (Note 1)
TC= 25°C
PD
93.75
W
Continuous Drain Cur-
rent (R JA) (Note 1)
TA= 25°C
ID
16.4
A
TA= 85°C
12.7
~~———++~~
~~ee~~
ee
~~CT~~
~~ee~~
~~ee ee~~
~~Pe)~~|**CASE 369C**
**DPAK**
**(Bent Lead)**
**STYLE 2**
**MARKING DIAGRAMS**
**& PIN ASSIGNMENT**
1 2
3
4
~~°~~°| |Power Dissipation
(R JA) (Note 1)
TA= 25°C
PD
2.5
W
Pulsed Drain Current
tp=10 s
TA= 25°C
IDM
300
A
Current Limited by Package
TA= 25°C
IDmaxPkg
45
A
Operating Junction and Storage Temperature
TJ, Tstg
−55 to
175
°C
Source Current (Body Diode)
IS
50
A
Drain to Source dV/dt
dV/dt
6.0
V/ns
Single Pulse Drain−to−Source Avalanche En-
ergy (VDD= 32 V, VGS= 10 V,
L = 0.3 mH, IL(pk)= 40 A, RG= 25 )
EAS
240
mJ
Lead Temperature for Soldering Purposes
(1/8″from case for 10 s)
TL
260
°C
1
Gate
2
Drain 3
Source
4
Drain
AYWW
58
02NG
A
= Assembly Location*
Y
= Year
WW
= Work Week
5802N = Device Code
G
= Pb−Free Package
* The Assembly Location code (A) is front side
~~ee ee~~
~~Ss~~
~~po~~
~~ee~~
~~pe Td~~
~~ee~~|| - These Devices are Pb−Free and are RoHS Compliant ## **Applications** - CPU Power Delivery - DC−DC Converters - Motor Driver * The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ## **ORDERING INFORMATION** See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Publication Order Number: **NTD5802N/D** **1** © Semiconductor Components Industries, LLC, 2014 **May, 2017 − Rev. 8** **NTD5802N, NVD5802N** ## **THERMAL RESISTANCE MAXIMUM RATINGS** |**THERMAL RESISTANCE MAXIMUM RATINGS**|||| |---|---|---|---| |**Parameter**|**Symbol**|**Value**|**Unit**| |Junction−to−Case (Drain)|R�JC|1.6|°C/W| |Junction−to−Ambient − Steady State (Note 1)|R�JA|60|| |Junction−to−Ambient − SteadyState(Note 2)|R�JA|105|| 1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. ## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) |**ELECTRICAL CHARACTERISTIC**|**S **(TJ= 25°C un|less otherwise noted)|less otherwise noted)||||| |---|---|---|---|---|---|---|---| |**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**| |**OFF CHARACTERISTICS**|||||||| |Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID|= 10�A|40|||V| |Drain−to−Source Breakdown Voltage
Temperature Coefficient|V(BR)DSS/TJ||||40||mV/°C| |Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,
VDS= 40 V|TJ= 25°C|||1.0|�A| ||||TJ= 150°C|||50|| |Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS=±20 V||||±100|nA| |**ON CHARACTERISTICS**(Note 3)|||||||| |Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 250�A||1.5||3.5|V| |Negative Threshold Temperature Co-
efficient|VGS(TH)/TJ||||−7.4||mV/°C| |Drain−to−Source On Resistance|RDS(on)|VGS= 10 V, ID= 50 A|||3.6|4.4|m�| |||VGS= 5.0 V, ID= 50 A|||6.5|7.8|| |Forward Transconductance|gFS|VDS= 15 V, ID= 15 A|||16.8||S| |**CHARGES AND CAPACITANCES**|||||||| |Input Capacitance|Ciss|VGS= 0 V, f = 1.0 MHz,
VDS= 12 V|||5300||pF| |Output Capacitance|Coss||||850||| |Reverse Transfer Capacitance|Crss||||550||| |Input Capacitance|Ciss|VGS= 0 V, f = 1.0 MHz,
VDS= 25 V|||5025||pF| |Output Capacitance|Coss||||580||| |Reverse Transfer Capacitance|Crss||||400||| |Total Gate Charge|QG(TOT)|VGS= 10 V, VDS= 15 V,
ID= 50 A|||75|100|nC| |Threshold Gate Charge|QG(TH)||||6.0||| |Gate−to−Source Charge|QGS||||18||| |Gate−to−Drain Charge|QGD||||15||| |**SWITCHING CHARACTERISTICS**(Note 4)|||||||| |Turn−On Delay Time|td(on)|VGS= 10 V, VDS= 20 V,
ID= 50 A, RG= 2.0�|||14||ns| |Rise Time|tr||||52||| |Turn−Off Delay Time|td(off)||||39||| |Fall Time|tf||||8.5||| Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. **www.onsemi.com** **2** **NTD5802N, NVD5802N** ## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) (continued) |**ELECTRICAL CHARACTERISTIC**|**S **(TJ= 25°C u|nless otherwise noted) (continued)|nless otherwise noted) (continued)||||| |---|---|---|---|---|---|---|---| |**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**| |**DRAIN−SOURCE DIODE CHARACTERISTICS**|||||||| |Forward Diode Voltage|VSD|VGS= 0 V,
IS= 50 A|TJ= 25°C||0.9|1.2|V| |||VGS= 0 V,
IS= 20 A|TJ= 25°C||0.8|1.0|| |Reverse Recovery Time|tRR|VGS= 0 V, dIs/dt = 100 A/�s,
IS= 50 A|||25||ns| |Charge Time|ta||||15||| |Discharge Time|tb||||10||| |Reverse Recovery Charge|QRR||||15||nC| Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. **www.onsemi.com** **3** **NTD5802N, NVD5802N** ## **TYPICAL PERFORMANCE CHARACTERISTICS** **==> picture [238 x 170] intentionally omitted <==** **----- Start of picture text -----**
200
10 V 6 V
180 VGS = 5 V
7 V
160
140 TJ = 25 ° C
120 4.5 V
100
80 4.2 V
60
4 V
40
3.8 V
20 3.6 V
0
0 1 2 3 4 5 6
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
, DRAIN CURRENT (A)
ID
**----- End of picture text -----**
**Figure 1. On−Region Characteristics** **==> picture [237 x 170] intentionally omitted <==** **----- Start of picture text -----**
200
VDS ≥ 10 V
150
100 T J = 25 ° C
50 T J = 100 ° C
TJ = −55 ° C
0
2 3 4 5 6
VGS, GATE−TO−SOURCE VOLTAGE (V)
, DRAIN CURRENT (A)
ID
**----- End of picture text -----**
**Figure 2. Transfer Characteristics** **==> picture [484 x 407] intentionally omitted <==** **----- Start of picture text -----**
0.010 0.015
VGS = 10 V 0.014 TJ = 25 ° C
0.013 VGS = 5 V
0.012
0.008
0.011
TJ = 150 ° C 0.010
0.009
0.006
0.008
0.007
TJ = 25 ° C 0.006
0.004 0.005
TJ = −55 ° C 0.004 VGS = 10 V
0.003
0.002 0.002
10 30 50 70 90 110 130 150 170 190 30 50 70 90 110 130 150 170 190
ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Drain Current Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.7 100000
1.6 ID = 50 A VGS = 0 V
VGS = 10 V
1.5
1.4 10000 TJ = 150 ° C
1.3
1.2
1.1
1000
1
TJ = 100 ° C
0.9
0.8
0.7 100
−50 −25 0 25 50 75 100 125 150 175 2 6 10 14 18 22 26 30 34 38
TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
) � ) �
, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (
DS(on) DS(on)
R R
, LEAKAGE (nA)
(NORMALIZED)
IDSS
, DRAIN−TO−SOURCE RESISTANCE
DS(on)
R
**----- End of picture text -----**
**Figure 5. On−Resistance Variation with Temperature** **Figure 6. Drain−to−Source Leakage Current vs. Voltage** **www.onsemi.com** **4** **NTD5802N, NVD5802N** ## **TYPICAL PERFORMANCE CHARACTERISTICS** **==> picture [493 x 394] intentionally omitted <==** **----- Start of picture text -----**
8000 15 30
7000 Ciss V T JGS = 25 = 0 V ° C TIDJ = 50 A = 25 ° C
12 24
6000 QT
5000 9 VDS VGS 18
4000
6 12
3000 QGS QDS
2000
Coss 3 6
1000
Crss
0 0 0
10 5 0 5 10 15 20 25 30 35 40 0 20 40 60 80
VGS VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLT- Qg, TOTAL GATE CHARGE (nC)
AGE (V) Figure 8. Gate−to−Source and
Figure 7. Capacitance Variation Drain−to−Source Voltage vs. Total Charge
1000 60
VDD = 20 V
VIDGS = 50 A = 10 V td(off) 50 VTJGS = 25 = 0 V ° C
tr
100 40
tf td(on) 30
10 20
10
1 0
1 10 100 0.4 0.6 0.8 1.0 1.2 1.4
RG, GATE RESISTANCE ( � ) VSD, SOURCE−TO−DRAIN VOLTAGE (V)
C, CAPACITANCE (pF)
, GATE−TO−SOURCE VOLTAGE (V) , DRAIN−TO−SOURCE VOLTAGE (V)
GS DS
V V
t, TIME (ns)
, SOURCE CURRENT (A)
IS
**----- End of picture text -----**
**Figure 9. Resistive Switching Time Variation vs. Gate Resistance** **Figure 10. Diode Forward Voltage vs. Current** **==> picture [243 x 173] intentionally omitted <==** **----- Start of picture text -----**
1000
100
10 � s
100 � s
10
1 ms
VGS = 10 V 10 ms
Single Pulse
1 TC = 25 ° C dc
RDS(on) Limit
Thermal Limit
Package Limit
0.1
0.1 1 10 100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
, DRAIN CURRENT (A)
ID
**----- End of picture text -----**
**Figure 11. Maximum Rated Forward Biased Safe Operating Area** **www.onsemi.com** **5** **NTD5802N, NVD5802N** ## **TYPICAL PERFORMANCE CHARACTERISTICS** **==> picture [494 x 174] intentionally omitted <==** **----- Start of picture text -----**
10
D = 0.5
1
0.2
0.1
0.05
0.1
0.02
0.01
Single Pulse
0.01
0.00001 0.0001 0.001 0.01 0.1 1
t, PULSE TIME (s)
C/W)
( °
r(t), Effective Transient Thermal Resistance
**----- End of picture text -----**
**Figure 12. Thermal Response** ## **ORDERING INFORMATION** |**ORDERING INFORMATION**||| |---|---|---| |**Order Number**|**Package**|**Shipping**†| |NTD5802NT4G|DPAK
(Pb−Free)|2500 / Tape & Reel| |NVD5802NT4G*|DPAK
(Pb−Free)|2500 / Tape & Reel| |NVD5802NT4G−VF01|DPAK
(Pb−Free)|2500 / Tape & Reel| - †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable. **www.onsemi.com** **6** **NTD5802N, NVD5802N** ## **PACKAGE DIMENSIONS** **==> picture [481 x 447] intentionally omitted <==** **----- Start of picture text -----**
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
NOTES:
A 1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
E C 2. CONTROLLING DIMENSION: INCHES.
A 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
b3 B c2 4. DIMENSIONS D AND E DO NOT INCLUDE MOLDMENSIONS b3, L3 and Z.
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
4 NOT EXCEED 0.006 INCHES PER SIDE.
L3 bale HE, Z 5. DIMENSIONS D AND E ARE DETERMINED AT THE
D DETAIL A H OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
1 2 3 PLANE H.
7. OPTIONAL MOLD FEATURE.
L4 NOTE 7 DIM MININCHESMAX MILLIMETERSMIN MAX
b2 c BOTTOM VIEW A 0.086 0.094 2.18 2.38
e SIDE VIEW A1 0.000 0.005 0.00 0.13
b b 0.025 0.035 0.63 0.89
TOP VIEW 0.005 (0.13) M C b2b3 0.0280.180 0.0450.215 0.724.57 1.145.46
c 0.018 0.024 0.46 0.61
c2 0.018 0.024 0.46 0.61
H Z Z D 0.235 0.245 5.97 6.22
E 0.250 0.265 6.35 6.73
e 0.090 BSC 2.29 BSC
L2 [GAUGE] PLANE C SEATINGPLANE HL 0.3700.055 0.4100.070 9.401.40 10.411.78
L1 0.114 REF 2.90 REF
L2 0.020 BSC 0.51 BSC
L L3 0.035 0.050 0.89 1.27
A1 BOTTOM VIEW L4 −−− 0.040 −−− 1.01
pgs L1 at CONSTRUCTIONSALTERNATE eb Z 0.155 −−− 3.93 −−−
DETAIL A STYLE 2:
ROTATED 9 CW SOLDERING FOOTPRINT* PIN 1. GATE
2. DRAIN
3. SOURCE
6.20 3.00 4. DRAIN
0.244 0.118
2.58
PP
0.102
5.80
1.60 6.17
0.228
0.063 0.243
mee
SCALE 3:1 mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
**----- End of picture text -----**
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