# Power MOSFET, N Channel, 30 V, 41 A, 0.0065 ohm, TO-252 (DPAK), Surface Mount ![Product image](https://novapart.co/image/farnell:2724407/) **URL**: https://novapart.co/products/NTD4909NT4G/power-mosfet-n-channel-30-v-41-a-00065-ohm-to-252 **SKU**: NTD4909NT4G **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.1280 **Stock**: 10+ ## Specifications | Parameter | Value | |---|---| | No. Of Pins | 3Pins | | Channel Type | N Channel | | Power Dissipation | 29.4W | | Transistor Mounting | Surface Mount | | Transistor Polarity | N Channel | | Power Dissipation Pd | 29.4W | | Rds(On) Test Voltage | 10V | | On Resistance Rds(On) | 0.0065ohm | | Transistor Case Style | TO-252 (DPAK) | | Drain Source Voltage Vds | 30V | | Operating Temperature Max | 175°C | | Continuous Drain Current Id | 41A | | Drain Source On State Resistance | 0.0065ohm | | Gate Source Threshold Voltage Max | 1.7V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2724407/) ## NTD4909N ## Power MOSFET **30 V, 41 A, Single N−Channel, DPAK/IPAK** ## **Features** - Low R to Minimize Conduction Losses DS(on) - Low Capacitance to Minimize Driver Losses - Optimized Gate Charge to Minimize Switching Losses ## **http://onsemi.com** - These are Pb−Free Devices **Applications V(BR)DSS RDS(on) MAX ID MAX** • CPU Power Delivery 30 V 8.0 m @ 10 V 41 A • DC−DC Converters 12 m @ 4.5 V **MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) D **Parameter Symbol Value Unit** Drain−to−Source Voltage VDSS 30 V **N−Channel** Gate−to−Source Voltage VGS 20 V G Continuous Drain TA = 25 ° C ID 12.1 A (Note 1)Current (R JA) TA = 100 ° C 8.6 S ~~Ss~~ Power Dissipation TA = 25 ° C PD 2.6 W 4 (R JA) (Note 1) 4 Continuous Drain TA = 25 ° C ID 8.8 A 4 (Note 2)Current (R JA) Steady TA = 100 ° C 6.2 Power Dissipation State TA = 25 ° C PD 1.37 W 1[2] 3 1 2 3 1 2 3 (R JA) (Note 2) Continuous Drain TC = 25 ° C ID 41 A **CASE 369AA CASE 369AD CASE 369D** (Note 1)Current (R JC) TC = 100 ° C 29 **(Bent Lead)DPAK (Straight Lead)IPAK (Straight LeadIPAK** Power Dissipation TC = 25 ° C PD 29.4 W **STYLE 2 DPAK)** (R JC) (Note 1) **MARKING DIAGRAMS** Pulsed Drain Current tp=10 s TA = 25 ° C IDM 167 A **& PIN ASSIGNMENTS** Current Limited by Package TA = 25 ° C IDmaxPkg 60 A Drain4 Operating Junction and Storage Temperature TJ, Tstg −55 to ° C Drain4 Drain4 175 Source Current (Body Diode) IS 27 A Drain to Source dV/dt dV/dt 7.0 V/ns Single Pulse Drain−to−Source Avalanche EAS 28 mJ Energy (TJ = 25 ° C, VDD = 50 V, VGS = 10 V, 2 L = 0.1 mH, IL(pk) = 24 A, RG = 25 ) 1 Drain 3 1 2 3 Gate Drain Source Lead Temperature for Soldering Purposes TL 260 ° C Gate Source 1 2 3 (1/8 ″ from case for 10 s) Gate Drain Source ~~a Of~~ Stresses exceeding those listed in the Maximum Ratings table may damage the A = Assembly Location device. If any of these limits are exceeded, device functionality should not be Y = Year assumed, damage may occur and reliability may be affected. WW = Work Week 1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 4909N = Device Code 2. Surface−mounted on FR4 board using the minimum recommended pad size. G = Pb−Free Package ## **ORDERING INFORMATION** See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. Publication Order Number: **1** © Semiconductor Components Industries, LLC, 2014 **May, 2014 − Rev. 3** **NTD4909N/D** **NTD4909N** ## **THERMAL RESISTANCE MAXIMUM RATINGS** |**THERMAL RESISTANCE MAXIMUM RATINGS**|||| |---|---|---|---| |**Parameter**|**Symbol**|**Value**|**Unit**| |Junction−to−Case (Drain)|R�JC|5.1|°C/W| |Junction−to−TAB (Drain)|R�JC−TAB|4.3|| |Junction−to−Ambient − Steady State (Note 3)|R�JA|58.2|| |Junction−to−Ambient − SteadyState(Note 4)|R�JA|110|| 3. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 4. Surface−mounted on FR4 board using the minimum recommended pad size. ## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) |**ELECTRICAL CHARACTERISTICS **(TJ|= 25°C unless|otherwise noted)|otherwise noted)||||| |---|---|---|---|---|---|---|---| |**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**| |**OFF CHARACTERISTICS**|||||||| |Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID= 250�A||30|||V| |Drain−to−Source Breakdown Voltage
Temperature Coefficient|V(BR)DSS/TJ||||15||mV/°C| |Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,
VDS= 24 V|TJ= 25°C|||1.0|�A| ||||TJ= 125°C|||10|| |Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS=�20 V||||�100|nA| |**ON CHARACTERISTICS**(Note 5)|||||||| |Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 250�A||1.0|1.7|2.2|V| |Negative Threshold Temperature Coefficient|VGS(TH)/TJ||||4.0||mV/°C| |Drain−to−Source On Resistance|RDS(on)|VGS= 10 V|ID= 30 A||6.5|8.0|m�| ||||ID= 15 A||6.5||| |||VGS= 4.5 V|ID= 30 A||9.5|12|| ||||ID= 15 A||9.5||| |Forward Transconductance|gFS|VDS= 1.5 V, ID= 30 A|||52||S| |**CHARGES AND CAPACITANCES**|||||||| |Input Capacitance|Ciss|VGS= 0 V, f = 1.0 MHz,
VDS= 15 V|||1314||pF| |Output Capacitance|Coss||||487||| |Reverse Transfer Capacitance|Crss||||17.4||| |Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 15 V,
ID= 30 A|||7.6||nC| |Threshold Gate Charge|QG(TH)||||2.1||| |Gate−to−Source Charge|QGS||||4.3||| |Gate−to−Drain Charge|QGD||||1.3||| |Total Gate Charge|QG(TOT)|VGS= 10 V, VDS= 15 V,
ID= 30 A|||17.5||nC| |**SWITCHING CHARACTERISTICS**(Note 6)|||||||| |Turn−On Delay Time|td(on)|VGS= 4.5 V, VDS= 15 V,
ID= 15 A, RG= 3.0�|||11||ns| |Rise Time|tr||||21||| |Turn−Off Delay Time|td(off)||||17||| |Fall Time|tf||||2.7||| Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 6. Switching characteristics are independent of operating junction temperatures. 7. Assume terminal length of 110 mils. **http://onsemi.com** **2** ## **NTD4909N** ## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) |**ELECTRICAL CHARACTERISTICS **(TJ|= 25°C unless|otherwise noted)|otherwise noted)||||| |---|---|---|---|---|---|---|---| |**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**| |Turn−On Delay Time|td(on)|VGS= 10 V, VDS= 15 V,
ID= 15 A, RG= 3.0�|||8.0||ns| |Rise Time|tr||||19||| |Turn−Off Delay Time|td(off)||||21||| |Fall Time|tf||||2.3||| |**DRAIN−SOURCE DIODE CHARACTERISTICS**|||||||| |Forward Diode Voltage|VSD|VGS= 0 V,
IS= 30 A|TJ= 25°C||0.9|1.1|V| ||||TJ= 125°C||0.8||| |Reverse Recovery Time|tRR|VGS= 0 V, dIs/dt = 100 A/�s,
IS= 30 A|||30||ns| |Charge Time|ta||||16||| |Discharge Time|tb||||14||| |Reverse Recovery Time|QRR||||20||nC| |**PACKAGE PARASITIC VALUES**|||||||| |Source Inductance (Note 7)|LS|TA= 25°C|||2.99||nH| |Drain Inductance, DPAK|LD||||0.0164||| |Drain Inductance, IPAK (Note 7)|LD||||1.88||| |Gate Inductance (Note 7)|LG||||4.9||| |Gate Resistance|RG||||1.0|2.0|�| Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 6. Switching characteristics are independent of operating junction temperatures. 7. Assume terminal length of 110 mils. ## **ORDERING INFORMATION** |**ORDERING INFORMATION**||| |---|---|---| |**Order Number**|**Package**|**Shipping**†| |NTD4909NT4G|DPAK
(Pb−Free)|2500 / Tape & Reel| |NTD4909N−1G|IPAK
(Pb−Free)|75 Units / Rail| |NTD4909N−35G|IPAK Trimmed Lead
(Pb−Free)|75 Units / Rail| - †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. **http://onsemi.com** **3** **NTD4909N** ## **TYPICAL CHARACTERISTICS** **==> picture [490 x 618] intentionally omitted <==** **----- Start of picture text -----**
90 80
10 V 7 V 4.5 V 4.2 V VGS = 4.0 V TJ = 25 ° C
80 VDS = 10 V
3.8 V
70
60
3.6 V
60
50 3.4 V
40
40 3.2 V
TJ = 25 ° C
30 3.0 V
20 2.8 V 20 T J = 125 ° C
10 2.6 V
2.4 V TJ = −55 ° C
0 0
0 1 2 3 4 2.0 2.5 3.0 3.5 4.0 4.5
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
0.020 0.014
0.018 TID J = 30 A= 25 ° C 0.013 TJ = 25 ° C
0.012
0.016
0.011
0.014
0.010 VGS = 4.5 V
0.012 0.009
0.010 0.008
0.007 VGS = 10 V
0.008
0.006
0.006
0.005
0.004 0.004
3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 15 25 35 45 55 65 75 85 95
VGS (V) ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. VGS Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10,000
2.0 VGS = 0 V
I D = 30 A
1.8 V GS = 10 V TJ = 150 ° C
1.6 1000
1.4 TJ = 125 ° C
1.2
100
1.0 TJ = 85 ° C
0.8
0.6 10
−50 −25 0 25 50 75 100 125 150 175 5 10 15 20 25 30
TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current
Temperature vs. Voltage
, DRAIN CURRENT (A) , DRAIN CURRENT (A)
ID ID
)
� )
, DRAIN−TO−SOURCE RESISTANCE ( �
, DRAIN−TO−SOURCE RESISTANCE (
DS(on)
R DS(on)
R
, LEAKAGE (nA)
, DRAIN−TO−SOURCE RES- IDSS
ISTANCE (NORMALIZED)
DS(on)
R
**----- End of picture text -----**
**http://onsemi.com** **4** **NTD4909N** ## **TYPICAL CHARACTERISTICS** **==> picture [490 x 172] intentionally omitted <==** **----- Start of picture text -----**
2000 15.0
VGS = 0 V 13.5 T J = 25 ° C
TJ = 25 ° C 12.0 QT
1500
Ciss 10.5
9.0
1000 7.5
Qgd
6.0
500 Coss 4.5 Qgs VDD = 15 V
3.0 V GS = 10 V
1.5 I D = 30 A
0 Crss 0
0 5 10 15 20 25 30 0 2 4 6 8 10 12 14 16 18 20
VDS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)
C, CAPACITANCE (pF)
, GATE−TO−SOURCE VOLTAGE (V)
GS
V
**----- End of picture text -----**
**Figure 7. Capacitance Variation** **Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge** **==> picture [491 x 382] intentionally omitted <==** **----- Start of picture text -----**
1000 30
VDD = 15 V VGS = 0 V
ID = 15 A 25
VGS = 10 V
td(off)
100 20
tf
tr 15
TJ = 125 ° C
10 td(on) 10
5
TJ = 25 ° C
1 0
1 10 100 0 0.2 0.4 0.6 0.8 1.0
RG, GATE RESISTANCE ( � ) VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage vs. Current
vs. Gate Resistance
1000 30
ID = 24 A
25
100
20
10 � s
10 100 � s 15
VGS = 10 V 1 ms
Single Pulse 10 ms 10
1 TC = 25 ° C dc
RDS(on) Limit 5
Thermal Limit
Package Limit
0.1 0
0.1 1 10 100 25 50 75 100 125 150 175
VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ, STARTING JUNCTION TEMPERATURE ( ° C)
t, TIME (ns)
, SOURCE CURRENT (A)
IS
, DRAIN CURRENT (A)
ID , SINGLE PULSE DRAIN−TO−
AS
E
SOURCE AVALANCHE ENERGY (mJ)
**----- End of picture text -----**
**Figure 11. Maximum Rated Forward Biased Safe Operating Area** **Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature** **http://onsemi.com** **5** **NTD4909N** ## **TYPICAL CHARACTERISTICS** **==> picture [491 x 173] intentionally omitted <==** **----- Start of picture text -----**
100
Duty Cycle = 50%
20%
10 10%
5%
2%
1
1%
0.1
Single Pulse
0.01
Psi Tab−A
0.001
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
PULSE TIME (sec)
C/W)
°
R(t) (
**----- End of picture text -----**
**Figure 13. FET Thermal Response** **==> picture [243 x 173] intentionally omitted <==** **----- Start of picture text -----**
60
50
40
30
20
10
0
0 5 10 15 20 25 30 35 40 45 50
ID (A)
GFS (S)
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**Figure 14. GFS vs. ID** **http://onsemi.com** **6** **NTD4909N** ## **PACKAGE DIMENSIONS** ## **3.5 MM IPAK, STRAIGHT LEAD** CASE 369AD ISSUE B **==> picture [474 x 224] intentionally omitted <==** **----- Start of picture text -----**
NOTES:
E A 1.. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
L2 E3 A1 E2 2.. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM TERMINAL TIP.
D2 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD GATE OR MOLD FLASH.
D
L1 MILLIMETERS
DIM MIN MAX
A 2.19 2.38
L A1 0.46 0.60
T A2 0.87 1.10
SEATING b 0.69 0.89
PLANE b1 A1 b1 0.77 1.10
D 5.97 6.22
2X e A2 D2 4.80 −−−
E2 E 6.35 6.73
3X b E2 4.57 5.45
0.13 M T E3 4.45 5.46
e 2.28 BSC
D2 L 3.40 3.60
L1 −−− 2.10
L2 0.89 1.27
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
OPTIONAL 4. DRAIN
CONSTRUCTION
**----- End of picture text -----**
**IPAK** CASE 369D ISSUE C **==> picture [432 x 195] intentionally omitted <==** **----- Start of picture text -----**
||||||||| |---|---|---|---|---|---|---|---| |B|C|NOTES:| |1.|DIMENSIONING AND TOLERANCING PER| |V|R|E|ANSI Y14.5M, 1982.| |2.|CONTROLLING DIMENSION: INCH.| |INCHES|MILLIMETERS| |4|Z|DIM|MIN|MAX|MIN|MAX| |A|0.235|0.245|5.97|6.35| |S|A|B|0.250|0.265|6.35|6.73| |1|2|3|C|0.086|0.094|2.19|2.38| |D|0.027|0.035|0.69|0.88| |E|0.018|0.023|0.46|0.58| |−T−|F|0.037|0.045|0.94|1.14| |SEATING|G|0.090 BSC|2.29 BSC| |PLANE|K|H|0.034|0.040|0.87|1.01| |J|0.018|0.023|0.46|0.58| |K|0.350|0.380|8.89|9.65| |R|0.180|0.215|4.45|5.45| |J|S|0.025|0.040|0.63|1.01| |F| |H|V|0.035|0.050|0.89|1.27| |Z|0.155|−−−|3.93|−−−| |D|3 PL| |G|0.13 (0.005)|M|T|STYLE 2:PIN 1.|GATE| |2.|DRAIN| |3.|SOURCE| |4.|DRAIN| **----- End of picture text -----**
**http://onsemi.com** **7** **NTD4909N** ## **PACKAGE DIMENSIONS** **DPAK (SINGLE GUAGE)** CASE 369AA **==> picture [37 x 8] intentionally omitted <==** **----- Start of picture text -----**
ISSUE B
**----- End of picture text -----**
**==> picture [467 x 415] intentionally omitted <==** **----- Start of picture text -----**
NOTES:
C 1. DIMENSIONING AND TOLERANCING PER ASME
A Y14.5M, 1994.
E A 2.3. CONTROLLING DIMENSION: INCHES.THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
b3 B c2 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
L3 4 Z 5. DIMENSIONS D AND E ARE DETERMINED AT THEOUTERMOST EXTREMES OF THE PLASTIC BODY.
1 2 3 D DETAIL A H 6. DATUMS A AND B ARE DETERMINED AT DATUMPLANE H.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
L4 A 0.086 0.094 2.18 2.38
Ht b2 ie A1 0.000 0.005 0.00 0.13
b c b 0.025 0.035 0.63 0.89
b2 0.030 0.045 0.76 1.14
e 0.005 (0.13) M C H b3 0.180 0.215 4.57 5.46
c 0.018 0.024 0.46 0.61
L2 [GAUGE] PLANE a C SEATINGPLANE _———— c2D 0.0180.235 0.0240.245 0.465.97 0.616.22
E 0.250 0.265 6.35 6.73
e 0.090 BSC 2.29 BSC
H 0.370 0.410 9.40 10.41
L A1 L 0.055 0.070 1.40 1.78
ow L1 as Weel=s== L1 0.108 REF 2.74 REF
L2 0.020 BSC 0.51 BSC
DETAIL A L3 0.035 0.050 0.89 1.27
ROTATED 9 CW L4 −−− 0.040 −−− 1.01
Z 0.155 −−− 3.93 −−−
STYLE 2:
SOLDERING FOOTPRINT* PIN 1. GATE
2. DRAIN
6.20 3.00 3.4. SOURCEDRAIN
0.244 0.118
2.58
PTET,
0.102
eae
5.80
1.60 6.17
0.228
0.063 0.243
LIS
SCALE 3:1 mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
**----- End of picture text -----**
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