# Power MOSFET, N Channel, 25 V, 73 A, 6200 µohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:2845374/)

**URL**: https://novapart.co/products/NTD4858NT4G./power-mosfet-n-channel-25-v-73-a-6200-ohm-to-252
**SKU**: NTD4858NT4G.
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.3110
**Stock**: 500+
**Lead Time**: 2 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:73A; Drain Source Voltage Vds:25V; On Resistance Rds(on):0.0062ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:2.5V; Pow

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (15-Jan-2018) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 54.5W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 25V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 73A |
| Drain Source On State Resistance | 6200µohm |
| Gate Source Threshold Voltage Max | 2.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2845374/)

NTD4858N 

## Power MOSFET **25 V, 73 A, Single N−Channel, DPAK/IPAK** 

## **Features** 

- Trench Technology 

- Low R to Minimize Conduction Losses DS(on) 

## **http://onsemi.com** 

- Low Capacitance to Minimize Driver Losses 

- Optimized Gate Charge to Minimize Switching Losses 

**==> picture [162 x 31] intentionally omitted <==**

**----- Start of picture text -----**<br>
V(BR)DSS RDS(ON) MAX ID MAX<br>6.2 m  @ 10 V<br>25 V 73 A<br>**----- End of picture text -----**<br>


- These are Pb−Free Devices 

25 V 9.3 m @ 4.5 V 

## **Applications** 

- VCORE Applications 

**==> picture [494 x 421] intentionally omitted <==**

**----- Start of picture text -----**<br>
D<br>• DC−DC Converters<br>• High/Low Side Switching<br>N−CHANNEL MOSFET<br>MAXIMUM RATINGS  (TJ = 25 ° C unless otherwise stated) G<br>Parameter Symbol Value Unit<br>S<br>Drain−to−Source Voltage VDSS 25 V<br>SS Gate−to−Source Voltage VGS ± 20 — V & 4 4<br>Continuous Drain TA = 25 ° C ID 14 A<br>Current R(Note 1) JA TA = 85 ° C 10.9 4<br>Power Dissipation TA = 25 ° C PD 2.0 W 1 [2] 1 1<br>R JA (Note 1) 3 2 3 2 3<br>Continuous Drain TA = 25 ° C ID 11.2 A DPAK IPAK IPAK<br>Current R(Note 2) JA Steady TA = 85 ° C 8.7 CASE 369AA(Bent Lead) (Straight Lead)CASE 369AD (Straight LeadCASE 369D<br>Power Dissipation State TA = 25 ° C PD 1.3 W STYLE 2 STYLE 2 DPAK) STYLE 2<br>R JA (Note 2)<br>===<br>Continuous Drain TC = 25 ° C ID 73 A MARKING DIAGRAMS<br>Current R(Note 1) JC TC = 85 ° C 56 & PIN ASSIGNMENTS 4<br>Drain<br>Power DissipationR JC (Note 1) TC = 25 ° C PD 54.5 W Drain4 Drain4<br>= ———=—EEE oe<br>Pulsed Drain tp=10 s TA = 25 ° C IDM 146 A<br>Current<br>Current Limited by Package TA = 25 ° C IDmaxPkg 45 A<br>Operating Junction and Storage TJ, −55 to ° C<br>Temperature TSTG +175 2<br>Source Current (Body Diode) IS 45 A Gate1 DrainSource3 Gate1 Drain2 3Source 1 2 3<br>Drain to Source dV/dt dV/dt 6 V/ns<br>Gate Drain Source<br>Single Pulse Drain−to−Source Avalanche EAS 112.5 mJ<br>Energy (TJ = 25 ° C, VDD = 50 V, VGS = 10 V, A = Assembly Location*<br>IL = 15 Apk, L = 1.0 mH, RG = 25  Y = Year<br>Lead Temperature for Soldering Purposes TL 260 ° C WW = Work Week<br>4858N = Device Code<br>—saa (1/8” from case for 10 s) G = Pb−Free Package<br>Stresses exceeding those listed in the Maximum Ratings table may damage the<br>device. If any of these limits are exceeded, device functionality should not be * The Assembly Location code (A) is front side<br>assumed, damage may occur and reliability may be affected.<br>48<br>AYWW 58NG<br>48 48<br>AYWW 58NG AYWW 58NG<br>**----- End of picture text -----**<br>


* The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. 

Publication Order Number: **NTD4858N/D** 

**1** 

© Semiconductor Components Industries, LLC, 2014 **June, 2014 − Rev. 3** 

**NTD4858N** 

## **THERMAL RESISTANCE MAXIMUM RATINGS** 

|**THERMAL RESISTANCE MAXIMUM RATINGS**||||
|---|---|---|---|
|**Parameter**|**Symbol**|**Value**|**Unit**|
|Junction−to−Case (Drain)|R�JC|2.75|°C/W|
|Junction−to−TAB (Drain)|R�JC−TAB|3.5||
|Junction−to−Ambient – Steady State (Note 1)|R�JA|73.5||
|Junction−to−Ambient – Steady State (Note 2)|R�JA|116||



1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu. 

2. Surface−mounted on FR4 board using the minimum recommended pad size. 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) 

|**ELECTRICAL CHARACTERISTICS**(TJ|= 25°C unless|otherwise specified)|otherwise specified)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|25|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/<br>TJ||||22||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 20 V|TJ= 25°C|||1.0|�A|
||||TJ= 125°C|||10||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS|=±20 V|||±100|nA|
|**ON CHARACTERISTICS**(Note 3)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID=|250�A|1.45||2.5|V|
|Negative Threshold Temperature<br>Coefficient|VGS(TH)/TJ||||5.3||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 10 V|ID= 30 A||5.2|6.2|m�|
|||VGS= 4.5 V|ID= 30 A||7.3|9.3||
|Forward Transconductance|gFS|VDS= 1.5 V, ID= 15 A|||55||S|
|**CHARGES AND CAPACITANCES**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1.0 MHz, VDS= 12 V|||1563||pF|
|Output Capacitance|COSS||||405|||
|Reverse Transfer Capacitance|CRSS||||200|||
|Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 15 V, ID= 30 A|||12.8|19.2|nC|
|Threshold Gate Charge|QG(TH)||||1.3|||
|Gate−to−Source Charge|QGS||||4.7|||
|Gate−to−Drain Charge|QGD||||5.2|||
|Total Gate Charge|QG(TOT)|VGS= 10 V, VDS= 15 V, ID= 30 A|||25.7||nC|
|**SWITCHING CHARACTERISTICS**(Note 4)||||||||
|Turn−On Delay Time|td(ON)|VGS= 4.5 V, VDS= 15 V,<br>ID= 15 A, RG= 3.0�|||12.6||ns|
|Rise Time|tr||||20.2|||
|Turn−Off Delay Time|td(OFF)||||16.4|||
|Fall Time|tf||||5.1|||



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

3. Pulse Test: pulse width � 300 � s, duty cycle � 2%. 

4. Switching characteristics are independent of operating junction temperatures. 

**http://onsemi.com 2** 

**NTD4858N** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) (continued) 

|**ELECTRICAL CHARACTERISTICS**(TJ|= 25°C unless|otherwise specified) (continued)|otherwise specified) (continued)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**SWITCHING CHARACTERISTICS**(Note 4)||||||||
|Turn−On Delay Time|td(ON)|VGS= 11.5 V, VDS= 15 V,<br>ID= 15 A, RG= 3.0�|||7.7||ns|
|Rise Time|tr||||17.3|||
|Turn−Off Delay Time|td(OFF)||||23.8|||
|Fall Time|tf||||2.8|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 30 A|TJ= 25°C||0.87|1.2|V|
||||TJ= 125°C||0.73|||
|Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt = 100 A/�s,<br>IS= 30 A|||11.6||ns|
|Charge Time|ta||||7.8|||
|Discharge Time|tb||||3.7|||
|Reverse Recovery Charge|QRR||||3.0||nC|
|**PACKAGE PARASITIC VALUES**||||||||
|Source Inductance|LS|TA= 25°C|||2.49||nH|
|Drain Inductance, DPAK|LD||||0.0164|||
|Drain Inductance, IPAK|LD||||1.88|||
|Gate Inductance|LG||||3.46|||
|Gate Resistance|RG||||0.7||�|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

3. Pulse Test: pulse width � 300 � s, duty cycle � 2%. 

4. Switching characteristics are independent of operating junction temperatures. 

**http://onsemi.com** 

**3** 

**NTD4858N** 

## **TYPICAL PERFORMANCE CURVES** 

**==> picture [489 x 633] intentionally omitted <==**

**----- Start of picture text -----**<br>
90 90<br>10 V 3.8 V TJ = 25 ° C VDS ≥  10 V<br>80 80<br>4 V<br>70 3.6 V 70<br>60 60<br>3.4 V<br>50 50<br>40 40<br>3.2 V<br>30 30<br>TJ = 125 ° C<br>20 3.0 V 20<br>TJ = 25 ° C<br>10 2.8 V 10<br>TJ = −55 ° C<br>0 0<br>0 1 2 3 4 5 1 2 3 4 5<br>VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>0.040 0.010<br>0.035 TIDJ = 30 A = 25 ° C 0.009 TJ = 25 ° C<br>0.030 0.008 VGS = 4.5 V<br>0.025 0.007<br>0.020 0.006<br>VGS = 11.5 V<br>0.015 0.005<br>0.010 0.004<br>0.005 0.003<br>0 0.002<br>2 3 4 5 6 7 8 9 10 11 10 20 30 40 50 60 70 80 90<br>VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>1.8 10000<br>ID = 30 A VGS = 0 V<br>1.6 VGS = 10 V 1000 TJ = 150 ° C<br>1.4 TJ = 125 ° C<br>100<br>1.2<br>10<br>1.0<br>0.8 1 TJ = 25 ° C<br>0.6 0.1<br>−50 −25 0 25 50 75 100 125 150 175 5 10 15 20 25<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current<br>Temperature vs. Drain Voltage<br>, DRAIN CURRENT (AMPS) , DRAIN CURRENT (AMPS)<br>ID ID<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (nA)<br>(NORMALIZED) IDSS<br>, DRAIN−TO−SOURCE RESISTANCE<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


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**4** 

**NTD4858N** 

## **TYPICAL PERFORMANCE CURVES** 

**==> picture [491 x 606] intentionally omitted <==**

**----- Start of picture text -----**<br>
2000 10<br>1800 Ciss VTGSJ = 25 = 0 V ° C Q T<br>1600 8<br>1400<br>1200 6 VGS<br>1000<br>800 Coss 4 Q1 Q2<br>600<br>400 2 ID = 30 A<br>200 C rss VTJDD = 25 = 15 V ° C<br>0 0<br>0 2.5 5 7.5 10 12.5 15 17.5 20 0 4 8 12 16 20 24 28<br>DRAIN−TO−SOURCE VOLTAGE (VOLTS) QG, TOTAL GATE CHARGE (nC)<br>Figure 7. Capacitance Variation Figure 8. Gate−To−Source and Drain−To−Source<br>Voltage vs. Total Charge<br>1000 30<br>V DD  = 15 V VGS = 0 V<br>I D  = 30 A 25 TJ = 25 ° C<br>VGS = 11.5 V<br>td(off)<br>100 tf 20<br>tr<br>15<br>10 td(on) 10<br>5<br>1 0<br>1 10 100 0.5 0.6 0.7 0.8 0.9<br>RG, GATE RESISTANCE (OHMS) VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)<br>Figure 9. Resistive Switching Time Figure 10. Diode Forward Voltage vs. Current<br>Variation vs. Gate Resistance<br>1000 120<br>ID = 15 A<br>100<br>100<br>10  � s<br>80<br>100  � s<br>10 60<br>1 ms<br>VGS = 20 V<br>SINGLE PULSE 10 ms<br>1 TC = 25 ° C dc 40<br>RDS(on) LIMIT<br>20<br>THERMAL LIMIT<br>PACKAGE LIMIT<br>0.1 0<br>0.1 1 10 100 25 50 75 100 125 150 175<br>VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE ( ° C)<br>C, CAPACITANCE (pF)<br>VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)<br>t, TIME (ns)<br>IS, SOURCE CURRENT (AMPS)<br>ID, DRAIN CURRENT (AMPS)<br>AVALANCHE ENERGY (mJ)<br>EAS, SINGLE PULSE DRAIN−TO−SOURCE<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

**Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature** 

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**5** 

**NTD4858N** 

## **TYPICAL PERFORMANCE CURVES** 

**==> picture [479 x 198] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.0<br>D = 0.5<br>0.2<br>0.1<br>0.1 0.05 P(pk)<br>0.02 R � JC(t) = r(t) R � JC<br>D CURVES APPLY FOR POWER<br>PULSE TRAIN SHOWN<br>0.01<br>SINGLE PULSE t1 READ TIME AT t1<br>t2 TJ(pk) − TC = P(pk) R � JC(t)<br>DUTY CYCLE, D = t1/t2<br>0.01<br>1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01<br>t, TIME ( � s)<br>(NORMALIZED)<br>r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE<br>**----- End of picture text -----**<br>


**Figure 13. Thermal Response** 

## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**|||
|---|---|---|
|**Device**|**Package**|**Shipping**†|
|NTD4858NT4G|DPAK<br>(Pb−Free)|2500 / Tape & Reel|
|NTD4858N−1G|IPAK<br>(Pb−Free)|75 Units / Rail|
|NTD4858N−35G|IPAK Trimmed Lead<br>(3.5±0.15 mm)<br>(Pb−Free)|75 Units / Rail|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

**http://onsemi.com** 

**6** 

**NTD4858N** 

## **PACKAGE DIMENSIONS** 

**==> picture [467 x 413] intentionally omitted <==**

**----- Start of picture text -----**<br>
DPAK (SINGLE GUAGE)<br>CASE 369AA<br>ISSUE B<br>NOTES:<br>C 1. DIMENSIONING AND TOLERANCING PER ASME<br>A Y14.5M, 1994.<br>E A 2.3. CONTROLLING DIMENSION: INCHES.THERMAL PAD CONTOUR OPTIONAL WITHIN DI-<br>MENSIONS b3, L3 and Z.<br>b3 B c2 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD<br>FLASH, PROTRUSIONS, OR BURRS. MOLD<br>FLASH, PROTRUSIONS, OR GATE BURRS SHALL<br>NOT EXCEED 0.006 INCHES PER SIDE.<br>L3 4 Z 5. DIMENSIONS D AND E ARE DETERMINED AT THEOUTERMOST EXTREMES OF THE PLASTIC BODY.<br>1 2 3 D DETAIL A H 6. DATUMS A AND B ARE DETERMINED AT DATUMPLANE H.<br>INCHES MILLIMETERS<br>DIM MIN MAX MIN MAX<br>L4 A 0.086 0.094 2.18 2.38<br>b2 A1 0.000 0.005 0.00 0.13<br>b c b 0.025 0.035 0.63 0.89<br>b2 0.030 0.045 0.76 1.14<br>e 0.005 (0.13) M C H b3 0.180 0.215 4.57 5.46<br>c 0.018 0.024 0.46 0.61<br>L2 [GAUGE] PLANE C SEATINGPLANE c2D 0.0180.235 0.0240.245 0.465.97 0.616.22<br>E 0.250 0.265 6.35 6.73<br>e 0.090 BSC 2.29 BSC<br>H 0.370 0.410 9.40 10.41<br>L A1 L 0.055 0.070 1.40 1.78<br>L1 L1 0.108 REF 2.74 REF<br>L2 0.020 BSC 0.51 BSC<br>DETAIL A L3 0.035 0.050 0.89 1.27<br>ROTATED 90  CW � L4 −−− 0.040 −−− 1.01<br>Z 0.155 −−− 3.93 −−−<br>STYLE 2:<br>SOLDERING FOOTPRINT* PIN 1. GATE<br>2. DRAIN<br>6.20 3.00 3.4. SOURCEDRAIN<br>0.244 0.118<br>2.58<br>0.102<br>5.80<br>1.60 6.17<br>0.228<br>0.063 0.243<br>SCALE 3:1<br>� inches [mm] �<br>**----- End of picture text -----**<br>


*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

**http://onsemi.com** 

**7** 

**NTD4858N** 

## **PACKAGE DIMENSIONS** 

**3.5 MM IPAK, STRAIGHT LEAD** CASE 369AD ISSUE B 

**==> picture [474 x 221] intentionally omitted <==**

**----- Start of picture text -----**<br>
NOTES:<br>E A 1.. DIMENSIONING AND TOLERANCING PER<br>ASME Y14.5M, 1994.<br>L2 E3 A1 E2 2.. CONTROLLING DIMENSION: MILLIMETERS.<br>3. DIMENSION b APPLIES TO PLATED TERMINAL<br>AND IS MEASURED BETWEEN 0.15 AND<br>0.30mm FROM TERMINAL TIP.<br>D2 4. DIMENSIONS D AND E DO NOT INCLUDE<br>MOLD GATE OR MOLD FLASH.<br>D<br>L1 MILLIMETERS<br>DIM MIN MAX<br>A 2.19 2.38<br>L A1 0.46 0.60<br>T A2 0.87 1.10<br>SEATING b 0.69 0.89<br>PLANE b1 A1 b1 0.77 1.10<br>E2 D 5.97 6.22<br>2X e A2 D2 4.80 −−−<br>E 6.35 6.73<br>3X b E2 4.57 5.45<br>0.13 M T D2 E3 4.45 5.46<br>e 2.28 BSC<br>L 3.40 3.60<br>L1 −−− 2.10<br>L2 0.89 1.27<br>STYLE 2:<br>PIN 1. GATE<br>OPTIONAL<br>CONSTRUCTION 2. DRAIN<br>3. SOURCE<br>4. DRAIN<br>**----- End of picture text -----**<br>


**http://onsemi.com** 

**8** 

**NTD4858N** 

## **PACKAGE DIMENSIONS** 

**IPAK** CASE 369D ISSUE C 

**==> picture [432 x 196] intentionally omitted <==**

**----- Start of picture text -----**<br>
B C NOTES:<br>1. DIMENSIONING AND TOLERANCING PER<br>V R E ANSI Y14.5M, 1982.<br>2. CONTROLLING DIMENSION: INCH.<br>INCHES MILLIMETERS<br>4 Z DIM MIN MAX MIN MAX<br>A 0.235 0.245 5.97 6.35<br>ae A eee B 0.250 0.265 6.35 6.73<br>S<br>1 2 3 C 0.086 0.094 2.19 2.38<br>D 0.027 0.035 0.69 0.88<br>E 0.018 0.023 0.46 0.58<br>−T− F 0.037 0.045 0.94 1.14<br>SEATING G 0.090 BSC 2.29 BSC<br>PLANE K H 0.034 0.040 0.87 1.01<br>J 0.018 0.023 0.46 0.58<br>K 0.350 0.380 8.89 9.65<br>R 0.180 0.215 4.45 5.45<br>J S 0.025 0.040 0.63 1.01<br>F<br>H V 0.035 0.050 0.89 1.27<br>Z 0.155 −−− 3.93 −−−<br>D 3 PL<br>G 0.13 (0.005) M T STYLE 2:<br>PIN 1. GATE<br>2. DRAIN<br>3. SOURCE<br>4. DRAIN<br>**----- End of picture text -----**<br>


**ON Semiconductor** and          are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).  SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf.  SCILLC reserves the right to make changes without further notice to any products herein.  SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.  All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.  SCILLC does not convey any license under its patent rights nor the rights of others.  SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.  Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.  SCILLC is an Equal Opportunity/Affirmative Action Employer.  This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **PUBLICATION ORDERING INFORMATION** 

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**NTD4858N/D** 

**9** 



## Links

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---

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