# Power MOSFET, N Channel, 30 V, 19.6 A, 0.0034 ohm, TO-252 (DPAK), Surface Mount ![Product image](https://novapart.co/image/farnell:2533184/) **URL**: https://novapart.co/products/NTD4804NT4G/power-mosfet-n-channel-30-v-196-a-00034-ohm-to-252 **SKU**: NTD4804NT4G **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €1.2200 **Stock**: 10+ ## Specifications | Parameter | Value | |---|---| | No. Of Pins | 3Pins | | Channel Type | N Channel | | Power Dissipation | 1.43W | | Transistor Mounting | Surface Mount | | Transistor Polarity | N Channel | | Power Dissipation Pd | 1.43W | | Rds(On) Test Voltage | 10V | | On Resistance Rds(On) | 0.0034ohm | | Transistor Case Style | TO-252 (DPAK) | | Drain Source Voltage Vds | 30V | | Operating Temperature Max | 175°C | | Continuous Drain Current Id | 19.6A | | Drain Source On State Resistance | 0.0034ohm | | Gate Source Threshold Voltage Max | 2.5V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2533184/) ## NTD4804N, NVD4804N ## Power MOSFET **30 V, 117 A, Single N−Channel, DPAK/IPAK** ## **Features** - Low R to Minimize Conduction Losses DS(on) - Low Capacitance to Minimize Driver Losses - Optimized Gate Charge to Minimize Switching Losses ## **www.onsemi.com** - AEC Q101 Qualified − NVD4804N - These Devices are Pb−Free and are RoHS Compliant ## **Applications** **==> picture [165 x 38] intentionally omitted <==** **----- Start of picture text -----**
V(BR)DSS RDS(on) MAX ID MAX
4.0 m @ 10 V
30 V 117 A
5.5 m @ 4.5 V
**----- End of picture text -----**
- CPU Power Delivery - DC−DC Converters **==> picture [493 x 423] intentionally omitted <==** **----- Start of picture text -----**
DC−DC Converters D
• Low Side Switching
MAXIMUM RATINGS (TJ = 25 ° C unless otherwise noted) G N−Channel
Parameter Symbol Value Unit
Drain−to−Source Voltage VDSS 30 V S
Gate−to−Source Voltage VGS 20 V
———-, -#
Continuous Drain TA = 25 ° C ID 19.6 A 4
Current (R JA) (Note 1) TA = 85 ° C 15.2 4
Power Dissipation TA = 25 ° C PD 2.66 W
(R JA) (Note 1) 1 [2] 1
Continuous Drain TA = 25 ° C ID 14.5 A 3 2 3
ae Current (R JA) (Note 2) Steady TA = 85 ° C 11 CASE 369AA CASE 369AD CASE 369D
Power Dissipation State TA = 25 ° C PD 1.43 W DPAK 3 IPAK IPAK
(R JA) (Note 2) (Bent Lead) (Straight Lead) (Straight Lead
Continuous Drain TC = 25 ° C ID 124 A STYLE 2 DPAK)
(Note 1)Current (R JC) TC = 85 ° C 96 MARKING DIAGRAMS
& PIN ASSIGNMENTS
Power Dissipation TC = 25 ° C PD 107 W 4
(R JC) (Note 1) 4 Drain4 Drain
Pulsed Drain Current tp=10 s TA = 25 ° C IDM 230 A Drain
Current Limited by Package TA = 25 ° C IDmaxPkg 45 A
Operating Junction and Storage Temperature TJ, Tstg −55 to ° C
175
Source Current (Body Diode) IS 78 A
2
Drain to Source dV/dt dV/dt 6.0 V/ns 1 Drain 3 1 2 3
a O e
Single Pulse Drain−to−Source Avalanche EAS 450 mJ Gate Source Gate Drain SourceGate1 Drain2 3Source
Energy (VDD = 24 V, VGS = 10 V,
L = 1.0 mH, IL(pk) = 30 A, RG = 25 ) A = Assembly Location
Y = Year
tt Lead Temperature for Soldering Purposes(1/8 ″ from case for 10 s) TL 260 ° C WW4804N = Device Code= Work Week
Stresses exceeding those listed in the Maximum Ratings table may damage the G = Pb−Free Package
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
AYWW 48 04NG
AYWW 48 04NG AYWW 48 04NG
**----- End of picture text -----**
## **ORDERING INFORMATION** See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Publication Order Number: **1** © Semiconductor Components Industries, LLC, 2016 **November, 2016 − Rev. 10** **NTD4804N/D** **NTD4804N, NVD4804N** ## **THERMAL RESISTANCE MAXIMUM RATINGS** |**THERMAL RESISTANCE MAXIMUM RATINGS**|||| |---|---|---|---| |**Parameter**|**Symbol**|**Value**|**Unit**| |Junction−to−Case (Drain)|R�JC|1.4|°C/W| |Junction−to−TAB (Drain)|R�JC−TAB|3.5|| |Junction−to−Ambient − Steady State (Note 1)|R�JA|56.4|| |Junction−to−Ambient − SteadyState(Note 2)|R�JA|105|| 1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) |**ELECTRICAL CHARACTERISTIC**|**S **(TJ= 25°C un|less otherwise noted)|less otherwise noted)||||| |---|---|---|---|---|---|---|---| |**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**| |**OFF CHARACTERISTICS**|||||||| |Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|30|||V| |Drain−to−Source Breakdown Voltage
Temperature Coefficient|V(BR)DSS/TJ||||26||mV/°C| |Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,
VDS= 24 V|TJ= 25°C|||1.0|�A| ||||TJ= 125°C|||10|| |Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS|=�20 V|||�100|nA| |**ON CHARACTERISTICS**(Note 3)|||||||| |Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID|= 250�A|1.5||2.5|V| |Negative Threshold Temperature
Coefficient|VGS(TH)/TJ||||7.6||mV/°C| |Drain−to−Source On Resistance|RDS(on)|VGS= 10 to 11.5 V|ID= 30 A||3.4|4.0|m�| ||||ID= 15 A||3.4||| |||VGS= 4.5 V|ID= 30 A||4.7|5.5|| ||||ID= 15 A||4.6||| |Forward Transconductance|gFS|VDS= 15 V, ID= 15 A|||23||S| |**CHARGES AND CAPACITANCES**|||||||| |Input Capacitance|Ciss|VGS= 0 V, f = 1.0 MHz,
VDS= 12 V|||4490||pF| |Output Capacitance|Coss||||952||| |Reverse Transfer Capacitance|Crss||||556||| |Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 15 V,
ID= 30 A|||30|40|nC| |Threshold Gate Charge|QG(TH)||||5.5||| |Gate−to−Source Charge|QGS||||13||| |Gate−to−Drain Charge|QGD||||13||| |Total Gate Charge|QG(TOT)|VGS= 11.5 V, VDS= 15 V,
ID= 30 A|||73||nC| |**SWITCHING CHARACTERISTICS**(Note 4)|||||||| |Turn−On Delay Time|td(on)|VGS= 4.5 V, VDS= 15 V,
ID= 15 A, RG= 3.0�|||18||ns| |Rise Time|tr||||20||| |Turn−Off Delay Time|td(off)||||24||| |Fall Time|tf||||8||| |Turn−On Delay Time|td(on)|VGS= 11.5 V, VDS= 15 V,
ID= 15 A, RG= 3.0�|||10||ns| |Rise Time|tr||||19||| |Turn−Off Delay Time|td(off)||||35||| |Fall Time|tf||||5||| 3. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. **www.onsemi.com** **2** ## **NTD4804N, NVD4804N** **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) |**ELECTRICAL CHARACTERISTICS **(TJ|= 25°C unless|otherwise noted)|otherwise noted)||||| |---|---|---|---|---|---|---|---| |**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**| |**DRAIN−SOURCE DIODE CHARACTERISTICS**|||||||| |Forward Diode Voltage|VSD|VGS= 0 V,
IS= 30 A|TJ= 25°C||0.81|1.2|V| ||||TJ= 125°C||0.72||| |Reverse Recovery Time|tRR|VGS= 0 V, dIs/dt = 100 A/�s,
IS= 30 A|||34||ns| |Charge Time|ta||||19||| |Discharge Time|tb||||15||| |Reverse Recovery Time|QRR||||30||nC| |**PACKAGE PARASITIC VALUES**|||||||| |Source Inductance|LS|TA= 25°C|||2.49||nH| |Drain Inductance, DPAK|LD||||0.0164||| |Drain Inductance, IPAK|LD||||1.88||| |Gate Inductance|LG||||3.46||| |Gate Resistance|RG||||0.6||�| Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. **www.onsemi.com** **3** **NTD4804N, NVD4804N** ## **TYPICAL PERFORMANCE CURVES** **==> picture [487 x 632] intentionally omitted <==** **----- Start of picture text -----**
240 240
10 V T J = 25 ° C V DS ≥ 10 V
6 V
200 4.5 V 200
160 160
120 4 V 120
80 3.6 V 80 TJ = 125 ° C
40 40 TJ = 25 ° C
3.2 V
TJ = −55 ° C
0 0
0 1 2 3 4 5 0 1 2 3 4 5 6 7
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
0.010 0.01
ID = 30 A TJ = 25 ° C
0.009 TJ = 25 ° C
0.0075
0.008
VGS = 4.5 V
0.007
0.005
0.006
VGS = 11.5 V
0.005
0.0025
0.004
0.003 0
2 4 6 8 10 10 20 30 40 50 60 70 80 90 100
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and
Voltage Gate Voltage
1.7 100,000
1.6 I D = 30 A VGS = 0 V
VGS = 10 V
1.5 TJ = 175 ° C
1.4
10,000
1.3
1.2
1.1
1000
1.0 TJ = 125 ° C
0.9
0.8
0.7 100
−50 −25 0 25 50 75 100 125 150 175 0 5 10 15 20
TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current
Temperature vs. Drain Voltage
, DRAIN CURRENT (AMPS) , DRAIN CURRENT (AMPS)
ID ID
) � ) �
, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (
DS(on) DS(on)
R R
, LEAKAGE (nA)
(NORMALIZED) IDSS
, DRAIN−TO−SOURCE RESISTANCE
DS(on)
R
**----- End of picture text -----**
**www.onsemi.com** **4** **NTD4804N, NVD4804N** ## **TYPICAL PERFORMANCE CURVES** **==> picture [242 x 171] intentionally omitted <==** **----- Start of picture text -----**
6000
Ciss TJ = 25 ° C
5000
4000
Ciss
3000
Crss
2000
1000 C oss
0 VDS = 0 V VGS = 0 V Crss
15 10 5 0 5 10 15 20 25 30
VGS VDS
C, CAPACITANCE (pF)
**----- End of picture text -----**
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) **Figure 7. Capacitance Variation** **==> picture [227 x 172] intentionally omitted <==** **----- Start of picture text -----**
5
QT
4 Q 1 Q 2
3
2
1
ID = 30 A
TJ = 25 ° C
0
0 5 10 15 20 25 30
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) QG, TOTAL GATE CHARGE (nC)
**----- End of picture text -----**
**Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge** **==> picture [241 x 387] intentionally omitted <==** **----- Start of picture text -----**
1000
V DD = 15 V
I D = 30 A
VGS = 11.5 V
100
tr
td(off)
tf
td(on)
10
1
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
1000
10 � s
100
100 � s
VGS = 20 V 1 ms
SINGLE PULSE
10 TC = 25 ° C
10 ms
RDS(on) LIMIT
THERMAL LIMIT dc
PACKAGE LIMIT
1
0.1 1 10 100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
t, TIME (ns)
ID, DRAIN CURRENT (AMPS)
**----- End of picture text -----**
**Figure 11. Maximum Rated Forward Biased Safe Operating Area** **==> picture [245 x 387] intentionally omitted <==** **----- Start of picture text -----**
30
VGS = 0 V
25 TJ = 25 ° C
20
15
10
5
0
0 0.2 0.4 0.6 0.8 1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage vs. Current
500
ID = 30 A
400
300
200
100
0
25 50 75 100 125 150 175
TJ, JUNCTION TEMPERATURE ( ° C)
IS, SOURCE CURRENT (AMPS)
AVALANCHE ENERGY (mJ)
EAS, SINGLE PULSE DRAIN−TO−SOURCE
**----- End of picture text -----**
**Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature** **www.onsemi.com** **5** **NTD4804N, NVD4804N** ## **TYPICAL PERFORMANCE CURVES** **==> picture [479 x 415] intentionally omitted <==** **----- Start of picture text -----**
100
125 ° C 100 ° C 25 ° C
10
1
1 10 100 1000
PULSE WIDTH ( � s)
Figure 13. Avalanche Characteristics
1.0
D = 0.5
0.2
0.1
0.1 0.05 P(pk)
0.02 R � JC(t) = r(t) R � JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.01
SINGLE PULSE t1 READ TIME AT t1
t2 TJ(pk) − TC = P(pk) R � JC(t)
DUTY CYCLE, D = t1/t2
0.01
1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01
t, TIME ( � s)
ID, DRAIN CURRENT (AMPS)
(NORMALIZED)
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
**----- End of picture text -----**
**Figure 14. Thermal Response** ## **ORDERING INFORMATION** |**ORDERING INFORMATION**||| |---|---|---| |**Order Number**|**Package**|**Shipping**†| |NTD4804NT4G|DPAK
(Pb−Free)|2500 / Tape & Reel| |NTD4804N−35G|IPAK Trimmed Lead
(3.5�0.15 mm)
(Pb−Free)|75 Units / Rail| |NVD4804NT4G|DPAK
(Pb−Free)|2500 / Tape & Reel| |NVD4804NT4G−VF01|DPAK
(Pb−Free)|2500 / Tape & Reel| †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. **www.onsemi.com** **6** **NTD4804N, NVD4804N** ## **PACKAGE DIMENSIONS** **DPAK (SINGLE GUAGE)** CASE 369AA ISSUE B **==> picture [467 x 379] intentionally omitted <==** **----- Start of picture text -----**
NOTES:
C 1. DIMENSIONING AND TOLERANCING PER ASME
A Y14.5M, 1994.
E A 2.3. CONTROLLING DIMENSION: INCHES.THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
b3 B c2 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
L3 4 Z 5. DIMENSIONS D AND E ARE DETERMINED AT THEOUTERMOST EXTREMES OF THE PLASTIC BODY.
1 2 3 D DETAIL A H 6. DATUMS A AND B ARE DETERMINED AT DATUMPLANE H.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
L4 A 0.086 0.094 2.18 2.38
b2 A1 0.000 0.005 0.00 0.13
b c b 0.025 0.035 0.63 0.89
b2 0.030 0.045 0.76 1.14
e 0.005 (0.13) M C H b3 0.180 0.215 4.57 5.46
c 0.018 0.024 0.46 0.61
L2 [GAUGE] PLANE C SEATINGPLANE c2D 0.0180.235 0.0240.245 0.465.97 0.616.22
E 0.250 0.265 6.35 6.73
e 0.090 BSC 2.29 BSC
H 0.370 0.410 9.40 10.41
L A1 L 0.055 0.070 1.40 1.78
L1 L1 0.108 REF 2.74 REF
L2 0.020 BSC 0.51 BSC
DETAIL A L3 0.035 0.050 0.89 1.27
ROTATED 90 CW � L4 −−− 0.040 −−− 1.01
Z 0.155 −−− 3.93 −−−
STYLE 2:
SOLDERING FOOTPRINT* PIN 1. GATE
2. DRAIN
6.20 3.00 3.4. SOURCEDRAIN
0.244 0.118
2.58
0.102
5.80
1.60 6.17
0.228
0.063 0.243
SCALE 3:1
� inches [mm] �
**----- End of picture text -----**
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. **www.onsemi.com** **7** **NTD4804N, NVD4804N** ## **PACKAGE DIMENSIONS** **3.5 MM IPAK, STRAIGHT LEAD** CASE 369AD ISSUE B **==> picture [475 x 209] intentionally omitted <==** **----- Start of picture text -----**
|||||||| |---|---|---|---|---|---|---| |NOTES:| |E|A|1..|DIMENSIONING AND TOLERANCING PER| |ASME Y14.5M, 1994.| |L2|E3|A1|E2|2..|CONTROLLING DIMENSION: MILLIMETERS.| |3.|DIMENSION b APPLIES TO PLATED TERMINAL| |4,|AND IS MEASURED BETWEEN 0.15 AND| |0.30mm FROM TERMINAL TIP.| |D2|4.|DIMENSIONS D AND E DO NOT INCLUDE| |MOLD GATE OR MOLD FLASH.| |D| |L1|MILLIMETERS| |DIM|MIN|MAX| |A|2.19|2.38| |L|A1|0.46|0.60| |T|A2|0.87|1.10| |SEATING|b|0.69|0.89| |PLANE|b1|A1|E2|b1|0.77|1.10| |D|5.97|6.22| |2X|e|A2|D2|4.80|−−−| |E|6.35|6.73| |3X|b|D2|E2|4.57|5.45| |0.13|M|T|E3|4.45|5.46| |e|2.28 BSC| |L|3.40|3.60| |L1|−−−|2.10| |L2|0.89|1.27| |a| |OPTIONAL| |CONSTRUCTION| **----- End of picture text -----**
**IPAK** CASE 369D **==> picture [37 x 8] intentionally omitted <==** **----- Start of picture text -----**
ISSUE C
**----- End of picture text -----**
**==> picture [475 x 297] intentionally omitted <==** **----- Start of picture text -----**
|||||||||||||| |---|---|---|---|---|---|---|---|---|---|---|---|---| |B|C|NOTES:| |1.|DIMENSIONING AND TOLERANCING PER| |V|R|E|ANSI Y14.5M, 1982.| |2.|CONTROLLING DIMENSION: INCH.| |INCHES|MILLIMETERS| |B|4|oe|Z|DIMA|0.235|MIN|0.245|MAX|5.97|MIN|MAX|6.35| |S|A|B|0.250|0.265|6.35|6.73| |1|2|3|C|0.086|0.094|2.19|2.38| |D|0.027|0.035|0.69|0.88| |E|0.018|0.023|0.46|0.58| |−T−|F|0.037|0.045|0.94|1.14| |SEATING|G|0.090 BSC|2.29 BSC| |PLANE|K|H|0.034|0.040|0.87|1.01| |J|0.018|0.023|0.46|0.58| |K|0.350|0.380|8.89|9.65| |R|0.180|0.215|4.45|5.45| |J|S|0.025|0.040|0.63|1.01| |F|H|STYLE 2:PIN 1.|GATE|VZ|0.1550.035|0.050−−−|3.930.89|1.27−−−| |D|3 PL|2.|DRAIN| |3.|SOURCE| |“a|G|0.13 (0.005)|L|M|T|W|4.|DRAIN| |ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.| |ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent| |coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.| |ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability| |arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.| |Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,| |regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or| |specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer| |application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not| |designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification| |in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized| |application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and| |expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such| |claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This| |literature is subject to all applicable copyright laws and is not for resale in any manner.| **----- End of picture text -----**
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