# Power MOSFET, Logic Level, P Channel, 30 V, 25 A, 0.08 ohm, TO-252 (DPAK), Surface Mount
**URL**: https://novapart.co/products/NTD25P03LT4G/power-mosfet-logic-level-p-channel-30-v-25-a-008
**SKU**: NTD25P03LT4G
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.3620
**Stock**: 1000+
**Lead Time**: 106 days (indicative)
## Description
Transistor Polarity:P Channel; Continuous Drain Current Id:-25A; Drain Source Voltage Vds:-30V; On Resistance Rds(on):0.056ohm; Rds(on) Test Voltage Vgs:-5V; Threshold Voltage Vgs:-1.6V; Po
## Specifications
| Parameter | Value |
|---|---|
| Msl | - |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | P Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 75W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 5V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 30V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 25A |
| Drain Source On State Resistance | 0.08ohm |
| Gate Source Threshold Voltage Max | 1.6V |
## Datasheet
📄 [Download PDF](https://novapart.co/datasheet/farnell:2101430/)
NTD25P03L, STD25P03L
## Power MOSFET
## **−25 A, −30 V, Logic Level P−Channel DPAK**
Designed for low voltage, high speed switching applications and to withstand high energy in the avalanche and commutation modes. The source−to−drain diode recovery time is comparable to a discrete fast recovery diode.
## **Features**
- S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable
- These Devices are Pb−Free and are RoHS Compliant
## **Typical Applications**
- PWM Motor Controls
- Power Supplies
- Converters
- Bridge Circuits
**MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted)
|**MAXIMUM RATINGS**(TJ = 25J = 25= 25°C unless otherwise noted)|C unless otherwise noted)|C unless otherwise noted)||
|---|---|---|---|
|**Rating**
~~_—————EE~~|**Symbol**
~~_—————EE~~|**Value**
~~_—————EE~~|**Unit**
~~_—————EE~~|
|Drain−to−Source Voltage
~~_—————EE~~
~~—~~|VDSS
~~_—————EE~~
|−30
~~_—————EE~~
|V
~~_—————EE~~
|
|Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tp≤10 ms)
~~—~~|VGS
VGSM
|±15
±20
|V
Vpk
|
|Drain Current
− Continuous @ TA= 25°C
− Single Pulse (tp ≤10 s)
~~—rs~~
~~Pe~~|ID
IDM
~~rs~~|−25
−75
~~rs~~|A
Apk
~~rs~~|
|Total Power Dissipation @ TA= 25°C
~~rs~~
~~Pe~~|PD
~~rs~~|75
~~rs~~|W
~~rs~~|
|Operating and Storage Temperature Range
~~Pe~~|TJ, Tstg|−55 to
+150|°C|
|Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ= 25°C
(VDD= 25 Vdc, VGS= 5.0 Vdc,
Peak IL= 20 Apk, L = 1.0 mH, RG= 25 )
~~Pe~~
~~ae~~|EAS
~~ae~~|200
~~ae~~|mJ
~~ae~~|
|Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
~~nae~~|R JC
R JA
R JA
~~nae~~|1.65
67
120
~~nae~~|°C/W
~~nae~~|
|Maximum Lead Temperature for Soldering
Purposes, (1/8 in from case for 10 seconds)
~~SE~~|TL
~~SE~~|260
~~SE~~|°C
~~SE~~|
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
## **http://onsemi.com**
**==> picture [164 x 401] intentionally omitted <==**
**----- Start of picture text -----**
V(BR)DSS RDS(on) Typ ID Max
−30 V 51 m @ 5.0 V −25 A
D
P−Channel
G
S
4
1 > [2]
3
DPAK
CASE 369C
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
on 2
1 3
Drain
Gate Source
A = Assembly Location*
Y = Year
WW = Work Week
25P03L = Device Code
G = Pb−Free Package
AYWW 25P 03LG
**----- End of picture text -----**
- The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank.
1. When surface mounted to an FR4 board using 0.5 sq in pad size.
2. When surface mounted to an FR4 board using the minimum recommended pad size.
## **ORDERING INFORMATION**
See detailed ordering and shipping information on page 7 of this data sheet.
Publication Order Number:
**1**
© Semiconductor Components Industries, LLC, 2014 **September, 2014 − Rev. 5**
**NTD25P03L/D**
## **NTD25P03L, STD25P03L**
## **ELECTRICAL CHARACTERISTICS** (TC = 25 ° C unless otherwise noted)
|**ELECTRICAL CHARACTERISTICS**(TC= 25°C unless otherwise noted)|**ELECTRICAL CHARACTERISTICS**(TC= 25°C unless otherwise noted)||||||
|---|---|---|---|---|---|---|
|**Characteristic**||**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**|||||||
|Drain−to−Source Breakdown Voltage (Note 3)
(VGS= 0 Vdc, ID= −250�A)
Temperature Coefficient (Positive)||V(BR)DSS|−30|−24||V
mV/°C|
|Zero Gate Voltage Drain Current
(VDS= −30 Vdc, VGS= 0 Vdc, TJ= 25°C)
(VDS= −30 Vdc, VGS= 0 Vdc, TJ= 125°C)||IDSS|||−1.0
−100|�A|
|Gate−Body Leakage Current
(VGS=±15 Vdc, VDS= 0 Vdc)||IGSS|||−100|nA|
|**ON CHARACTERISTICS**(Note 3)|||||||
|Gate Threshold Voltage
(VDS= VGS, ID= −250�Adc)
Temperature Coefficient (Negative)||VGS(th)|−1.0|−1.6
4.0|−2.0|V
mV/°C|
|Static Drain−to−Source On−State Resistance
(VGS= −5.0 Vdc, ID= −12.5 Adc)
(VGS= −5.0 Vdc, ID= −25 Adc)
(VGS= −4.0 Vdc, ID= −10 Adc)||RDS(on)||0.051
0.056
0.065|0.072
0.080
0.090|�|
|Forward Transconductance
(VDS= −8.0 Vdc, ID= −12.5 Adc)||gFS||13||Mhos|
|**DYNAMIC CHARACTERISTICS**|||||||
|Input Capacitance|(VDS= −25 Vdc, VGS= 0 Vdc,
f = 1.0 MHz)|Ciss||900|1260|pF|
|Output Capacitance||Coss||290|410||
|Reverse Transfer Capacitance||Crss||105|210||
|**SWITCHING CHARACTERISTICS**(Notes 3 & 4)|||||||
|Turn−On Delay Time|(VDD= −15 Vdc, ID= −25 A,
VGS= −5.0 V,
RG= 1.3�)|td(on)||9.0|20|ns|
|Rise Time||tr||37|75||
|Turn−Off Delay Time||td(off)||15|30||
|Fall Time||tf||16|55||
|Gate Charge|(VDS= −24 Vdc,
VGS= −5.0 Vdc,
ID= −25 A)|QT||15|20|nC|
|||Q1||3.0|||
|||Q2||9.0|||
|||Q3||7.0|||
|**BODY−DRAIN DIODE RATINGS**(Note 3)|||||||
|Diode Forward On−Voltage|(IS= −25 Adc, VGS= 0 V)
(IS= −25 Adc, VGS= 0 V, TJ= 125°C)|VSD||−1.0
−0.9|−1.5|V|
|Reverse Recovery Time|(IS= −25 A, VGS= 0 V,
dIS/dt = 100 A/�s)|trr||35||ns|
|||ta||20|||
|||tb||14|||
|Reverse Recovery Stored Charge||QRR||0.035||�C|
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperature.
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**NTD25P03L, STD25P03L**
## **TYPICAL MOSFET ELECTRICAL CHARACTERISTICS**
**==> picture [490 x 605] intentionally omitted <==**
**----- Start of picture text -----**
50 50
VGS = 10 V TJ = 25 ° C TJ = −40 ° C
40 9 V 6 V 5 V 40 V DS ≥ −5 V T J = 25 ° C
8 V
7 V 4.5 V TJ = 125 ° C
30 30
4 V
20 20
3.5 V
10 10
3 V
2.5 V
0 0
0 1 2 3 4 5 1 2 3 4 5 6
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
0.3 0.01
VGS = −5 V T J = 25 ° C
0.25
0.075
0.2 V GS = −5 V
0.15 0.05
V GS = −10 V
T = 125 ° C
0.1
T = 25 ° C 0.025
0.05
T = −40 ° C
0 0
0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50
−ID, DRAIN CURRENT (AMPS) −ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current Figure 4. On−Resistance versus Drain Current
and Temperature and Gate Voltage
1.6 10,000
ID = −12.5 VGS = 0 V
1.4 VGS = −5 V
1000 TJ = 150 ° C
1.2
1 TJ = 125 ° C
100
0.8
0.6 10
−50 −25 0 25 50 75 100 125 150 0 5 10 15 20 25 30
TJ, JUNCTION TEMPERATURE ( ° C) −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
, DRAIN CURRENT (AMPS) , DRAIN CURRENT (AMPS)
D D
−I −I
) � ) �
, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (
DS(on) DS(on)
R R
, LEAKAGE (nA)
(NORMALIZED) DSS
−I
, DRAIN−TO−SOURCE RESISTANCE
DS(on)
R
**----- End of picture text -----**
**Figure 5. On−Resistance Variation with Temperature**
**Figure 6. Drain−to−Source Leakage Current versus Voltage**
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**3**
**NTD25P03L, STD25P03L**
## **POWER MOSFET SWITCHING**
Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (�t) are determined by how fast the FET input capacitance can be charged by current from the generator.
The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
## where
VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are:
The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off).
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
**==> picture [243 x 186] intentionally omitted <==**
**----- Start of picture text -----**
2200
2000 C iss T J = 25 ° C
1800
1600
1400
1200 C rss
1000 Ciss
800
600
400 C oss
200 Crss
0 VDS = 0 V VGS = 0 V
10 5 0 5 10 15 20 25
−VGS −VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
**----- End of picture text -----**
**Figure 7. Capacitance Variation**
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**4**
**NTD25P03L, STD25P03L**
**==> picture [489 x 203] intentionally omitted <==**
**----- Start of picture text -----**
10 30 1000
Q T V DD = −15 V
−VDS 25 I D = −25 A
8 VTJGS = 25 = −5.0 V ° C tr
20 100
6 tf
Q 1 Q 2 −V GS 15 td(off)
4
10 10 td(on)
2 ID = −25 A 5
TJ = 25 ° C
0 Q 3 0 1
0 2.5 5 7.5 10 12.5 15 1 10 100
Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE ( � )
Figure 8. Gate−to−Source and Figure 9. Resistive Switching Time Variation
Drain−to−Source Voltage versus Total Charge versus Gate Resistance
t, TIME (ns)
, GATE−TO−SOURCE VOLTAGE (VOLTS) , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
GS DS
−V −V
**----- End of picture text -----**
## **DRAIN−TO−SOURCE DIODE CHARACTERISTICS**
The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 14. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses.
The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.
**==> picture [235 x 172] intentionally omitted <==**
**----- Start of picture text -----**
25
VGS = 0 V
20 TJ = 25 ° C
15
10
5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
, SOURCE CURRENT (AMPS)
S
−I
**----- End of picture text -----**
**Figure 10. Diode Forward Voltage versus Current**
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**5**
**NTD25P03L, STD25P03L**
## **SAFE OPERATING AREA**
The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.”
Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 �s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(R�JC).
A power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature.
Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
**==> picture [236 x 170] intentionally omitted <==**
**----- Start of picture text -----**
100
VGS = −20 V
SINGLE PULSE
TC = 25 ° C 100 � s
10 1 ms
10 ms
dc
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1 1 10 100
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
, DRAIN CURRENT (AMPS)
D
−I
**----- End of picture text -----**
**Figure 11. Maximum Rated Forward Biased Safe Operating Area**
**==> picture [247 x 200] intentionally omitted <==**
**----- Start of picture text -----**
200
180 I D = −20 A
160
140
120
100
80
60
40
20
0
25 50 75 100 125 150
TJ, STARTING JUNCTION TEMPERATURE ( ° C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
AVALANCHE ENERGY (mJ)
, SINGLE PULSE DRAIN−TO−SOURCE
AS
E
**----- End of picture text -----**
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**NTD25P03L, STD25P03L**
## **TYPICAL ELECTRICAL CHARACTERISTICS**
**==> picture [484 x 167] intentionally omitted <==**
**----- Start of picture text -----**
1
D = 0.5
0.2
0.1
0.1 0.05 P(pk)
R � JC(t) = r(t) R � JC
0.02 D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.01
t1 READ TIME AT t 1
SINGLE PULSE t2 TJ(pk) − TC = P(pk) R � JC(t)
DUTY CYCLE, D = t1/t2
0.01
1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01
t, TIME (s)
RESISTANCE (NORMALIZED)
r(t), EFFECTIVE TRANSIENT THERMAL
**----- End of picture text -----**
**Figure 13. Thermal Response**
**==> picture [203 x 98] intentionally omitted <==**
**----- Start of picture text -----**
di/dt
IS
t rr
ta t b
TIME
t p 0.25 IS
IS
**----- End of picture text -----**
**Figure 14. Diode Reverse Recovery Waveform**
## **ORDERING INFORMATION**
|**ORDERING INFORMATION**|||
|---|---|---|
|**Device**|**Package**|**Shipping**†|
|NTD25P03LT4G|DPAK
(Pb−Free)|2500 / Tape & Reel|
|STD25P03LT4G*|DPAK
(Pb−Free)|2500 / Tape & Reel|
- †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
- *S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable.
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**7**
**NTD25P03L, STD25P03L**
## **PACKAGE DIMENSIONS**
**==> picture [484 x 447] intentionally omitted <==**
**----- Start of picture text -----**
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE E
NOTES:
A 1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
E C 2. CONTROLLING DIMENSION: INCHES.
A 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
b3 B c2 4. DIMENSIONS D AND E DO NOT INCLUDE MOLDMENSIONS b3, L3 and Z.
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
4 NOT EXCEED 0.006 INCHES PER SIDE.
L3 bale ve Z Z 5. DIMENSIONS D AND E ARE DETERMINED AT THE
D DETAIL A H 6. DATUMS A AND B ARE DETERMINED AT DATUMOUTERMOST EXTREMES OF THE PLASTIC BODY.
1 2 3 PLANE H.
7. OPTIONAL MOLD FEATURE.
L4 NOTE 7 DIM MININCHESMAX MILLIMETERSMIN MAX
b2 c BOTTOM VIEW BOTTOM VIEW A 0.086 0.094 2.18 2.38
e b SIDE VIEW CONSTRUCTIONALTERNATE A1b 0.0000.025 0.0050.035 0.000.63 0.130.89
TOP VIEW 0.005 (0.13) M C H b2b3 0.0280.180 0.0450.215 0.724.57 1.145.46
c 0.018 0.024 0.46 0.61
L2 [GAUGE] PLANE C SEATINGPLANE c2D 0.0180.235 0.0240.245 0.465.97 0.616.22
E 0.250 0.265 6.35 6.73
e 0.090 BSC 2.29 BSC
L H 0.370 0.410 9.40 10.41
A1 L 0.055 0.070 1.40 1.78
L1 L1 0.114 REF 2.90 REF
DETAIL A L2 0.020 BSC 0.51 BSC
ROTATED 9 CW L3 0.035 0.050 0.89 1.27
L4 −−− 0.040 −−− 1.01
Z 0.155 −−− 3.93 −−−
STYLE 2:
SOLDERING FOOTPRINT* PIN 1. GATE
2. DRAIN
6.20 3.00 3.4. SOURCEDRAIN
0.244 0.118
2.58
PA
0.102
5.80
1.60 6.17
0.228
0.063 0.243
Ts"
SCALE 3:1 mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
**----- End of picture text -----**
ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
## **PUBLICATION ORDERING INFORMATION**
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## **LITERATURE FULFILLMENT** :
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**NTD25P03L/D**
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## Links
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- [Supplier page](https://es.farnell.com/on-semiconductor/ntd25p03lt4g/mosfet-p-ch-30v-25a-d-pak/dp/2101430)
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