# Power MOSFET, N Channel, 60 V, 18 A, 0.065 ohm, TO-252 (DPAK), Surface Mount ![Product image](https://novapart.co/image/farnell:2533181/) **URL**: https://novapart.co/products/NTD18N06LT4G/power-mosfet-n-channel-60-v-18-a-0065-ohm-to-252 **SKU**: NTD18N06LT4G **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.4390 **Stock**: 1000+ **Lead Time**: 148 days (indicative) ## Description Transistor Polarity:N Channel; Continuous Drain Current Id:18A; Drain Source Voltage Vds:60V; On Resistance Rds(on):0.054ohm; Rds(on) Test Voltage Vgs:5V; Threshold Voltage Vgs:1.8V ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | No SVHC (25-Jun-2025) | | No. Of Pins | 3Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | - | | Power Dissipation | 55W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 5V | | Transistor Case Style | TO-252 (DPAK) | | Drain Source Voltage Vds | 60V | | Operating Temperature Max | 175°C | | Continuous Drain Current Id | 18A | | Drain Source On State Resistance | 0.065ohm | | Gate Source Threshold Voltage Max | 1.8V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2533181/) ## NTD18N06L, NTDV18N06L ## Power MOSFET ## **18 A, 60 V, Logic Level N−Channel DPAK** Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. **www.onsemi.com** ## **Features** **==> picture [492 x 429] intentionally omitted <==** **----- Start of picture text -----**
|||||||| |---|---|---|---|---|---|---| |•|AEC Q101 Qualified − NTDV18N06L|V(BR)DSS|RDS(on) TYP|ID MAX| |•|These Devices are Pb−Free and are RoHS Compliant|60 V|54 m|5.0 V|18 A| |(Note 1)| |jfow||| |Typical Applications| |•|Power Supplies|D| |•|Converters| |•|Power Motor Controls| |N−Channel| |•|Bridge Circuits|G| |MAXIMUM RATINGS|(TJ = 25|°|C unless otherwise noted)|S| |Rating|Symbol|Value|Unit| |4| |Drain−to−Source Voltage|VDSS|60|Vdc| |Drain−to−Gate Voltage (RGS = 10 M|)|VDGR|60|Vdc| |or|1|2|[2]| |Gate−to−Source Voltage|Vdc|3| |− Continuous|VGS|±|15| |DPAK| |− Non−repetitive (tp|10 ms)|VGS|±|20|CASE 369C| |Drain Current| |− Continuous @ TA = 25|°|C|ID|18|Adc|STYLE 2| |− Continuous @ TA = 100|°|C|ID|10| |SEE|− Single Pulse (tp|10 s)|IDM|54|Apk|MARKING DIAGRAM| |Total Power Dissipation @ TA = 25|°|C|PD|55|W|& PIN ASSIGNMENT| |Derate above 25|°|C|0.36|W/|°|C| |Total Power Dissipation @ TA = 25|°|C (Note 2)|2.1|W|4| |Se|Operating and Storage Temperature Range|TJ, Tstg|−55 to|°|C|Drain| |+175| |Single Pulse Drain−to−Source Avalanche|EAS|72|mJ| |Energy − Starting TJ = 25|°|C| |(VDD = 50 Vdc, VGS = 5.0 Vdc,| |L = 1.0 mH, IL(pk) = 12 A, VDS = 60 Vdc)| |oO|Thermal Resistance|°|C/W|1|2|3| |Drain| |− Junction−to−Case|R|JC|2.73|Gate|Source| |− Junction−to−Ambient (Note 1)|R|JA|100| |− Junction−to−Ambient (Note 2)|R|JA|71.4|A|= Assembly Location*| |Maximum Lead Temperature for Soldering|TL|260|°|C|18N6L|= Device Code| |Purposes, 1/8|″|from case for 10 seconds|Y|= Year| |ee|WW|= Work Week| |Stresses exceeding those listed in the Maximum Ratings table may damage the|G|= Pb−Free Device| **----- End of picture text -----**
- AEC Q101 Qualified − NTDV18N06L - These Devices are Pb−Free and are RoHS Compliant ## **Typical Applications** - Power Supplies - Converters - Power Motor Controls - Bridge Circuits Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. * The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. 1. When surface mounted to an FR−4 board using the minimum recommended pad size. 2. When surface mounted to an FR−4 board using the 0.5 sq in drain pad size. ## **ORDERING INFORMATION** See detailed ordering and shipping information on page 2 of this data sheet. Publication Order Number: **1** © Semiconductor Components Industries, LLC, 2016 **November, 2018 − Rev. 8** **NTD18N06L/D** ## **NTD18N06L, NTDV18N06L** ## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) |**ELECTRICAL CHARACTERISTICS **(TJ= 25°C unless otherwise noted)|**ELECTRICAL CHARACTERISTICS **(TJ= 25°C unless otherwise noted)|||||| |---|---|---|---|---|---|---| |**Characteristic**||**Symbol**|**Min**|**Typ**|**Max**|**Unit**| |**OFF CHARACTERISTICS**||||||| |Drain−to−Source Breakdown Voltage (Note 3)
(VGS= 0 Vdc, ID= 250�Adc)
Temperature Coefficient (Positive)||V(BR)DSS|60
−|70
57.6|−
−|Vdc
mV/°C| |Zero Gate Voltage Drain Current
(VDS= 60 Vdc, VGS= 0 Vdc)
(VDS= 60 Vdc, VGS= 0 Vdc, TJ= 150°C)||IDSS|−
−|−
−|1.0
10|�Adc| |Gate−BodyLeakage Current (VGS=±15 Vdc, VDS= 0 Vdc)||IGSS|−|−|±100|nAdc| |**ON CHARACTERISTICS**(Note 3)||||||| |Gate Threshold Voltage (Note 3)
(VDS= VGS, ID= 250�Adc)
Threshold Temperature Coefficient (Negative)||VGS(th)|1.0
−|1.8
5.2|2.0
−|Vdc
mV/°C| |Static Drain−to−Source On−Resistance (Note 3)
(VGS= 5.0 Vdc, ID= 9.0 Adc)||RDS(on)|−|54|65|m�| |Static Drain−to−Source On−Resistance (Note 3)
(VGS= 5.0 Vdc, ID= 18 Adc)
(VGS= 5.0 Vdc, ID= 9.0 Adc, TJ= 150°C)||VDS(on)|−
−|1.0
0.86|1.3
−|Vdc| |Forward Transconductance (Note 3) (VDS= 7.0 Vdc, ID= 9.0 Adc)||gFS|−|13.5|−|mhos| |**DYNAMIC CHARACTERISTICS**||||||| |Input Capacitance|(VDS= 25 Vdc, VGS= 0 Vdc,
f = 1.0 MHz)|Ciss|−|482|675|pF| |Output Capacitance||Coss|−|166|230|| |Transfer Capacitance||Crss|−|56|80|| |**SWITCHING CHARACTERISTICS**(Note 4)||||||| |Turn−On Delay Time|(VDD= 30 Vdc, ID= 18 Adc,
VGS= 5.0 Vdc,
RG= 9.1�) (Note 3)|td(on)|−|9.9|20|ns| |Rise Time||tr|−|79|160|| |Turn−Off Delay Time||td(off)|−|19|40|| |Fall Time||tf|−|38|80|| |Gate Charge|(VDS= 48 Vdc, ID= 18 Adc,
VGS= 5.0 Vdc) (Note 3)|QT|−|11|22|nC| |||Q1|−|3.2|−|| |||Q2|−|6.5|−|| |**SOURCE−DRAIN DIODE CHARACTERISTICS**||||||| |Forward On−Voltage|(IS= 18 Adc, VGS= 0 Vdc) (Note 3)
(IS= 18 Adc, VGS= 0 Vdc, TJ= 150°C)|VSD|−
−|0.94
0.83|1.15
−|Vdc| |Reverse Recovery Time|(IS= 18 Adc, VGS= 0 Vdc,
dIS/dt = 100 A/�s) (Note 3)|trr|−|41|−|ns| |||ta|−|26|−|| |||tb|−|15|−|| |Reverse RecoveryStored Charge||QRR|−|0.057|−|�C| Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. ## **ORDERING INFORMATION** |**Device**|**Package**|**Shipping**†| |---|---|---| |NTD18N06LT4G|DPAK
(Pb−Free)|2500 / Tape & Reel| |NTDV18N06LT4G|DPAK
(Pb−Free)|2500 / Tape & Reel| |STD18N06LT4G−VF01|DPAK
(Pb−Free)|2500 / Tape & Reel| †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. **www.onsemi.com** **2** **NTD18N06L, NTDV18N06L** **==> picture [490 x 632] intentionally omitted <==** **----- Start of picture text -----**
40 40
VGS = 10 V 5.5 V 5 V VDS ≥ 10 V
8 V
30 30
6 V 4.5 V
20 20
4 V
3.5 V
10 10 T J = 25 ° C
3 V T J = 100 ° C T J = −55 ° C
0 0
0 1 2 3 4 1.6 2.4 3.2 4 4.8 5.6
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
0.12 0.12
VGS = 5 V
VGS = 10 V
0.1 0.1
TJ = 100 ° C
0.08 0.08
TJ = 25 ° C TJ = 100 ° C
0.06 0.06
TJ = 25 ° C
0.04 TJ = −55 ° C 0.04
TJ = −55 ° C
0.02 0.02
0 0
0 10 20 30 40 0 10 20 30 40
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Figure 4. On−Resistance versus Drain Current
Gate−to−Source Voltage and Gate Voltage
2 10000
ID = 9 A VGS = 0 V
1.8 VGS = 5 V TJ = 150 ° C
1000
1.6
1.4
100
1.2
TJ = 100 ° C
1
10
0.8
0.6 1
−50 −25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60
TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current
Temperature versus Voltage
, DRAIN CURRENT (AMPS) , DRAIN CURRENT (AMPS)
ID ID
) � ) �
, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (
DS(on) DS(on)
R R
, LEAKAGE (nA)
(NORMALIZED) IDSS
, DRAIN−TO−SOURCE RESISTANCE
DS(on)
R
**----- End of picture text -----**
**www.onsemi.com** **3** **NTD18N06L, NTDV18N06L** ## **POWER MOSFET SWITCHING** Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (�t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP ## where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) **==> picture [242 x 171] intentionally omitted <==** **----- Start of picture text -----**
1400
Ciss TJ = 25 ° C
1200
VDS = 0 V VGS = 0 V
1000
800 Crss
600 Ciss
400
Coss
200
0 Crss
10 5 0 5 10 15 20 25
VGS VDS
C, CAPACITANCE (pF)
**----- End of picture text -----**
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) **Figure 7. Capacitance Variation** **www.onsemi.com** **4** **NTD18N06L, NTDV18N06L** **==> picture [490 x 402] intentionally omitted <==** **----- Start of picture text -----**
8 1000
6
Q T VGS 100 tr
Q 1 Q2 tf
4
td(off)
10 td(on)
2
VDS = 30 V
ID = 18 A ID = 18 A
TJ = 25 ° C VGS = 5 V
0 1
0 2 4 6 8 10 12 1 10 100
QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE ( � )
Figure 8. Gate−To−Source and Drain−To−Source Figure 9. Resistive Switching Time
Voltage versus Total Charge Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
20
VGS = 0 V
TJ = 25 ° C
16
12
8
4
0
0.6 0.68 0.76 0.84 0.92 1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
t, TIME (ns)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
IS, SOURCE CURRENT (AMPS)
**----- End of picture text -----**
**Figure 10. Diode Forward Voltage versus Current** ## **SAFE OPERATING AREA** The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 �s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(R�JC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. **www.onsemi.com** **5** **NTD18N06L, NTDV18N06L** ## **SAFE OPERATING AREA** **==> picture [490 x 395] intentionally omitted <==** **----- Start of picture text -----**
100 80
V GS = 15 V ID = 12 A
SINGLE PULSE TC = 25 ° C 10 � s 60
10
100 � s
1 ms 40
10 ms
1 dc
RDS(on) LIMIT 20
THERMAL LIMIT
PACKAGE LIMIT
0.1 0
0.1 1 10 100 25 50 75 100 125 150 175
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE ( ° C)
Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
0.1 0.05 P(pk)
0.02 R � JC(t) = r(t) R � JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.01
SINGLE PULSE t1 READ TIME AT t1
t2 TJ(pk) − TC = P(pk) R � JC(t)
DUTY CYCLE, D = t1/t2
0.01
1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01
t, TIME ( � s)
ID, DRAIN CURRENT (AMPS)
AVALANCHE ENERGY (mJ)
EAS, SINGLE PULSE DRAIN−TO−SOURCE
(NORMALIZED)
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
**----- End of picture text -----**
**Figure 13. Thermal Response** **==> picture [204 x 99] intentionally omitted <==** **----- Start of picture text -----**
di/dt
IS
t rr
ta t b
TIME
t p 0.25 IS
IS
**----- End of picture text -----**
**Figure 14. Diode Reverse Recovery Waveform** **www.onsemi.com** **6** **NTD18N06L, NTDV18N06L** ## **PACKAGE DIMENSIONS** **DPAK (SINGLE GAUGE)** CASE 369C **==> picture [36 x 8] intentionally omitted <==** **----- Start of picture text -----**
ISSUE F
**----- End of picture text -----**
**==> picture [481 x 422] intentionally omitted <==** **----- Start of picture text -----**
NOTES:
A 1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
E C 2. CONTROLLING DIMENSION: INCHES.
A 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
b3 B c2 4. DIMENSIONS D AND E DO NOT INCLUDE MOLDMENSIONS b3, L3 and Z.
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
4 NOT EXCEED 0.006 INCHES PER SIDE.
L3 bale Z 5. DIMENSIONS D AND E ARE DETERMINED AT THE
D DETAIL A H 6. DATUMS A AND B ARE DETERMINED AT DATUMOUTERMOST EXTREMES OF THE PLASTIC BODY.
1 2 3 PLANE H.
7. OPTIONAL MOLD FEATURE.
L4 NOTE 7 DIM MININCHESMAX MILLIMETERSMIN MAX
b2 c BOTTOM VIEW A 0.086 0.094 2.18 2.38
e SIDE VIEW A1 0.000 0.005 0.00 0.13
ie b Coo b 0.025 0.035 0.63 0.89
TOP VIEW 0.005 (0.13) M C b2b3 0.0280.180 0.0450.215 0.724.57 1.145.46
c 0.018 0.024 0.46 0.61
c2 0.018 0.024 0.46 0.61
H Z Z D 0.235 0.245 5.97 6.22
E 0.250 0.265 6.35 6.73
e 0.090 BSC 2.29 BSC
L2 [GAUGE] PLANE C SEATINGPLANE HL 0.3700.055 0.4100.070 9.401.40 10.411.78
L1 0.114 REF 2.90 REF
L2 0.020 BSC 0.51 BSC
L L3 0.035 0.050 0.89 1.27
A1 BOTTOM VIEW L4 −−− 0.040 −−− 1.01
pot L1 s Sa CONSTRUCTIONS t ALTERNATE Z 0.155 −−− 3.93 −−−
DETAIL A
ROTATED 9 CW STYLE 2:
SOLDERING FOOTPRINT* PIN 1. GATE
2. DRAIN
3. SOURCE
6.20 3.00 4. DRAIN
0.244 0.118
2.58
0.102
5.80
1.60 6.17
0.228
0.063 0.243
ee
SCALE 3:1 mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
**----- End of picture text -----**
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