# Power MOSFET, N Channel, 60 V, 45 A, 0.023 ohm, TO-263 (D2PAK), Surface Mount

![Product image](https://novapart.co/image/farnell:2845367/)

**URL**: https://novapart.co/products/NTB45N06LT4G/power-mosfet-n-channel-60-v-45-a-0023-ohm-to-263
**SKU**: NTB45N06LT4G
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.5100
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Power Dissipation | 125W |
| Transistor Mounting | Surface Mount |
| Transistor Polarity | N Channel |
| Power Dissipation Pd | 125W |
| Rds(On) Test Voltage | 5V |
| On Resistance Rds(On) | 0.023ohm |
| Transistor Case Style | TO-263 (D2PAK) |
| Drain Source Voltage Vds | 60V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 45A |
| Drain Source On State Resistance | 0.023ohm |
| Gate Source Threshold Voltage Max | 1.8V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2845367/)

## NTB45N06L, NTBV45N06L 

## Power MOSFET 45 Amps, 60 Volts 

## **Logic Level, N−Channel D[2] PAK** 

Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. 

## **Features** 

- Higher Current Rating 

- Lower RDS(on) 

- Lower VDS(on) 

- Lower Capacitances 

- Lower Total Gate Charge 

- Tighter VSD Specification 

- Lower Diode Reverse Recovery Time 

- Lower Reverse Recovery Stored Charge 

- AEC−Q101 Qualified and PPAP Capable − NTBV45N06L 

- These Devices are Pb−Free and are RoHS Compliant 

## **Typical Applications** 

- Power Supplies 

- Converters 

- Power Motor Controls 

- Bridge Circuits 

## **http://onsemi.com** 

**==> picture [140 x 241] intentionally omitted <==**

**----- Start of picture text -----**<br>
45 AMPERES, 60 VOLTS<br>R  = 28 m<br>DS(on)<br>N−Channel<br>D<br>G<br>3 S<br>4<br>1 2<br>»<br>3<br>D [2] PAK<br>CASE 418B<br>STYLE 2<br>**----- End of picture text -----**<br>


**MARKING DIAGRAM & PIN ASSIGNMENT1** 4 Drain NTx 45N06LG AYWW ~~7~~ 1 2 3 Gate Drain Source NTx45N06L = Device Code x = B or P A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. 

Publication Order Number: **NTB45N06L/D** 

**1** 

© Semiconductor Components Industries, LLC, 2011 **October, 2011 − Rev. 1** 

**NTB45N06L, NTBV45N06L** 

**MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) 

|**MAXIMUM RATINGS**(TJ= 25°C unless otherwise noted)||||
|---|---|---|---|
|**Rating**|**Symbol**|**Value**|**Unit**|
|Drain−to−Source Voltage|VDSS|60|Vdc|
|Drain−to−Gate Voltage (RGS= 10 M�)|VDGR|60|Vdc|
|Gate−to−Source Voltage<br>− Continuous<br>− Non−Repetitive (tp�10 ms)|VGS<br>VGS|�15<br>�20|Vdc|
|Drain Current<br>− Continuous @ TA= 25°C<br>− Continuous @ TA= 100°C<br>− Single Pulse (tp�10�s)|ID<br>ID<br>IDM|45<br>30<br>150|Adc<br>Apk|
|Total Power Dissipation @ TA= 25°C<br>Derate above 25°C<br>Total Power Dissipation @ TA= 25°C (Note 1)<br>Total Power Dissipation @ TA= 25°C (Note 2)|PD|125<br>0.83<br>3.2<br>2.4|W<br>W/°C<br>W<br>W|
|Operating and Storage Temperature Range|TJ, Tstg|−55 to +175|°C|
|Single Pulse Drain−to−Source Avalanche Energy − Starting TJ= 25°C<br>(VDD= 50 Vdc, VGS= 5.0 Vdc, L = 0.3 mH<br>IL(pk)= 40 A, VDS= 60 Vdc, RG= 25�)|EAS|240|mJ|
|Thermal Resistance<br>− Junction−to−Case<br>− Junction−to−Ambient (Note 1)<br>− Junction−to−Ambient (Note 2)|R�JC<br>R�JA<br>R�JA|1.2<br>46.8<br>63.2|°C/W|
|Maximum Lead Temperature for Soldering Purposes, 1/8 in from case for 10 seconds|TL|260|°C|



Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 

1. When surface mounted to an FR4 board using 1 ″ pad size, (Cu Area 1.127 in[2] ). 

2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in[2] ). 

## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**|||
|---|---|---|
|**Device**|**Package**|**Shipping**†|
|NTB45N06LG|D2PAK<br>(Pb−Free)|50 Units / Rail|
|NTB45N06LT4G|D2PAK<br>(Pb−Free)|800 / Tape & Reel|
|NTBV45N06LT4G|D2PAK<br>(Pb−Free)|800 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

**http://onsemi.com** 

**2** 

**NTB45N06L, NTBV45N06L** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) 

|**ELECTRICAL CHARACTERISTICS **(TJ= 25°C unless otherwise noted)|**ELECTRICAL CHARACTERISTICS **(TJ= 25°C unless otherwise noted)||||||
|---|---|---|---|---|---|---|
|**Characteristic**||**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**|||||||
|Drain−to−Source Breakdown Voltage (Note 3)<br>(VGS= 0 Vdc, ID= 250�Adc)<br>Temperature Coefficient (Positive)||V(BR)DSS|60<br>−|67<br>67.2|−<br>−|Vdc<br>mV/°C|
|Zero Gate Voltage Drain Current<br>(VDS= 60 Vdc, VGS= 0 Vdc)<br>(VDS= 60 Vdc, VGS= 0 Vdc, TJ= 150°C)||IDSS|−<br>−|−<br>−|1.0<br>10|�Adc|
|Gate−Body Leakage Current (VGS=±15 Vdc, VDS= 0 Vdc)||IGSS|−|−|±100|nAdc|
|**ON CHARACTERISTICS**(Note 4)|||||||
|Gate Threshold Voltage (Note 4)<br>(VDS= VGS, ID= 250�Adc)<br>Threshold Temperature Coefficient (Negative)||VGS(th)|1.0<br>−|1.8<br>4.7|2.0<br>−|Vdc<br>mV/°C|
|Static Drain−to−Source On−Resistance (Note 4)<br>(VGS= 5.0 Vdc, ID= 22.5 Adc)||RDS(on)|−|23|28|m�|
|Static Drain−to−Source On−Voltage (Note 4)<br>(VGS= 5.0 Vdc, ID= 45 Adc)<br>(VGS= 5.0 Vdc, ID= 22.5 Adc, TJ= 150°C)||VDS(on)|−<br>−|1.03<br>0.93|1.51<br>−|Vdc|
|Forward Transconductance (Note 4) (|VDS= 8.0 Vdc, ID= 12 Adc)|gFS|−|22.8|−|mhos|
|**DYNAMIC CHARACTERISTICS**|||||||
|Input Capacitance|(VDS= 25 Vdc, VGS= 0 Vdc,<br>f = 1.0 MHz)|Ciss|−|1212|1700|pF|
|Output Capacitance||Coss|−|352|480||
|Transfer Capacitance||Crss|−|90|180||
|**SWITCHING CHARACTERISTICS**(Note 5)|||||||
|Turn−On Delay Time|(VDD= 30 Vdc, ID= 45 Adc,<br>VGS= 5.0 Vdc, RG= 9.1�) (Note 4)|td(on)|−|13|30|ns|
|Rise Time||tr|−|341|680||
|Turn−Off Delay Time||td(off)|−|36|75||
|Fall Time||tf|−|158|320||
|Gate Charge|(VDS= 48 Vdc, ID= 45 Adc,<br>VGS= 5.0 Vdc) (Note 4)|QT|−|23|32|nC|
|||Q1|−|4.6|−||
|||Q2|−|14.1|−||
|**SOURCE−DRAIN DIODE CHARACTERISTICS**|||||||
|Forward On−Voltage|(IS= 45 Adc, VGS= 0 Vdc) (Note 4)<br>(IS= 45 Adc, VGS= 0 Vdc, TJ= 150°C)|VSD|−<br>−|1.01<br>0.92|1.15<br>−|Vdc|
|Reverse Recovery Time|(IS= 45 Adc, VGS= 0 Vdc,<br>dIS/dt = 100 A/�s) (Note 4)|trr|−|56|−|ns|
|||ta|−|30|−||
|||tb|−|26|−||
|Reverse Recovery Stored Charge||QRR|−|0.09|−|�C|



3. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in[2] ). 

4. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 

5. Switching characteristics are independent of operating junction temperatures. 

**http://onsemi.com** 

**3** 

**NTB45N06L, NTBV45N06L** 

**==> picture [491 x 631] intentionally omitted <==**

**----- Start of picture text -----**<br>
80 80<br>VGS = 10 V V GS  = 5.5 V V DS  > = 10 V<br>70 70<br>VGS = 5 V<br>60 V GS  = 6 V 60<br>50 VGS = 4.5 V 50<br>V GS  = 7 V<br>40 40<br>30 VGS = 8 V V GS = 4 V 30 T J = 25 ° C<br>20 20<br>10 VGS = 9 V VGS = 3.5 V 10 T J  = 100 ° C<br>TJ = −55 ° C<br>0 0<br>0 1 2 3 4 1.8 2.6 3.4 4.2 5 5.8<br>VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>0.046 0.046<br>VGS = 5 V<br>0.042 0.042<br>TJ = 100 ° C<br>0.038<br>0.038<br>0.034<br>0.034<br>0.03 TJ = 25 ° C VGS = 5 V<br>0.03<br>0.026<br>0.026<br>0.022<br>0.018 TJ = −55 ° C 0.022 VGS = 10 V<br>0.014 0.018<br>0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80<br>ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>2 10000<br>ID = 22.5 A VGS = 0 V<br>1.8 VGS = 5 V TJ = 150 ° C<br>1.6<br>1000<br>1.4 TJ = 125 ° C<br>1.2<br>100<br>1<br>TJ = 100 ° C<br>0.8<br>0.6 10<br>−50 −25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current<br>Temperature vs. Voltage<br>, DRAIN CURRENT (AMPS) , DRAIN CURRENT (AMPS)<br>ID ID<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (nA)<br>(NORMALIZED) IDSS<br>, DRAIN−TO−SOURCE RESISTANCE<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


**http://onsemi.com** 

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**NTB45N06L, NTBV45N06L** 

**==> picture [246 x 185] intentionally omitted <==**

**----- Start of picture text -----**<br>
4000<br>VDS = 0 V VGS = 0 V TJ = 25 ° C<br>3600 Ciss<br>3200<br>2800 Crss<br>2400<br>2000<br>1600 Ciss<br>1200<br>800 Coss<br>400 Crss<br>0<br>10 5 VGS 0 VDS 5 10 15 20 25<br>GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE<br>(VOLTS)<br>C, CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


**Figure 7. Capacitance Variation** 

**==> picture [247 x 158] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000<br>VDS = 30 V<br>ID = 45 A<br>VGS = 5 V tr<br>tf<br>100<br>td(off)<br>td(on)<br>10<br>1 10 100<br>t, TIME (ns)<br>**----- End of picture text -----**<br>


RG, GATE RESISTANCE ( � ) 

**Figure 9. Resistive Switching Time Variation vs. Gate Resistance** 

**==> picture [233 x 187] intentionally omitted <==**

**----- Start of picture text -----**<br>
6<br>QT<br>5 VGS<br>Q1 Q2<br>4<br>3<br>2<br>1 ID = 45 A<br>TJ = 25 ° C<br>0<br>0 4 8 12 16 20 24<br>Qg, TOTAL GATE CHARGE (nC)<br>, GATE−TO−SOURCE VOLTAGE (VOLTS)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge** 

**==> picture [233 x 174] intentionally omitted <==**

**----- Start of picture text -----**<br>
48<br>VGS = 0 V<br>40 TJ = 25 ° C<br>32<br>24<br>16<br>8<br>0<br>0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96 1<br>VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)<br>, SOURCE CURRENT (AMPS)<br>IS<br>**----- End of picture text -----**<br>


**Figure 10. Diode Forward Voltage vs. Current** 

**==> picture [234 x 174] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000<br>VGS = 15 V<br>SINGLE PULSE<br>TC = 25 ° C<br>100<br>dc<br>10<br>10 ms<br>1 ms<br>1 RDS(on) Limit 100  � s<br>Thermal Limit<br>Package Limit<br>0.1<br>0.10 1 10 100<br>VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>, DRAIN CURRENT (AMPS)<br>ID<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

**==> picture [247 x 177] intentionally omitted <==**

**----- Start of picture text -----**<br>
280<br>I D  = 45 A<br>240<br>200<br>160<br>120<br>80<br>40<br>0<br>25 50 75 100 125 150 175<br>TJ, STARTING JUNCTION TEMPERATURE ( ° C)<br>AVALANCHE ENERGY (mJ)<br>, SINGLE PULSE DRAIN−TO−SOURCE<br>AS<br>E<br>**----- End of picture text -----**<br>


**Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature** 

**http://onsemi.com** 

**5** 

**NTB45N06L, NTBV45N06L** 

**==> picture [481 x 304] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>Normalized to R � JC  at Steady State<br>0.1<br>0.01<br>0.00001 0.0001 0.001 0.01 0.1 1 10<br>t, TIME (s)<br> EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED)<br>r(t),<br>**----- End of picture text -----**<br>


**Figure 13. Thermal Response** 

**==> picture [489 x 305] intentionally omitted <==**

**----- Start of picture text -----**<br>
10<br>Normalized to R � JA at Steady State,<br>1 ″  square Cu Pad, Cu Area 1.127 in [2] ,<br>3 x 3 inch FR4 board<br>1<br>0.1<br>0.01<br>0.001<br>0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>t, TIME (s)<br>r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)<br>**----- End of picture text -----**<br>


**Figure 14. Thermal Response** 

**http://onsemi.com** 

**6** 

**NTB45N06L, NTBV45N06L** 

## **PACKAGE DIMENSIONS** 

**==> picture [441 x 597] intentionally omitted <==**

**----- Start of picture text -----**<br>
D [2] PAK 3<br>CASE 418B−04<br>ISSUE K<br>NOTES:<br>C 1. DIMENSIONING AND TOLERANCING<br>PER ANSI Y14.5M, 1982.<br>E 2. CONTROLLING DIMENSION: INCH.<br>−B− V 3. 418B−01 THRU 418B−03 OBSOLETE,NEW STANDARD 418B−04.<br>W<br>4 INCHES MILLIMETERS<br>DIM MIN MAX MIN MAX<br>A 0.340 0.380 8.64 9.65<br>B 0.380 0.405 9.65 10.29<br>A C 0.160 0.190 4.06 4.83<br>S D 0.020 0.035 0.51 0.89<br>1 2 3 E 0.045 0.055 1.14 1.40<br>F 0.310 0.350 7.87 8.89<br>G 0.100 BSC 2.54 BSC<br>−T− H 0.080 0.110 2.03 2.79<br>K J 0.018 0.025 0.46 0.64<br>SEATINGPLANE G J W KL 0.0900.052 0.0720.110 2.291.32 2.791.83<br>M 0.280 0.320 7.11 8.13<br>H N 0.197 REF 5.00 REF<br>D 3 PL P 0.079 REF 2.00 REF<br>R 0.039 REF 0.99 REF<br>0.13 (0.005) M T B M S 0.575 0.625 14.60 15.88<br>V 0.045 0.055 1.14 1.40<br>STYLE 2:<br>PIN 1. GATE<br>2. DRAIN<br>VARIABLE 3. SOURCE<br>CONFIGURATION 4. DRAIN<br>ZONE N P<br>R<br>U<br>L L L<br>M M M<br>F F F<br>VIEW W−W VIEW W−W VIEW W−W<br>1 2 3<br>SOLDERING FOOTPRINT*<br>10.49<br>8.38<br>16.155<br>2X<br>3.504<br>2X<br>1.016<br>5.080<br>PITCH<br>DIMENSIONS: MILLIMETERS<br>**----- End of picture text -----**<br>


*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

**http://onsemi.com** 

**7** 

**NTB45N06L, NTBV45N06L** 

**ON Semiconductor** and          are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).  SCILLC reserves the right to make changes without further notice to any products herein.  SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.  All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.  SCILLC does not convey any license under its patent rights nor the rights of others.  SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.  Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.  SCILLC is an Equal Opportunity/Affirmative Action Employer.  This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **PUBLICATION ORDERING INFORMATION** 

**N. American Technical Support** : 800−282−9855 Toll Free USA/Canada 

## **LITERATURE FULFILLMENT** : 

Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA **Europe, Middle East and Africa Technical Support: Phone** : 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 **Fax** : 303−675−2176 or 800−344−3867 Toll Free USA/Canada **Japan Customer Focus Center Email** : orderlit@onsemi.com Phone: 81−3−5817−1050 

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**Order Literature** : http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative 

**NTB45N06L/D** 

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**8** 



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