# Bipolar Pre-Biased / Digital Transistor, Dual PNP, 50 V, 100 mA

![Product image](https://novapart.co/image/farnell:3617159/)

**URL**: https://novapart.co/products/NSBA114EDP6T5G/bipolar-pre-biased-digital-transistor-dual-pnp-50
**SKU**: NSBA114EDP6T5G
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || Transistors || Bipolar Transistors || Pre-Biased / Digital Bipolar Transistors
**Price**: €0.0420
**Stock**: 10+
**Lead Time**: 113 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 6 Pin |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 408mW |
| Transistor Mounting | Surface Mount |
| Transistor Polarity | Dual PNP |
| Transistor Case Style | SOT-963 |
| Base Input Resistor R1 | - |
| Dc Current Gain Hfe Min | 35hFE |
| Base Emitter Resistor R2 | - |
| Operating Temperature Max | 150°C |
| Continuous Collector Current | 100mA |
| Collector Emitter Voltage Max Npn | - |
| Collector Emitter Voltage Max Pnp | 50V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3617159/)

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## Dual PNP Bias Resistor Transistors R1 = 10 k R2 = 10 k 

**PNP Transistors with Monolithic Bias Resistor Network** 

## MUN5111DW1, NSBA114EDXV6, NSBA114EDP6 

This series of digital transistors is designed to replace a single device and its external resistor bias network. The Bias Resistor Transistor (BRT) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base−emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can reduce both system cost and board space. 

## **Features** 

- Simplifies Circuit Design 

- Reduces Board Space 

- Reduces Component Count 

- S and NSV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q101 Qualified and PPAP Capable* 

- These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant 

## **MAXIMUM RATINGS** 

(TA = 25C, common for Q1 and Q2, unless otherwise noted) 

|**Rating**|**Symbol**|**Max**|**Unit**|
|---|---|---|---|
|Collector−Base Voltage|VCBO|50|Vdc|
|Collector−Emitter Voltage|VCEO|50|Vdc|
|Collector Current − Continuous|IC|100|mAdc|
|Input Forward Voltage|VIN(fwd)|40|Vdc|
|Input Reverse Voltage|VIN(rev)|10|Vdc|



## **PIN CONNECTIONS** 

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(3) (2) (1)<br>R1 R2<br>Q1<br>Q2<br>R2<br>R1<br>(4) (5) (6)<br>**----- End of picture text -----**<br>


## **MARKING DIAGRAMS** 

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**----- Start of picture text -----**<br>
6<br>SOT−363<br>0A M<br>CASE 419B<br>1<br>SOT−563<br>0A  M  CASE 463A<br>1<br>SOT−963<br> M  CASE 527AD<br>e 1<br>0A/F = Specific Device Code<br>M = Date Code*<br>= Pb−Free Package<br>(Note: Microdot may be in either location)<br>F<br>**----- End of picture text -----**<br>


*Date Code orientation may vary depending upon manufacturing location. 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information on page 2 of this data sheet. 

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

Publication Order Number: **DTA114ED/D** 

**1** 

 Semiconductor Components Industries, LLC, 2014 **June, 2024 − Rev. 4** 

**MUN5111DW1, NSBA114EDXV6, NSBA114EDP6** 

**ORDERING INFORMATION** 

|**Device**<br>~~———~~|**Package**<br>~~———~~|**Shipping**†<br>~~———~~|
|---|---|---|
|MUN5111DW1T1G, SMUN5111DW1T1G*<br>~~———~~|SOT−363<br>~~———~~|3,000 / Tape & Reel<br>~~———~~|
|NSVMUN5111DW1T3G*<br>~~———~~|SOT−363<br>~~———~~|10,000 / Tape & Reel<br>~~———~~|
|NSBA114EDXV6T1G,<br>NSVBA114EDXV6T1G*<br>~~———~~|SOT−563<br>~~———~~|4,000 / Tape & Reel<br>~~———~~|
|NSBA114EDP6T5G<br>~~———~~|SOT−963<br>~~———~~|8,000 / Tape & Reel<br>~~———~~|



## **THERMAL CHARACTERISTICS** 

|||**Characteristic**|**Symbol**|**Max**|**Unit**|
|---|---|---|---|---|---|
||**MUN5111DW1 (SOT−363) One Junction Heated**|||||
||Total Device Dissipation||PD|||
||TA= 25C|(Note 1)||187|mW|
|||(Note 2)||256||
||Derate above 25C|(Note 1)||1.5|mW/C|
|||(Note 2)||2.0||
||Thermal Resistance,|(Note 1)|R JA|670|C/W|
||Junction to Ambient|(Note 2)||490||
||**MUN5111DW1 (SOT−363) Both Junction Heated**(Note 3)|||||
||Total Device Dissipation||PD|||
||TA= 25C|(Note 1)||250|mW|
|||(Note 2)||385||
||Derate above 25C|(Note 1)||2.0|mW/C|
|||(Note 2)||3.0||
||Thermal Resistance,|(Note 1)|R JA|493|C/W|
||Junction to Ambient|(Note 2)||325||
||Thermal Resistance,|(Note 1)|R JL|188|C/W|
||Junction to Lead|(Note 2)||208||
||Junction and Storage Temperature Range||TJ, Tstg|−55 to +150|C|
||**NSBA114EDXV6 (SOT−563) One Junction Heated**|||||
||Total Device Dissipation||PD|||
||TA= 25C|(Note 1)||357|mW|
||Derate above 25C|(Note 1)||2.9|mW/C|
||Thermal Resistance,||R JA||C/W|
||Junction to Ambient|(Note 1)||350||
||**NSBA114EDXV6 (SOT−563) Both Junction Heated**(Note 3)|||||
|Total Device Dissipation<br>TA= 25C<br>(Note 1)<br>Derate above 25C<br>(Note 1)<br>PD<br>500<br>4.0<br>mW<br>mW/C<br>Thermal Resistance,<br>Junction to Ambient<br>(Note 1)<br>R JA<br>250<br>C/W<br>Junction and Storage Temperature Range<br>TJ, Tstg<br>−55 to +150<br>C<br>**NSBA114EDP6 (SOT−963) One Junction Heated**<br>Total Device Dissipation<br>TA= 25C<br>(Note 4)<br>(Note 5)<br>Derate above 25C<br>(Note 4)<br>(Note 5)<br>PD<br>231<br>269<br>1.9<br>2.2<br>mW<br>mW/C<br>Thermal Resistance,<br>(Note 4)<br>Junction to Ambient<br>(Note 5)<br>R JA<br>540<br>464<br>C/W<br>~~SS~~||||||
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**MUN5111DW1, NSBA114EDXV6, NSBA114EDP6** 

## **THERMAL CHARACTERISTICS** 

|**NSBA114EDP6 (SOT−963) Both Junction Heated**(Note 3)||||
|---|---|---|---|
|Total Device Dissipation<br>TA= 25C<br>(Note 4)<br>(Note 5)<br>Derate above 25C<br>(Note 4)<br>(Note 5)|PD|339<br>408<br>2.7<br>3.3|mW<br>mW/C|
|Thermal Resistance,<br>(Note 4)<br>Junction to Ambient<br>(Note 5)|R JA|369<br>306|C/W|
|Junction and Storage Temperature Range<br>~~a~~|TJ, Tstg<br>~~a~~|−55 to +150<br>~~a~~|C<br>~~a~~|



1. FR−4 @ Minimum Pad. 

2. FR−4 @ 1.0 x 1.0 Inch Pad. 

3. Both junction heated values assume total power is sum of two equally powered channels. 

4. FR−4 @ 100 mm[2] , 1 oz. copper traces, still air. 

5. FR−4 @ 500 mm[2] , 1 oz. copper traces, still air. 

**ELECTRICAL CHARACTERISTICS** (TA = 25C, common for Q1 and Q2, unless otherwise noted) 

|**Characteristic**<br>**Symbol**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>**OFF CHARACTERISTICS**<br>~~ee~~|
|---|
|Collector−Base Cutoff Current<br>(VCB= 50 V, IE= 0)<br>ICBO<br>−<br>−<br>100<br>nAdc<br>Collector−Emitter Cutoff Current<br>(VCE= 50 V, IB= 0)<br>ICEO<br>−<br>−<br>500<br>nAdc<br>Emitter−Base Cutoff Current<br>(VEB= 6.0 V, IC= 0)<br>IEBO<br>−<br>−<br>0.5<br>mAdc<br>Collector−Base Breakdown Voltage<br>(IC= 10 A, IE= 0)<br>V(BR)CBO<br>50<br>−<br>−<br>Vdc<br>Collector−Emitter Breakdown Voltage (Note 6)<br>(IC= 2.0 mA, IB= 0)<br>V(BR)CEO<br>50<br>−<br>−<br>Vdc<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ee ee~~<br>~~ee~~<br>~~ee~~<br>~~Ds~~|
|**ON CHARACTERISTICS**|
|DC Current Gain (Note 6)<br>(IC= 5.0 mA, VCE= 10 V)<br>hFE<br>35<br>60<br>−<br>Collector−Emitter Saturation Voltage (Note 6)<br>(IC= 10 mA, IB= 0.3 mA)<br>VCE(sat)<br>−<br>−<br>0.25<br>Vdc<br>Input Voltage (off)<br>(VCE= 5.0 V, IC= 100 A)<br>Vi(off)<br>−<br>1.2<br>−<br>Vdc<br>Input Voltage (on)<br>(VCE= 0.2 V, IC= 10 mA)<br>Vi(on)<br>−<br>2.2<br>−<br>Vdc<br>Output Voltage (on)<br>(VCC= 5.0 V, VB= 2.5 V, RL= 1.0 k )<br>VOL<br>−<br>−<br>0.2<br>Vdc<br>Output Voltage (off)<br>(VCC= 5.0 V, VB= 0.5 V, RL= 1.0 k )<br>VOH<br>4.9<br>−<br>−<br>Vdc<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~|
|Input Resistor<br>R1<br>7.0<br>10<br>13<br>k<br>Resistor Ratio<br>R1/R2<br>0.8<br>1.0<br>1.2<br>Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product<br>~~Gs~~<br>~~a~~<br>~~G~~|
|performance may not be indicated by the Electrical Characteristics if operated under different conditions.|



6. Pulsed Condition: Pulse Width = 300 msec, Duty Cycle  2%. 

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**MUN5111DW1, NSBA114EDXV6, NSBA114EDP6** 

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400<br>350 pot ft tt | dt<br>300 PN<br>250<br>200<br>Sa A NN<br>(1) (2) (3)<br>150<br>100<br>ee eeNN<br>Ne<br>500 eee<br>−50 −25 0 25 50 75 100 125 150<br>AMBIENT TEMPERATURE (C)<br>, POWER DISSIPATION (mW)<br>D<br>P<br>**----- End of picture text -----**<br>


- (1) SOT−363; 1.0 x 1.0 inch Pad (2) SOT−563; Minimum Pad (3) SOT−963; 100 mm[2] , 1 oz. copper trace 

**Figure 1. Derating Curve** 

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**MUN5111DW1, NSBA114EDXV6, NSBA114EDP6** 

## **TYPICAL CHARACTERISTICS MUN5111DW1, NSBA114EDXV6** 

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1 1000<br>I C /I B = 10 V CE  = 10 V<br>_ J aotRS | |asid [<br>T A = −25C<br>++),a 75 TAR C 25C ee ee eee TA = 75C<br>0.1 | |err= JF | | 100 TtTPTIeo e −25C<br>EE —— a ee 25  C<br>Lr Tt(tC Cr er<br>0.01 10<br>0 20 40 60 80 1 10 100<br>IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)<br>Figure 2. VCE(sat) vs. IC Figure 3. DC Current Gain<br>109 f = 10 kHz 100 —_ 75C SS 25C SS SS SS<br>lE = 0 A T A  = −25C<br>8 | a T A  = 25  C 10 ee /7c<br>7<br>6 1<br>5 KEOt i‘é‘d Ca— EES)ff<br>4<br>0.1<br>yoo ee<br>3<br>2<br>0.01<br>1 ASE VO = 5 V<br>0 a 0.001 === eee<br>0 10 20 30 40 50 0 1 2 3 4 5 6 7 8 9 10<br>VR, REVERSE VOLTAGE (V) Vin, INPUT VOLTAGE (V)<br>VOLTAGE (V)<br>, COLLECTOR−EMITTER , DC CURRENT GAIN<br>FE<br>h<br>CE(sat)<br>V<br>, OUTPUT CAPACITANCE (pF)Cob , COLLECTOR CURRENT (mA)IC<br>**----- End of picture text -----**<br>


**Figure 4. Output Capacitance** 

**Figure 5. Output Current vs. Input Voltage** 

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100 a|<br>VO = 0.2 V<br>2———<br>sses eses |<br>10 T A = −25C<br>25C<br>75C<br>——ee eee [|<br>1 a |<br>ee|<br>eS<br>Es es<br>0.1 es es<br>0 10 20 30 40 50<br>IC, COLLECTOR CURRENT (mA)<br>, INPUT VOLTAGE (V)<br>in<br>V<br>**----- End of picture text -----**<br>


**Figure 6. Input Voltage vs. Output Current** 

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**MUN5111DW1, NSBA114EDXV6, NSBA114EDP6** 

## **TYPICAL CHARACTERISTICS NSBA114EDP6** 

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**----- Start of picture text -----**<br>
1 1000<br>IC/IB = 10 25  C<br>= ———_—— J} = ot<br>a $$ Ht 4 Hat 150  C H<br>PF 25 {| C | | 150 | C | | ft | 100 | ee −55C mS<br>0.1 |_| —_—— _ | + SSSPtBtae SS<br>= SS | — ALA<br>a LA<br>—_—————— 10 alll<br>−55 ges C pooes aSa ee<br>Fo | | | | ft ft ft] A FF TTT<br>0.01 a 1 V CE = 10 V<br>0 10 20 30 40 50 0.1 1 10 100<br>IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)<br>Figure 7. VCE(sat) vs. IC Figure 8. DC Current Gain<br>7 100<br>f = 10 kHz 150C<br>6 IE = 0 A −55C<br>TA = 25C<br>10<br>5<br><br>H | | | | | tT SS 2 ES 25 C<br>4 Yo | | | ff ft t—f-f— FFfi es<br>he 1 | iff] hf [CTT]<br>3<br>SOE ee<br>2<br>0.1<br>Os Lf iff {|_| _| _| _| _|__|<br>1 ee ee ee ee == ———<br>V O  = 5 V<br>0 a 0.01 ee|; ye | | | ft<br>0 10 20 30 40 50 0 1 2 3 4 5 6 7 8<br>VR, REVERSE VOLTAGE (V) Vin, INPUT VOLTAGE (V)<br>VOLTAGE (V)<br>, COLLECTOR−EMITTER , DC CURRENT GAIN<br>FE<br>h<br>CE(sat)<br>V<br>, OUTPUT CAPACITANCE (pF) , COLLECTOR CURRENT (mA)<br>Cob IC<br>**----- End of picture text -----**<br>


**Figure 9. Output Capacitance** 

**Figure 10. Output Current vs. Input Voltage** 

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**----- Start of picture text -----**<br>
100 SSS SSS55<br>ee<br>a|<br>a<br>10 25C<br>CE<br>= _————————— −55C ————<br>pTa=o—  eeee—eem ee—————e e e eee eee<br>ee<br>1 150C<br>2SeaeeSS SS S =S SSS|<br>V O  = 0.2 V<br>0.1 —>44-+-+- |<br>0 10 20 30 40 50<br>IC, COLLECTOR CURRENT (mA)<br>, INPUT VOLTAGE (V)<br>in<br>V<br>**----- End of picture text -----**<br>


**Figure 11. Input Voltage vs. Output Current** 

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MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

## **SC−88 2.00x1.25x0.90, 0.65P** CASE 419B−02 ISSUE Z 

## DATE 18 APR 2024 

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GENERIC<br>MARKING DIAGRAM*<br>6<br>io o<br>XXXM<br>1 UU U<br>XXX = Specific Device Code<br>M = Date Code*<br>: = Pb−Free Package<br>(Note: Microdot may be in either location)<br>*Date Code orientation and/or position may<br>vary depending upon manufacturing location.<br>**----- End of picture text -----**<br>


*This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ : ”, may or may not be present. Some products may not follow the Generic Marking. 

## **STYLES ON PAGE 2** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

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DOCUMENT NUMBER: 98ASB42985B<br>**----- End of picture text -----**<br>


## **SC−88 2.00x1.25x0.90, 0.65P** 

## **PAGE 1 OF 2** 

## 

## **DESCRIPTION:** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba onsemi. **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

 Semiconductor Components Industries, LLC, 2019 

## **SC−88 2.00x1.25x0.90, 0.65P** CASE 419B−02 ISSUE Z 

## DATE 18 APR 2024 

|STYLE 1:|STYLE 2:|STYLE 3:|STYLE 4:|STYLE 5:|STYLE 6:|
|---|---|---|---|---|---|
|PIN 1. EMITTER 2|CANCELLED|CANCELLED|PIN 1. CATHODE|PIN 1. ANODE|PIN 1. ANODE 2|
|2. BASE 2|||2. CATHODE|2. ANODE|2. N/C|
|3. COLLECTOR 1|||3. COLLECTOR|3. COLLECTOR|3. CATHODE 1|
|4. EMITTER 1|||4. EMITTER|4. EMITTER|4. ANODE 1|
|5. BASE 1|||5. BASE|5. BASE|5. N/C|
|6. COLLECTOR 2|||6. ANODE|6. CATHODE|6. CATHODE 2|
|STYLE 7:|STYLE 8:|STYLE 9:|STYLE 10:|STYLE 11:|STYLE 12:|
|PIN 1. SOURCE 2|CANCELLED|PIN 1. EMITTER 2|PIN 1. SOURCE 2|PIN 1. CATHODE 2|PIN 1. ANODE 2|
|2. DRAIN 2||2. EMITTER 1|2. SOURCE 1|2. CATHODE 2|2. ANODE 2|
|3. GATE 1||3. COLLECTOR 1|3. GATE 1|3. ANODE 1|3. CATHODE 1|
|4. SOURCE 1||4. BASE 1|4. DRAIN 1|4. CATHODE 1|4. ANODE 1|
|5. DRAIN 1||5. BASE 2|5. DRAIN 2|5. CATHODE 1|5. ANODE 1|
|6. GATE 2||6. COLLECTOR 2|6. GATE 2|6. ANODE 2|6. CATHODE 2|
|STYLE 13:|STYLE 14:|STYLE 15:|STYLE 16:|STYLE 17:|STYLE 18:|
|PIN 1. ANODE|PIN 1. VREF|PIN 1. ANODE 1|PIN 1. BASE 1|PIN 1. BASE 1|PIN 1. VIN1|
|2. N/C|2. GND|2. ANODE 2|2. EMITTER 2|2. EMITTER 1|2. VCC|
|3. COLLECTOR|3. GND|3. ANODE 3|3. COLLECTOR 2|3. COLLECTOR 2|3. VOUT2|
|4. EMITTER|4. IOUT|4. CATHODE 3|4. BASE 2|4. BASE 2|4. VIN2|
|5. BASE|5. VEN|5. CATHODE 2|5. EMITTER 1|5. EMITTER 2|5. GND|
|6. CATHODE|6. VCC|6. CATHODE 1|6. COLLECTOR 1|6. COLLECTOR 1|6. VOUT1|
|STYLE 19:|STYLE 20:|STYLE 21:|STYLE 22:|STYLE 23:|STYLE 24:|
|PIN 1. I OUT|PIN 1. COLLECTOR|PIN 1. ANODE 1|PIN 1. D1 (i)|PIN 1. Vn|PIN 1. CATHODE|
|2. GND|2. COLLECTOR|2. N/C|2. GND|2. CH1|2. ANODE|
|3. GND|3. BASE|3. ANODE 2|3. D2 (i)|3. Vp|3. CATHODE|
|4. V CC|4. EMITTER|4. CATHODE 2|4. D2 (c)|4. N/C|4. CATHODE|
|5. V EN|5. COLLECTOR|5. N/C|5. VBUS|5. CH2|5. CATHODE|
|6. V REF|6. COLLECTOR|6. CATHODE 1|6. D1 (c)|6. N/C|6. CATHODE|
|STYLE 25:|STYLE 26:|STYLE 27:|STYLE 28:|STYLE 29:|STYLE 30:|
|PIN 1. BASE 1|PIN 1. SOURCE 1|PIN 1. BASE 2|PIN 1. DRAIN|PIN 1. ANODE|PIN 1. SOURCE 1|
|2. CATHODE|2. GATE 1|2. BASE 1|2. DRAIN|2. ANODE|2. DRAIN 2|
|3. COLLECTOR 2|3. DRAIN 2|3. COLLECTOR 1|3. GATE|3. COLLECTOR|3. DRAIN 2|
|4. BASE 2|4. SOURCE 2|4. EMITTER 1|4. SOURCE|4. EMITTER|4. SOURCE 2|
|5. EMITTER|5. GATE 2|5. EMITTER 2|5. DRAIN|5. BASE/ANODE|5. GATE 1|
|6. COLLECTOR 1|6. DRAIN 1|6. COLLECTOR 2|6. DRAIN|6. CATHODE|6. DRAIN 1|



Note: Please refer to datasheet for style callout. If style type is not called out in the datasheet refer to the device datasheet pinout or pin assignment. 

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Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>DOCUMENT NUMBER: 98ASB42985B Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.<br>DESCRIPTION: SC−88 2.00x1.25x0.90, 0.65P PAGE 2 OF 2<br>**----- End of picture text -----**<br>


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MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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SOT−563−6 1.60x1.20x0.55, 0.50P<br>CASE 463A<br>ISSUE J<br>DATE 15 FEB 2024<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
GENERIC<br>MARKING DIAGRAM*<br>S T YL E 7: S T YL E 8 S T YL E 9:<br>P I N 1. C ATH OD E P I N 1 , DR AI N P I N 1 , SOURC E 1 O55<br>2, A NOD E 2, DR AI N 2, G ATE 1<br>XXM<br>3. C ATH OD E 3. G ATE 3, DR AI N 2<br>4. C ATH OD E 4. SOURC E 4. SOURC E 2 1<br>5, A NOD E 5, DR AI N 5, G ATE 2 —<br>6. C ATH OD E 6. DR AI N 6. DR AI N 1 XX = Specific Device Code<br>M = Month Code<br>. = Pb−Free Package<br>S T YL E 1 0: S T YL E 1<br>P I N 1 . C ATH OD E 1 P I N 1 . E M ITTE R 2 *This information is generic. Please refer to<br>2, N/C 2, B A S E 2 device data sheet for actual part marking.<br>3. C ATH OD E 2 3, COLL E C T OR 1 Pb−Free indicator, “G” or microdot “ . ”, may<br>5.4. N/C A NOD E 2 4.5. E BM AITTE S E 1 R 1 or may not be present. Some products may<br>6. A NOD E 1 6. COLL E C T OR 2 not follow the Generic Marking.<br>Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>DOCUMENT NUMBER: 98AON11126D Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.<br>DESCRIPTION: SOT−563−6 1.60x1.20x0.55, 0.50P PAGE 1 OF 1<br>**----- End of picture text -----**<br>


**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

## **SOT−963 1.00x1.00x0.37, 0.35P** CASE 527AD ISSUE F 

## DATE  20 FEB 2024 

- STYLE 1: STYLE 2: STYLE 3: PIN 1. EMITTER 1 PIN 1. EMITTER 1 PIN 1. CATHODE 1 2. BASE 1 2. EMITTER2 2. CATHODE 1 3. COLLECTOR 2 3. BASE 2 3. ANODE/ANODE 2 4. EMITTER 2 4. COLLECTOR 2 4. CATHODE 2 5. BASE 2 5. BASE 1 5. CATHODE 2 6. COLLECTOR 1 6. COLLECTOR 1 6. ANODE/ANODE 1 

- STYLE 4: STYLE 5: STYLE 6: PIN 1. COLLECTOR PIN 1. CATHODE PIN 1. CATHODE 2. COLLECTOR 2. CATHODE 2. ANODE 3. BASE 3. ANODE 3. CATHODE 4. EMITTER 4. ANODE 4. CATHODE 5. COLLECTOR 5. CATHODE 5. CATHODE 6. COLLECTOR 6. CATHODE 6. CATHODE 

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GENERIC<br>MARKING DIAGRAM*<br>XXM<br>1<br>XX = Specific Device Code<br>M = Month Code<br>**----- End of picture text -----**<br>


STYLE 9: 

STYLE 7: STYLE 8: STYLE 9: PIN 1. CATHODE PIN 1. DRAIN PIN 1. SOURCE 1 2. ANODE 2. DRAIN 2. GATE 1 3. CATHODE 3. GATE 3. DRAIN 2 4. CATHODE 4. SOURCE 4. SOURCE 2 5. ANODE 5. DRAIN 5. GATE 2 6. CATHODE 6. DRAIN 6. DRAIN 1 

- STYLE 10: PIN 1. CATHODE 1 2. N/C 3. CATHODE 2 

*This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ ”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

4. ANODE 2 5. N/C 6. ANODE 1 

## **DOCUMENT NUMBER: 98AON26456D** 

**DESCRIPTION: SOT−963 1.00x1.00x0.37, 0.35P** 

**PAGE 1 OF 1** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2008 

**onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** ’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

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**==> picture [232 x 43] intentionally omitted <==**

 



## Links

- [View this product on Novapart](https://novapart.co/products/NSBA114EDP6T5G/bipolar-pre-biased-digital-transistor-dual-pnp-50)
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- [Supplier page](https://es.farnell.com/on-semiconductor/nsba114edp6t5g/digital-transistor-50v-0-1a/dp/3617159)
---

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