# Power MOSFET, N Channel, 52 V, 9 A, 0.09 ohm, TO-252 (DPAK), Surface Mount ![Product image](https://novapart.co/image/farnell:3463986RL/) **URL**: https://novapart.co/products/NID9N05BCLT4G/power-mosfet-n-channel-52-v-9-a-009-ohm-to-252 **SKU**: NID9N05BCLT4G **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.4530 **Stock**: 10+ ## Specifications | Parameter | Value | |---|---| | Channel Type | N Channel | | Qualification | AEC-Q101 | | Power Dissipation | 1.74W | | Drain Source On State Resistance | 0.09ohm | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:3463986RL/) ## NID9N05ACL, NID9N05BCL ## Power MOSFET ## **9.0 A, 52 V, N−Channel, Logic Level, Clamped MOSFET w/ESD Protection in a DPAK Package** ## **www.onsemi.com** ## **Benefits** **==> picture [190 x 205] intentionally omitted <==** **----- Start of picture text -----**
VDSS ID MAX
(Clamped) RDS(ON) TYP (Limited)
52 V 90 m 9.0 A
eeee ee
Drain
(Pins 2, 4)
Overvoltage MPWR
Gate
Protection
(Pin 1) RG
ESD Protection
Source
(Pin 3)
**----- End of picture text -----**
- High Energy Capability for Inductive Loads - Low Switching Noise Generation ## **Features** - Diode Clamp Between Gate and Source - ESD Protection − HBM 5000 V - Active Over−Voltage Gate to Drain Clamp - Scalable to Lower or Higher RDS(on) - Internal Series Gate Resistance - AEC−Q101 Qualified and PPAP Capable - These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant ## **Applications** - Automotive and Industrial Markets: Solenoid Drivers, Lamp Drivers, Small Motor Drivers **MARKING DIAGRAM** ## **MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) **Rating Symbol Value Unit** Drain−to−Source Voltage Internally Clamped VDSS 52−59 V 1 YWW Gate−to−Source Voltage − Continuous VGS ± 15 V **DPAK** 2 D9N 4 Drain Current − Continuous @ TA = 25 ° C ID 9.0 A **CASE 369C** 3 xxxxxG Drain Current − Single Pulse (tp = 10 s) IDM 35 **STYLE 2** ~~a c~~ m ~~)~~ Total Power Dissipation @ TA = 25 ° C PD 1.74 W Operating and Storage Temperature Range TJ, Tstg −55 to 175 ° C YWW = Work Week= Year 12 = Drain= Gate ~~ee~~ Single Pulse Drain−to−Source Avalanche EAS 160 mJ xxxxx = 05ACL or 05BCL 3 = Source Energy − Starting TJ = 125 ° C G = Pb−Free Package 4 = Drain (VDD = 50 V, ID(pk) = 1.5 A, VGS = 10 V, RG = 25 ) ~~Pe.~~ Thermal Resistance, Junction−to−Case ~~ULL~~ R JC 5.2 ° C/W **ORDERING INFORMATION** Junction−to−Ambient (Note 1) R JA 72 ~~PE~~ Junction−to−Ambient (Note 2) R JA 100 **Device Package Shipping**[[†]] Maximum Lead Temperature for SolderingPurposes, 1/8 ″ from Case for 10 seconds TL 260 ° C NID9N05ACLT4G DPAK 2500/Tape & Reel (Pb−Free) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be NID9N05BCLT4G DPAK 2500/Tape & Reel assumed, damage may occur and reliability may be affected. (Pb−Free) ~~ee~~ ″ ~~=~~ 1. When surface mounted to a FR4 board using 1 pad size, (Cu area 1.127 in[2] ). 2. When surface mounted to a FR4 board using minimum recommended pad †For information on tape and reel specifications, including part orientation and tape sizes, please size, (Cu area 0.412 in[2] ). **Device Package Shipping**[[†]] NID9N05ACLT4G DPAK 2500/Tape & Reel (Pb−Free) NID9N05BCLT4G DPAK 2500/Tape & Reel (Pb−Free) ~~=~~ †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: **1** © Semiconductor Components Industries, LLC, 2016 **November, 2016 − Rev. 11** **NID9N05CL/D** ## **NID9N05ACL, NID9N05BCL** ## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) |**ELECTRICAL CHARACTERISTICS**(TJ= 25°C unless otherwise noted|**ELECTRICAL CHARACTERISTICS**(TJ= 25°C unless otherwise noted|)||||| |---|---|---|---|---|---|---| |**Characteristic**||**Symbol**|**Min**|**Typ**|**Max**|**Unit**| |**OFF CHARACTERISTICS**||||||| |Drain−to−Source Breakdown Voltage (Note 3)
(VGS= 0 V, ID= 1.0 mA, TJ= 25°C)
(VGS= 0 V, ID= 1.0 mA, TJ= −40°C to 125°C)
Temperature Coefficient (Negative)||V(BR)DSS|52
50.8
−|55
54
−10|59
59.5
−|V
V
mV/°C| |Zero Gate Voltage Drain Current
(VDS= 40 V, VGS= 0 V)
(VDS= 40 V, VGS= 0 V, TJ= 125°C)||IDSS|−
−|−
−|10
25|�A| |Gate−Body Leakage Current
(VGS=±8 V, VDS= 0 V)
(VGS=±14 V, VDS= 0 V)||IGSS|−
−|−
±22|±10
−|�A| |**ON CHARACTERISTICS**(Note 3)||||||| |Gate Threshold Voltage (Note 3)
(VDS= VGS, ID= 100�A)
Threshold Temperature Coefficient (Negative)||VGS(th)|1.3
−|1.75
−4.5|2.5
−|V
mV/°C| |Static Drain−to−Source On−Resistance (Note 3)
(VGS= 4.0 V, ID= 1.5 A)
(VGS= 3.5 V, ID= 0.6 A)
(VGS= 3.0 V, ID= 0.2 A)
(VGS= 12 V, ID= 9.0 A)
(VGS= 12 V, ID= 12 A)||RDS(on)|−
−
−
70
67|153
175
−
90
95|181
364
1210
−
−|m�| |Forward Transconductance (Note 3) (VDS= 15 V, ID= 9.0 A)||gFS|−|24|−|Mhos| |**DYNAMIC CHARACTERISTICS**||||||| |Input Capacitance|(VDS= 40 V, VGS= 0 V, f = 10 kHz)|Ciss|−|155|250|pF| |Output Capacitance||Coss|−|60|100|| |Transfer Capacitance||Crss|−|25|40|| |Input Capacitance|(VDS= 25 V, VGS= 0 V, f = 10 kHz)|Ciss|−|175|−|pF| |Output Capacitance||Coss|−|70|−|| |Transfer Capacitance||Crss|−|30|−|| |**SWITCHING CHARACTERISTICS**(Note 4)||||||| |Turn−On Delay Time|(VGS= 10 V, VDD= 40 V,
ID= 9.0 A, RG= 9.0�)|td(on)|−|130|200|ns| |Rise Time||tr|−|500|750|| |Turn−Off Delay Time||td(off)|−|1300|2000|| |Fall Time||tf|−|1150|1850|| |Turn−On Delay Time|(VGS= 10 V, VDD= 15 V,
ID= 1.5 A, RG= 2 k�)|td(on)|−|200|−|ns| |Rise Time||tr|−|500|−|| |Turn−Off Delay Time||td(off)|−|2500|−|| |Fall Time||tf|−|1800|−|| |Turn−On Delay Time|(VGS= 10 V, VDD= 15 V,
ID= 1.5 A, RG= 50�)|td(on)|−|120|−|ns| |Rise Time||tr|−|275|−|| |Turn−Off Delay Time||td(off)|−|1600|−|| |Fall Time||tf|−|1100|−|| |Gate Charge|(VGS= 4.5 V, VDS= 40 V,
ID= 9.0 A) (Note 3)|QT|−|4.5|7.0|nC| |||Q1|−|1.2|−|| |||Q2|−|2.7|−|| Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. **www.onsemi.com** **2** ## **NID9N05ACL, NID9N05BCL** ## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) |**ELECTRICAL CHARACTERISTICS**(TJ= 25°C unless otherwise noted|**ELECTRICAL CHARACTERISTICS**(TJ= 25°C unless otherwise noted|)||||| |---|---|---|---|---|---|---| |**Characteristic**||**Symbol**|**Min**|**Typ**|**Max**|**Unit**| |**SWITCHING CHARACTERISTICS**(Note 4)||||||| |Gate Charge|(VGS= 4.5 V, VDS= 15 V,
ID= 1.5 A) (Note 3)|QT|−|3.6|−|nC| |||Q1|−|1.0|−|| |||Q2|−|2.0|−|| |**SOURCE−DRAIN DIODE CHARACTERISTICS**||||||| |Forward On−Voltage|(IS= 4.5 A, VGS= 0 V) (Note 3)
(IS= 4.0 A, VGS= 0 V)
(IS= 4.5 A, VGS= 0 V, TJ= 125°C)|VSD|−
−
−|0.86
0.845
0.725|1.2
−
−|V| |Reverse Recovery Time|(IS= 4.5 A, VGS= 0 V,
dIs/dt = 100 A/�s) (Note 3)|trr|−|700|−|ns| |||ta|−|200|−|| |||tb|−|500|−|| |Reverse Recovery Stored Charge||QRR|−|6.5|−|�C| |**ESD CHARACTERISTICS**||||||| |Electro−Static Discharge
Capability|Human Body Model (HBM)|ESD|5000|−|−|V| ||Machine Model (MM)||500|−|−|| Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. **www.onsemi.com** **3** **NID9N05ACL, NID9N05BCL** ## **TYPICAL PERFORMANCE CURVES** **==> picture [238 x 158] intentionally omitted <==** **----- Start of picture text -----**
18
VGS = 10 V 6 V
16 T J = 25 ° C
8 V
14
6.5 V 5 V
12
4.6 V
10
4.2 V
8
4 V
6 3.8 V
3.2 V
4 3.4 V
2
2.8 V
0
0 1 2 3 4 5 6 7 8
, DRAIN CURRENT (AMPS)
ID
**----- End of picture text -----**
**==> picture [171 x 9] intentionally omitted <==** **----- Start of picture text -----**
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
**----- End of picture text -----**
**Figure 1. On−Region Characteristics** **==> picture [231 x 158] intentionally omitted <==** **----- Start of picture text -----**
18
16 T J = −55 ° C
14
TJ = 25 ° C TJ = 100 ° C
12
10
8
6
4
2 V DS ≥ 10 V
0
1 2 3 4 5 6 7 8 9
, DRAIN CURRENT (AMPS)
ID
**----- End of picture text -----**
**==> picture [168 x 9] intentionally omitted <==** **----- Start of picture text -----**
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
**----- End of picture text -----**
**Figure 2. Transfer Characteristics** **==> picture [488 x 436] intentionally omitted <==** **----- Start of picture text -----**
0.5 0.4
0.4 T ID J = 4.5 A = 25 ° C 0.35 VGS = 4 V TJ = 25 ° C
0.3
0.25
0.3
0.2
0.2
0.15
VGS = 12 V
0.1
0.1
0.05
0 0
2 4 6 8 10 12 0 2 4 6 8 10 12 14 16 18
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Figure 4. On−Resistance versus Drain Current
Gate−to−Source Voltage and Gate Voltage
2.5 1,000,000
ID = 9 A VGS = 0 V
VGS = 12 V
2 100,000
TJ = 150 ° C
1.5 10,000
TJ = 100 ° C
1 1000
0.5 100
−50 −25 0 25 50 75 100 125 150 175 20 25 30 35 40 45 50
TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current
Temperature versus Voltage
) � ) �
, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (
DS(on) DS(on)
R R
, LEAKAGE (nA)
(NORMALIZED)
IDSS
, DRAIN−TO−SOURCE RESISTANCE
DS(on)
R
**----- End of picture text -----**
**www.onsemi.com** **4** **NID9N05ACL, NID9N05BCL** ## **TYPICAL PERFORMANCE CURVES** **==> picture [242 x 158] intentionally omitted <==** **----- Start of picture text -----**
500
Frequency = 10 kHz T J = 25 ° C
400 VGS = 0 V
300
200 C iss
100 Coss
Crss
0
0 10 20 30 40 50
C, CAPACITANCE (pF)
**----- End of picture text -----**
**==> picture [171 x 9] intentionally omitted <==** **----- Start of picture text -----**
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
**----- End of picture text -----**
**Figure 7. Capacitance Variation** **==> picture [490 x 403] intentionally omitted <==** **----- Start of picture text -----**
5 50 10,000
Q T
VDD = 40 V
4 40 ID = 9 A
VGS VGS = 10 V
Q gs Q gd
3 30 td(off)
1000
tf
2 20
ID = 9 A tr
VDS TJ = 25 ° C
1 10
td(on)
0 0 100
0 1 2 3 4 5 1 10 100
Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)
Figure 8. Gate−To−Source and Drain−To−Source Figure 9. Resistive Switching Time
Voltage versus Total Charge Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
10
VGS = 0 V
TJ = 25 ° C
8
6
4
2
0
0.4 0.6 0.8 1.0 1.2
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
V
DS
t, TIME (ns)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
IS, SOURCE CURRENT (AMPS)
**----- End of picture text -----**
**Figure 10. Diode Forward Voltage versus Current** **www.onsemi.com** **5** **NID9N05ACL, NID9N05BCL** ## **SAFE OPERATING AREA** The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 �s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(R�JC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. **==> picture [474 x 394] intentionally omitted <==** **----- Start of picture text -----**
100
V GS = 12 V 10 � s
SINGLE PULSE
TC = 25 ° C 100 � s
10
1 ms
10 ms
1 dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1 1 10 100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
1.0
D = 0.5
0.2
0.1 0.1 P(pk)
0.05 R � JC(t) = r(t) R � JC
D CURVES APPLY FOR POWER
0.01 PULSE TRAIN SHOWN
t1 READ TIME AT t1
t2 TJ(pk) − TC = P(pk) R � JC(t)
SINGLE PULSE DUTY CYCLE, D = t1/t2
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
t, TIME (s)
ID, DRAIN CURRENT (AMPS)
(NORMALIZED)
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
**----- End of picture text -----**
**Figure 12. Thermal Response** **www.onsemi.com** **6** **NID9N05ACL, NID9N05BCL** ## **PACKAGE DIMENSIONS** **DPAK (SINGLE GAUGE)** CASE 369C ISSUE F **==> picture [481 x 429] intentionally omitted <==** **----- Start of picture text -----**
NOTES:
A 1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
E C 2. CONTROLLING DIMENSION: INCHES.
A 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
b3 B c2 4. DIMENSIONS D AND E DO NOT INCLUDE MOLDMENSIONS b3, L3 and Z.
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
4 NOT EXCEED 0.006 INCHES PER SIDE.
L3 hie Z 5. DIMENSIONS D AND E ARE DETERMINED AT THE
D DETAIL A H 6. DATUMS A AND B ARE DETERMINED AT DATUMOUTERMOST EXTREMES OF THE PLASTIC BODY.
1 2 3 PLANE H.
7. OPTIONAL MOLD FEATURE.
L4 NOTE 7 DIM MININCHESMAX MILLIMETERSMIN MAX
b2 c BOTTOM VIEW A 0.086 0.094 2.18 2.38
e SIDE VIEW A1 0.000 0.005 0.00 0.13
b b 0.025 0.035 0.63 0.89
TOP VIEW 0.005 (0.13) M C b2b3 0.0280.180 0.0450.215 0.724.57 1.145.46
c 0.018 0.024 0.46 0.61
c2 0.018 0.024 0.46 0.61
H Z Z D 0.235 0.245 5.97 6.22
E 0.250 0.265 6.35 6.73
e 0.090 BSC 2.29 BSC
L2 [GAUGE] PLANE C SEATINGPLANE H 0.370 0.410 9.40 10.41
L 0.055 0.070 1.40 1.78
L1 0.114 REF 2.90 REF
L2 0.020 BSC 0.51 BSC
L L3 0.035 0.050 0.89 1.27
A1 BOTTOM VIEW L4 −−− 0.040 −−− 1.01
pip L1 e OO CONSTRUCTIONSALTERNATE Z 0.155 −−− 3.93 −−−
DETAIL A
ROTATED 9 CW
SOLDERING FOOTPRINT*
6.20 3.00
0.244 0.118
2.58
0.102
5.80
1.60 6.17
0.228
0.063 0.243
Te
SCALE 3:1 mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
**----- End of picture text -----**
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