# Power MOSFET, N Channel, 20 V, 1.3 A, 0.16 ohm, SuperSOT, Surface Mount

![Product image](https://novapart.co/image/farnell:1839006/)

**URL**: https://novapart.co/products/NDS331N/power-mosfet-n-channel-20-v-13-a-016-ohm-supersot
**SKU**: NDS331N
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.1500
**Stock**: 1000+
**Lead Time**: 104 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:1.3A; Drain Source Voltage Vds:20V; On Resistance Rds(on):0.11ohm; Rds(on) Test Voltage Vgs:4.5V; Threshold Voltage Vgs:700mV; Power

## Specifications

| Parameter | Value |
|---|---|
| Msl | - |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 500mW |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 4.5V |
| Transistor Case Style | SuperSOT |
| Drain Source Voltage Vds | 20V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 1.3A |
| Drain Source On State Resistance | 0.16ohm |
| Gate Source Threshold Voltage Max | 700mV |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:1839006/)

## N-Channel Logic Level Enhancement Mode Field Effect Transistor 

## NDS331N 

## **General Description** 

These N−Channel logic level enhancement mode power field effect transistors are produced using ON Semiconductor’s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on−state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast switching, and low in−line power loss are needed in a very small outline surface mount package. 

## **Features** 

- 1.3 A, 20 V 

   - ♦ RDS(on) = 0.21  @ VGS = 2.7 V 

   - ♦ RDS(on) = 0.16 @ VGS = 4.5 V 

- Industry Standard Outline SOT−23 Surface Mount Package Using Proprietary SUPERSOT −3 Design for Superior Thermal and Electrical Capabilities 

- High Density Cell Design for Extremely Low RDS(on) 

- Exceptional On−Resistance and Maximum DC Current Capability 

**www.onsemi.com** 

**==> picture [154 x 192] intentionally omitted <==**

**----- Start of picture text -----**<br>
D<br>G ><br>S<br>SOT−23/SUPERSOT−23, 3 LEAD, 1.4x2.9<br>CASE 527AG<br>MARKING DIAGRAM<br>Drain<br>3<br>331M<br>1 2<br>Gate Source<br>M = Date Code<br>**----- End of picture text -----**<br>


- This is a Pb−Free Device 

**==> picture [75 x 77] intentionally omitted <==**

**----- Start of picture text -----**<br>
D<br>G S<br>**----- End of picture text -----**<br>


**ORDERING INFORMATION Device Package Shipping**[†] NDS331N SOT−23−3/ 3000 / SUPERSOT−23 Tape & Reel (Pb−Free) ~~Tt~~ †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

Publication Order Number: **NDS331N/D** 

**1** 

© Semiconductor Components Industries, LLC, 2017 **May, 2021 − Rev. 7** 

**NDS331N** 

**ABSOLUTE MAXIMUM RATINGS** TA = 25 ° C unless otherwise noted. 

|**ABSOLUT**|**E MAXIMUM RATINGS**TA= 25°C unless otherwise noted.|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Ratings**|**Unit**|
|VDSS|Drain−Source Voltage|20|V|
|VGSS|Gate−Source Voltage − Continuous|±8|V|
|ID|Maximum Drain Current – Continuous (Note 1a)|1.3|A|
||Maximum Drain Current – Pulsed|10||
|PD|Maximum Power Dissipation (Note 1a)|0.5|W|
||Maximum Power Dissipation (Note 1b)|0.46||
|TJ, TSTG|Operating and Storage Temperature Range|−55 to +150|°C|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

## **THERMAL CHARACTERISTICS** 

|**THERMAL**|**CHARACTERISTICS**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Ratings**|**Unit**|
|R�JA|Thermal Resistance, Junction−to−Ambient (Note 1a)|250|°C/W|
|R�JC|Thermal Resistance, Junction−to−Case (Note 1)|75|°C/W|



1. R � JA is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R � JC is guaranteed by design while R � CA is determined by the user’s board design. 

TJ � TA TJ � TA PD(t) � R � JA(t) � R � JC � R � CA(t) � I[2] D[(t)][ �][R] DS(on)@TJ 

Typical R � JA using the board layouts shown below on 4.5 ″ x5 ″ FR−4 PCB in a still air environment: 

a) 250 ° C/W when mounted on a 0.02 in[2] pad of 2oz copper. 

b) 270 ° C/W when mounted on a 0.001 in[2] pad of 2oz copper. 

Scale 1:1 on letter size paper 

**www.onsemi.com** 

**2** 

**NDS331N** 

**ELECTRICAL CHARACTERISTICS** TA = 25 ° C unless otherwise noted. 

|**ELECTRI**|**CAL CHARACTERISTICS**TA= 25°|C unless otherwise noted.|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**|||||||
|BVDSS|Drain–Source Breakdown Voltage|VGS= 0 V, ID= 250�A|20|−|−|V|
|IDSS|Zero Gate Voltage Drain Current|VDS= 16 V, VGS= 0 V|−|−|1|�A|
|||VDS= 16 V, VGS= 0 V, TJ= 125°C|−|−|10||
|IGSSF|Gate–Body Leakage, Forward|VGS= 8 V, VDS= 0 V|−|−|100|nA|
|IGSSR|Gate–Body Leakage, Reverse|VGS= −8 V, VDS= 0 V|−|−|−100|nA|
|**ON CHARACTERISTICS**(Note 2)|||||||
|VGS(th)|Gate Threshold Voltage|VDS= VGS,ID= 250�A|0.5|0.7|1|V|
|||VDS= VGS,ID= 250�A, TJ= 125°C|0.3|0.53|0.8||
|RDS(on)|Static Drain–Source On–Resistance|VGS= 2.7 V, ID= 1.3 A|−|0.15|0.21|�|
|||VGS= 2.7 V, ID= 1.3 A, TJ= 125°C|−|0.24|0.4||
|||VGS= 4.5 V, ID= 1.5 A|−|0.11|0.16||
|ID(on)|On–State Drain Current|VGS= 2.7 V, VDS= 5 V|3|−|−|A|
|||VGS= 4.5 V, VDS= 5 V|4|−|−||
|gFS|Forward Transconductance|VDS= 5 V, ID= 1.3 A|−|3.5|−|S|
|**DYNAMIC**|**CHARACTERISTICS**||||||
|Ciss|Input Capacitance|VDS= 10 V, VGS= 0 V, f = 1.0 MHz|−|162|−|pF|
|Coss|Output Capacitance||−|85|−|pF|
|Crss|Reverse Transfer Capacitance||−|28|−|pF|
|**SWITCHING CHARACTERISTICS**(Note 2)|||||||
|tD(on)|Turn–On Delay Time|VDD= 5 V, ID= 1 A, VGS= 5 V,<br>RGEN= 6�|−|5|20|ns|
|tr|Turn–On Rise Time||−|25|40|ns|
|tD(off)|Turn–Off Delay Time||−|10|20|ns|
|tf|Turn–Off Fall Time||−|5|20|ns|
|Qg|Total Gate Charge|VDS= 5 V, ID= 1.3 A, VGS= 4.5 V|−|3.5|5|nC|
|Qgs|Gate–Source Charge||−|0.3|−|nC|
|Qgd|Gate–Drain Charge||−|1|−|nC|
|**DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS**|||||||
|IS|Maximum Continuous Drain–Source Diode Forward Current||−|−|0.42|A|
|ISM|Maximum Pulsed Drain−Source Diode Forward Current||−|−|10|A|
|VSD|Drain–Source Diode Forward Voltage|VGS= 0 V, IS= 0.42 A (Note 2)|−|0.8|1.2|V|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2.0%. 

**www.onsemi.com** 

**3** 

**NDS331N** 

## **TYPICAL ELECTRICAL CHARACTERISTICS** 

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**----- Start of picture text -----**<br>
4 1.75<br>VGS = 4.5 V<br>3.0 2.0<br>2.7<br>2.5 1.5<br>3<br>VGS = 2.0 V<br>1.25<br>2 2.5<br>1<br>1.5<br>1<br>0.75 4.5<br>2.7 3.0 3.5<br>0 0.5<br>0 1 2 3 0 0.5 1 1.5 2 2.5 3<br>VDS, Drain−Source Voltage (V) ID, Drain Current (A)<br>Figure 1. On−Region Characteristics Figure 2. On−Resistance Variation with<br>Drain Current and Gate Voltage<br>1.8 1.75<br>1.6 VID GS  = 1.3 A= 2.7 V VGS = 2.7 V TJ = 125 ° C<br>1.5<br>1.4<br>1.25<br>1.2 25 ° C<br>1<br>1<br>−55 ° C<br>0.75<br>0.8<br>0.6 0.5<br>−50 −25 0 25 50 75 100 125 150 0 0.5 1 1.5 2 2.5 3<br>TJ, Junction Temperature ( ° C) ID, Drain Current (A)<br>Figure 3. On−Resistance Variation with Figure 4. On−Resistance Variation with<br>Temperature Drain Current and Temperature<br>4 1.3<br>VDS = 5.0 V TJ = −55 ° C 25 ° C 1.2 VDS = VGS<br>125 ° C ID = 250  � A<br>3 1.1<br>1<br>2 0.9<br>0.8<br>1 0.7<br>0.6<br>0 0.5<br>0 0.5 1 1.5 2 2.5 3 −50 −25 0 25 50 75 100 125 150<br>VGS, Gate To Source Voltage (V) TJ, Junction Temperature ( ° C)<br>, Normalized<br>DS(on)<br>R<br>, Drain−Source Current (A)<br>ID Drain−Source On−Resistance<br>, Normalized  , Normalized<br>DS(on) DS(on)<br>R R<br>Drain−Source On−Resistance Drain−Source On−Resistance<br>, Drain Current (A)<br>ID Threshold Voltage<br>, Normalized Gate−Source<br>th<br>V<br>**----- End of picture text -----**<br>


**Figure 5. Transfer Characteristics** 

**Figure 6. Gate Threshold Variation with Temperature** 

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**4** 

**NDS331N** 

## **TYPICAL ELECTRICAL CHARACTERISTICS** (continued) 

**==> picture [240 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.12<br>ID = 250  � A<br>1.08<br>1.04<br>1<br>0.96<br>0.92<br>−50 −25 0 25 50 75 100 125 150<br>TJ, Junction Temperature ( ° C)<br>, Normalized Drain−Source Breakdown Voltage<br>DSS<br>BV<br>**----- End of picture text -----**<br>


**Figure 7. Breakdown Voltage Variation with Temperature** 

**==> picture [237 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>VGS = 0 V<br>0.1<br>T J  = 125 ° C 25 ° C<br>0.01<br>−55 ° C<br>0.001<br>0.0001<br>0 0.2 0.4 0.6 0.8 1 1.2<br>VSD, Body Diode Forward Voltage (V)<br>, Reverse Drain Current (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature** 

**==> picture [234 x 170] intentionally omitted <==**

**----- Start of picture text -----**<br>
600<br>400<br>200 Ciss<br>Coss<br>100<br>50<br>C rss<br>20 f = 1 MHz<br>VGS = 0 V<br>10<br>0.1 0.2 0.5 1 2 5 10 20<br>VDS, Drain−Source Voltage (V)<br>Capacitance (pF)<br>**----- End of picture text -----**<br>


**Figure 9. Capacitance Characteristics** 

**==> picture [230 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
5<br>ID = 1.3 A<br>VDS = 5 V 10 V<br>4<br>15 V<br>3<br>2<br>1<br>0<br>0 1 2 3 4 5<br>Qg, Gate Charge (nC)<br>, Gate−Source Voltage (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 10. Gate Charge Characteristics** 

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**----- Start of picture text -----**<br>
VDD<br>VIN RL<br>D VOUT<br>VGS<br>RGEN G DUT<br>S<br>**----- End of picture text -----**<br>


**Figure 11. Switching Test Circuit** 

**==> picture [211 x 146] intentionally omitted <==**

**----- Start of picture text -----**<br>
ton toff<br>td(on) tr td(off) tf<br>90% 90%<br>VOUT 10% 10%<br>Inverted<br>90%<br>50% 50%<br>VIN<br>10%<br>Pulse Width<br>**----- End of picture text -----**<br>


**Figure 12. Switching Waveforms** 

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**5** 

**NDS331N** 

## **TYPICAL ELECTRICAL CHARACTERISTICS** (continued) 

**==> picture [228 x 167] intentionally omitted <==**

**----- Start of picture text -----**<br>
8<br>VDS = 5.0 V<br>TJ = −55 ° C<br>6<br>25 ° C<br>4<br>125 ° C<br>2<br>0<br>0 1 2 3 4<br>ID, Drain Current (A)<br>, Transconductance (Siemens)<br>FS<br>g<br>**----- End of picture text -----**<br>


**Figure 13. Transconductance Variation with Drain Current and Temperature** 

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**----- Start of picture text -----**<br>
50<br>This Area is Limited by rDS(on)<br>10<br>100  � s<br>1 ms<br>1<br>10 ms<br>0.1 Single Pulse 100 ms<br>TJ = Max Rated<br>R � JA = 270 ° C/W Curve Bent to<br>T A  = 25 ° C Measured Date<br>0.01<br>0.1 1 10 60<br>VDS, Drain to Source Voltage (V)<br>, Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 14. Maximum Safe Operating Area** 

**==> picture [483 x 397] intentionally omitted <==**

**----- Start of picture text -----**<br>
1 1.8<br>0.8<br>1.6<br>0.6<br>1a<br>1.4<br>1b<br>0.4 1a<br>4.5 ″ x5 ″  FR−4 Board<br>0.2 T4.5A = 25 ″ x5 ″  FR ° C  −4 Board 1.2 1b TStill AirA = 25Still AirA = 25A = 25 = 25 ° C<br>Still Air VGS = 2.7 VGS = 2.7 V = 2.7 V<br>0 1<br>0 0.1 0.2 0.3 0.4 0 0.1 0.2 0.3<br>2oz Copper Mounting Pad Area (in [2] ) 2oz Copper Mounting Pad Area (in [[2]] )<br>Figure 15. SUPERSOT−3 Maximum Steady−State Figure 16. Maximum Steady−State Drain<br>Power Dissipation versus Copper Mounting Pad Area Current versus Copper Mounting Pad Area<br>2<br>Duty Cycle−Descending Order<br>1<br>D = 0.5<br>0.2<br>0.1<br>PDM<br>0.1 0.05<br>0.02<br>0.01 t1<br>t 2<br>NOTES:<br>0.01 Z � JA(t)= r(t) x R � JA<br>Single Pulse R � JA = 270 ° C/W<br>Peak T J  = P DM  x Z � JA (t) + T A<br>Duty Cycle, D = t1 / t2<br>0.001<br>10 [−4] 10 [−3] 10 [−2] 10 [−1] 1 10 100 1000<br>t, Rectangular Pulse Duration (s)<br>, Steady−State Drain Current (A)<br>IDD<br>Steady−State Power Dissipation (W)<br>, Normalized Thermal Impedance<br>JA<br>�<br>Z<br>**----- End of picture text -----**<br>


**==> picture [232 x 170] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.8<br>1.6<br>1.4<br>1a<br>4.5 ″ x5 ″  FR−4 Board<br>1.2 1b TStill AirA = 25Still AirA = 25A = 25 = 25 ° C<br>VGS = 2.7 VGS = 2.7 V = 2.7 V<br>1<br>0 0.1 0.2 0.3 0.4<br>2oz Copper Mounting Pad Area (in [[2]] )<br>, Steady−State Drain Current (A)<br>IDD<br>**----- End of picture text -----**<br>


**Figure 17. Transient Thermal Response Curve** 

NOTE: Thermal characterization performed using the conditions described in Note 1b. Response will change depending on the circuit board design. 

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**6** 

**NDS331N** 

SUPERSOT is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. 

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**7** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

## **SOT−23/SUPERSOT −23, 3 LEAD, 1.4x2.9** CASE 527AG ISSUE A 

## DATE 09 DEC 2019 

## **GENERIC** 

**MARKING DIAGRAM*** XXX = Specific Device Code M = Month Code XXXM = Pb−Free Package 

*This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ ”, may or may not be present. Some products may not follow the Generic Marking. 

(Note: Microdot may be in either location) 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

## **DOCUMENT NUMBER:** 

## **98AON34319E** 

**DESCRIPTION: SOT−23/SUPERSOT−23, 3 LEAD, 1.4X2.9** 

**PAGE 1 OF 1** 

ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

**onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** ’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **ADDITIONAL INFORMATION** 

**TECHNICAL PUBLICATIONS** : **ONLINE SUPPORT** : www.onsemi.com/support **Technical Library:** www.onsemi.com/design/resources/technical−documentation **For additional information, please contact your local Sales Representative at onsemi Website:** www.onsemi.com www.onsemi.com/support/sales 

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 



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