# Power MOSFET, N Channel, 44 V, 3.9 A, 0.145 ohm, SOT-223, Surface Mount ![Product image](https://novapart.co/image/farnell:3588857/) **URL**: https://novapart.co/products/NCV8412ASTT3G/power-mosfet-n-channel-44-v-39-a-0145-ohm-sot-223 **SKU**: NCV8412ASTT3G **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.4730 **Stock**: 50+ **Lead Time**: 127 days (indicative) ## Specifications | Parameter | Value | |---|---| | Msl | - | | Svhc | No SVHC (25-Jun-2025) | | No. Of Pins | 4Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | AEC-Q101 | | Power Dissipation | 2.2W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | SOT-223 | | Drain Source Voltage Vds | 44V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 3.9A | | Drain Source On State Resistance | 0.145ohm | | Gate Source Threshold Voltage Max | 1.6V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:3588857/) ## Self-Protected Low Side Driver with In-Rush Current Management ## NCV8412, NCV8412D The NCV8412 is a three terminal protected Low−Side Smart Discrete FET. The protection features include Delta Thermal Shutdown, overcurrent, overtemperature, ESD and integrated Drain−to−Gate clamping for overvoltage protection. The device also offers fault indication via the gate pin. This device is suitable for harsh automotive environments. ## **Features** - Short−Circuit Protection with In−Rush Current Management ## **www.onsemi.com** **==> picture [190 x 43] intentionally omitted <==** **----- Start of picture text -----**
VDSS ID MAX
(Clamped) RDS(ON) TYP (Limited)
42 V 145 m @ 10 V 5.9 A
rsa ee
**----- End of picture text -----**
- Delta Thermal Shutdown - Thermal Shutdown with Automatic Restart - Overvoltage Protection - Integrated Clamp for Overvoltage Protection and Inductive Switching - ESD Protection **SOT−223 (TO−261) SOIC−8 NB CASE 318E CASE 751** - dV/dt Robustness - Analog Drive Capability (Logic Level Input) - NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Grade 1 Qualified and PPAP Capable - These Devices are Pb−Free and are RoHS Compliant ## **Typical Applications** - Switch a Variety of Resistive, Inductive and Capacitive Loads - Can Replace Electromechanical Relays and Discrete Circuits - Automotive/Industrial **==> picture [172 x 149] intentionally omitted <==** **----- Start of picture text -----**
Drain
Overvoltage
Gate Protection
Input
ESD Protection
Temperature Current Current
Limit Limit Sense
Source
**----- End of picture text -----**
## **MARKING DIAGRAM** **==> picture [151 x 216] intentionally omitted <==** **----- Start of picture text -----**
DRAIN
4
AYW
8
8412A
8412AD
ALYWX
1 2 3
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
8412A or 8412AD
= Specific Device Code
= Pb−Free Package
(Note: Microdot may be in either location)
DRAIN 1 DRAIN 1 DRAIN 2 DRAIN 2
GATE DRAIN SOURCE
SOURCE 1 GATE 1 SOURCE 2 GATE 2
**----- End of picture text -----**
## **ORDERING INFORMATION** See detailed ordering and shipping information on page 12 of this data sheet. **Figure 1. Block Diagram** Publication Order Number: **1** © Semiconductor Components Industries, LLC, 2019 **July, 2020 − Rev. 0** **NCV8412/D** **NCV8412, NCV8412D** ## **MAXIMUM RATINGS** |**MAXIMUM RATINGS**|||| |---|---|---|---| |**Rating**|**Symbol**|**Value**|**Unit**| |Drain−to−Source Voltage Internally Clamped|VDSS|42|V| |Drain−to−Gate Voltage Internally Clamped|VDG|42|V| |Gate−to−Source Voltage|VGS|�14|V| |Drain Current − Continuous|ID|Internally Limited|| |Total Power Dissipation (SOT−223)
@ TA= 25°C (Note 1)
@ TA= 25°C (Note 2)|PD|1.44
2.20|W| |Total Power Dissipation (SOIC−8 Dual), both channels loaded equally
@ TA= 25°C (Note 1)
@ TA= 25°C (Note 2)|PD|1.14
1.53|W| |Total Power Dissipation (SOIC−8 Dual), only one channel loaded
@ TA= 25°C (Note 1)
@ TA= 25°C (Note 2)|PD|0.93
1.18|W| |Thermal Resistance (SOT−223)
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Junction−to−Case (Soldering Point)
Junction−to−Case (Top)|R�JA
R�JA
R�JS
R�JCT|86.7
56.9
4.7
58|°C/W| |Thermal Resistance (SOIC−8 Dual), both channels loaded equallyJunction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Junction−to−Case (Soldering Point)
Junction−to−Case (Top)|R�JA
R�JA
R�JS
R�JCT|109.2
81.7
28.6
69|°C/W| |Thermal Resistance (SOIC−8 Dual), only one channel loaded
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Junction−to−Case (Soldering Point)
Junction−to−Case (Top)|R�JA
R�JA
R�JS
R�JCT|134.4
105.8
28.6
69|°C/W| |Single Pulse Inductive Load Switching Energy
(L = 50 mH, ILpeak= 2 A, VGS= 5 V, RG= 25�, TJstart= 25°C)|EAS|100|mJ| |Load Dump Voltage
(VGS= 0 and 10 V, RL= 22�) (Note 3)|US*|55|V| |Operating Junction Temperature|TJ|−40 to 150|°C| |Storage Temperature|Tstorage|−55 to 150|°C| Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Mounted onto a 80 x 80 x 1.6 mm single layer FR4 board (100 sq mm, 1 oz. Cu, steady state) 2. Mounted onto a 80 x 80 x 1.6 mm single layer FR4 board (645 sq mm, 1 oz. Cu, steady state) 3. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in production. Passed Class C according to ISO16750−1. ## **ESD ELECTRICAL CHARACTERISTICS** (Notes 4, 5) |**Parameter**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |Electro−Static Discharge Capability|Human Body Model (HBM)|ESD|4000|||V| ||Charged Device Model (CDM)||1000|||| 4. Not tested in production. 5. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (JS−001−2017) Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes smaller than 2 x 2 mm due to the inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current waveform characteristic defined in JEDEC JS−002−2018. **www.onsemi.com** **2** **NCV8412, NCV8412D** **==> picture [292 x 191] intentionally omitted <==** **----- Start of picture text -----**
+
ID
DRAIN
IG
+ GATE VDS
SOURCE
VGS
− −
**----- End of picture text -----**
**Figure 2. Voltage and Current Convention** **www.onsemi.com** **3** **NCV8412, NCV8412D** **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) |**ELECTRICAL CHARACTERISTICS**|(TJ= 25°C unless otherwise noted)|||||| |---|---|---|---|---|---|---| |**Parameter**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**| |**OFF CHARACTERISTICS**||||||| |Drain−to−Source Clamped Breakdown
Voltage|VGS= 0 V, ID= 10 mA|V(BR)DSS|42|44|49|V| ||VGS= 0 V, ID= 10 mA, TJ= 150°C
(Note 6)||39|42|49|| |Zero Gate Voltage Drain Current|VGS= 0 V, VDS= 32 V|IDSS||0.7|4.0|�A| ||VGS= 0 V, VDS= 32 V, TJ= 150°C
(Note 6)|||2.3|20|| |Gate Input Current|VGS= 5 V, VDS= 0 V|IGSS||52|72|�A| |**ON CHARACTERISTICS**||||||| |Gate Threshold Voltage|VGS= VDS, ID= 150�A|VGS(th)|1.0|1.6|2.2|V| |Gate Threshold Temperature Coefficient|VGS= VDS, ID= 150�A (Note 6)|VGS(th)/TJ||3.1||mV/°C| |Static Drain−to−Source On Resistance|VGS= 10 V, ID= 1.7 A|RDS(ON)||145|200|m�| ||VGS= 10 V, ID= 1.7 A, TJ= 150°C
(Note 6)|||255|400|| ||VGS= 5.0 V, ID= 1.7 A|||180|230|| ||VGS= 5.0 V, ID= 1.7 A, TJ= 150°C
(Note 6)|||310|460|| ||VGS= 5.0 V, ID= 0.5 A|||180|230|| ||VGS= 5.0 V, ID= 0.5 A, TJ= 150°C
(Note 6)|||305|460|| |Source−to−Drain Forward On Voltage|IS= 7 A, VGS= 0 V|VSD||0.95|1.2|V| |**SWITCHING CHARACTERISTICS**(Note 6)||||||| |Turn−On Time (10% VGSto 90% ID)|VGS= 0 V to 10 V,
VDD= 12 V, ID= 1 A|tON||20|31|�s| |Turn−On Rise Time (10% IDto 90% ID)||trise||14|25|�s| |Turn−Off Time (90% VGSto 10% ID)||tOFF||96|140|�s| |Turn−Off Fall Time (90% IDto 10% ID)||tfall||37|50|�s| |Slew Rate On (80% VDSto 50% VDS)||−dVDS/dtON|0.45|1.0||V��s| |Slew Rate Off(50% VDSto 80% VDS)||dVDS/dtOFF|0.3|0.4||V��s| |**SELF PROTECTION CHARACTERISTICS**||||||| |Current Limit|VDS= 10 V, VGS= 5.0 V|ILIM|3.3|4.4|5.6|A| ||VDS= 10 V, VGS= 5.0 V, TJ= 150°C
(Note 6)||3.3|4.0|4.9|| ||VDS= 10 V, VGS= 10 V (Note 6)||2.6|3.9|5.9|| ||VDS= 10 V, VGS= 10 V, TJ= 150°C
(Note 6)||2.3|3.5|5.0|| |Temperature Limit (Turn−Off)|VGS= 5.0 V (Note 6)|TLIM(OFF)|150|175|190|°C| |Thermal Hysteresis||�TLIM(ON)||15||| |Temperature Limit (Turn−Off)|VGS= 10 V (Note 6)|TLIM(OFF)|150|185|200|| |Thermal Hysteresis||�TLIM(ON)||15||| |**GATE INPUT CHARACTERISTICS**(Note 6)||||||| |Device ON Gate Input Current|VGS= 5 V, VDS= 10 V, ID= 1 A|IGON|25|52|72|�A| ||VGS= 10 V, VDS= 10 V, ID= 1 A||250|333|480|| |Current Limit Gate Input Current|VGS= 5 V, VDS= 10 V|IGCL|35|65|96|| ||VGS= 10 V, VDS= 10 V||200|390|540|| |Thermal Limit Gate Input Current|VGS= 5 V, VDS= 10 V, ID= 0 A|IGTL|550|630|750|| ||VGS= 10 V, VDS= 10 V, ID= 0 A||1350|1500|1650|| Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Not tested in production. **www.onsemi.com** **4** **NCV8412, NCV8412D** ## **TYPICAL PERFORMANCE CURVES** **==> picture [235 x 379] intentionally omitted <==** **----- Start of picture text -----**
10
TJstart = 25 ° C
TJstart = 150 ° C
1
10 100
L (mH)
Figure 3. Single Pulse Maximum Switch−off
Current vs. Load Inductance
10
T Jstart = 25 ° C
1 T Jstart = 150 ° C
0.1
1 10
TIME IN CLAMP (ms)
(A)
IL(max)
(A)
IL(max)
**----- End of picture text -----**
**Figure 5. Single Pulse Maximum Inductive Switch−off Current vs. Time in Clamp** **==> picture [243 x 379] intentionally omitted <==** **----- Start of picture text -----**
1000
TJstart = 25 ° C
100
T Jstart = 150 ° C
10
10 100
L (mH)
Figure 4. Single Pulse Maximum Switching
Energy vs. Load Inductance
1000
TJstart = 25 ° C
100
TJstart = 150 ° C
10
1 10
TIME IN CLAMP (ms)
(mJ)
max
E
(mJ)
max
E
**----- End of picture text -----**
**Figure 6. Single Pulse Maximum Inductive Switching Energy vs. Time in Clamp** **==> picture [232 x 170] intentionally omitted <==** **----- Start of picture text -----**
5
TA = 25 ° C 8 V
6 V
10 V
4
5 V
4 V
3
3.5 V
2
3 V
1
VGS = 2.5 V
0
0 1 2 3 4 5
VDS (V)
(A)
ID
**----- End of picture text -----**
**Figure 7. On−state Output Characteristics** **==> picture [243 x 170] intentionally omitted <==** **----- Start of picture text -----**
5
VDS = 10 V
25 ° C −40 ° C
4
3 150 ° C
105 ° C
2
1
0
1 2 3 4 5
VGS (V)
(A)
ID
**----- End of picture text -----**
**Figure 8. Transfer Characteristics** **www.onsemi.com** **5** **NCV8412, NCV8412D** ## **TYPICAL PERFORMANCE CURVES** **==> picture [239 x 373] intentionally omitted <==** **----- Start of picture text -----**
400
150 ° C, ID = 1.7 A
150 ° C, ID = 0.5 A
300
105 ° C, I D = 1.7 A
105 ° C, ID = 0.5 A
200
25 ° C, ID = 1.7 A
25 ° C, ID = 0.5 A
100
−40 ° C, ID = 0.5 A
−40 ° C, ID = 1.7 A
0
4 5 6 7 8 9 10
VGS (V)
Figure 9. RDS(on) vs. Gate−Source Voltage
2
ID = 1.7 A
1.75
VGS = 5 V
1.5
1.25
VGS = 10 V
1
0.75
0.5
−40 −20 0 20 40 60 80 100 120 140
TJ ( ° C)
) �
(m
DS(on)
R
(NORMIALZIZED)
DS(on)
R
**----- End of picture text -----**
**Figure 11. Normalized RDS(on) vs. Temperature** **==> picture [243 x 374] intentionally omitted <==** **----- Start of picture text -----**
350
150 ° C, VGS = 5 V
300
105 ° C, VGS = 10 V
250 °
150 C, V GS = 10 V
105 ° C, VGS = 5 V
200
25 ° C, VGS = 5 V
150 25 ° C, V GS = 10 V
100 −40 ° C, VGS = 5 V
−40 ° C, VGS = 10 V
50
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
ID (A)
Figure 10. RDS(on) vs. Drain Current
8
VDS = 10 V
7
6 25 ° C
−40 ° C
5
150 ° C
4
3 105 ° C
2
5 6 7 8 9 10
VGS (V)
) �
(m
DS(on)
R
(A)
ILIM
**----- End of picture text -----**
**Figure 12. Current Limit vs. Gate−Source Voltage** **==> picture [233 x 172] intentionally omitted <==** **----- Start of picture text -----**
5.5
VDS = 10 V
5
4.5
VGS = 10 V
4
3.5 VGS = 5 V
3
−40 −20 0 20 40 60 80 100 120 140
TJ ( ° C)
(A)
ILIM
**----- End of picture text -----**
**Figure 13. Current Limit vs. Junction Temperature** **==> picture [243 x 171] intentionally omitted <==** **----- Start of picture text -----**
100
VGS = 0 V
10
1 150 ° C
0.1
105 ° C
0.01 25 ° C
−40 ° C
0.001
10 15 20 25 30 35 40
VDS (V)
A)
�
(
IDSS
**----- End of picture text -----**
**Figure 14. Drain−to−Source Leakage Current** **www.onsemi.com** **6** **NCV8412, NCV8412D** ## **TYPICAL PERFORMANCE CURVES** **==> picture [241 x 603] intentionally omitted <==** **----- Start of picture text -----**
1.2
ID = 150 � A
1.1 V GS = V DS
1
0.9
0.8
0.7
0.6
−40 −20 0 20 40 60 80 100 120 140
TJ ( ° C)
Figure 15. Normalized Threshold Voltage vs.
Temperature
160 ID = 1 A
VDD = 12 V
140 tr tON RG = 0 �
120
100 t OFF
80
60
40
20 t f
0
3 4 5 6 7 8 9 10
VGS (V)
Figure 17. Resistive Load Switching Time vs.
Gate−Source Voltage
tOFF, (VGS = 10 V)
100
I D = 1 A
80 VDD = 12 V
tOFF, (VGS = 5 V)
60 t ON , (V GS = 5 V)
tf, (VGS = 10 V) tr, (VGS = 5 V)
40
tf, (VGS = 5 V)
20
tON, (VGS = 10 V)
t r , (V GS = 10 V)
0
0 500 1000 1500 2000
RG ( � )
(V)
GS(th)
NORMALIZED V
s)
�
TIME (
s)
�
TIME (
**----- End of picture text -----**
**Figure 19. Resistive Load Switching Time vs. Gate Resistance** **==> picture [245 x 603] intentionally omitted <==** **----- Start of picture text -----**
1.1
1 −40 ° C
0.9 25 ° C
0.8 105 ° C
0.7
150 ° C
0.6
VGS = 0 V
0.5
1 2 3 4 5 6 7 8 9 10
IS (A)
Figure 16. Source−Drain Diode Forward
Characteristics
1.5
ID = 1 A
VDD = 12 V
RG = 0 �
−dVDS/dtON
1.0
0.5 dVDS/dtOFF
0
3 4 5 6 7 8 9 10
VGS (V)
Figure 18. Resistive Load Switching
Drain−Source Voltage Slope vs. Gate−Source
Voltage
1.4
−dV DS /dt ON , V GS = 10 V
1.2
1 ID = 1 A
VDD = 12 V
0.8
0.6 dVDS/dtOFF, VGS = 5 V
dVDS/dtOFF, VGS = 10 V
0.4
−dVDS/dtON, VGS = 5 V
0.2
0
0 500 1000 1500 2000
RG ( � )
(V)
SD
V
s)
�
DRAIN−SOURCE VOLTAGE SLOPE (V/
s)
�
DRAIN−SOURCE VOLTAGE SLOPE (V/
**----- End of picture text -----**
**Figure 20. Drain−Source Voltage Slope during Turn On and Turn Off vs. Gate Resistance** **www.onsemi.com** **7** **NCV8412, NCV8412D** ## **TYPICAL PERFORMANCE CURVES** **==> picture [244 x 170] intentionally omitted <==** **----- Start of picture text -----**
110
100
90
PCB Cu thickness, 1.0 oz
80
70
60
50 PCB Cu thickness, 2.0 oz
40
0 100 200 300 400 500 600 700
COPPER HEAT SPREADER AREA (mm [2] )
C/W)
°
(
JA
�
R
**----- End of picture text -----**
**Figure 21. R � JA vs. Copper Area − SOT−223** **==> picture [485 x 177] intentionally omitted <==** **----- Start of picture text -----**
100
50% Duty Cycle
20%
10
10%
5%
2%
1
1%
0.1
Single Pulse
645 mm [2] 1 oz. Copper
0.01
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
PULSE WIDTH (sec)
C/W)
( ° JA(t)
�
R
**----- End of picture text -----**
**Figure 22. Transient Thermal Resistance − SOT−223** **www.onsemi.com** **8** **NCV8412, NCV8412D** ## **APPLICATION INFORMATION** ## **Circuit Protection Features** The NCV8412 has three main protections. Current Limit, Thermal Shutdown and Delta Thermal Shutdown. These protections establish robustness of the NCV8412. junction temperature is exceeded. When activated at typically 175°C, the NCV8412 turns off. This feature is provided to prevent failures from accidental overheating. ## **EMC Performance** ## **Current Limit and Short Circuit Protection** The NCV8412 has current sense element. In the event that the drain current reaches designed current limit level, integrated Current Limit protection establishes its constant level. If better EMC performance is needed, connect a small ceramic capacitor to the drain pin as close to the device as possible according to Figure 23. ## **Delta Thermal Shutdown** Delta Thermal Shutdown (DTSD) Protection increases higher reliability of the NCV8412. DTSD consist of two independent temperature sensors – cold and hot sensors. The NCV8412 establishes a slow junction temperature rise by sensing the difference between the hot and cold sensors. ON/OFF output cycling is designed with hysteresis that results in a controlled saw tooth temperature profile (Figure 24). The die temperature slowly rises (DTSD) until the absolute temperature shutdown (TSD) is reached around 175°C. ## **Thermal Shutdown with Automatic Restart** Internal Thermal Shutdown (TSD) circuitry is provided to protect the NCV8412 in the event that the maximum **Figure 23. EMC Capacitor Placement** ## **TEST CIRCUITS AND WAVEFORMS** **==> picture [367 x 254] intentionally omitted <==** **----- Start of picture text -----**
Thermal Transient Limitation Phase Overtemperature Nominal
Cycling Load
VG
ILIM
ID
INOM
TSD
Delta TSD
activation
TJ
Time
**----- End of picture text -----**
**Figure 24. Overload Protection Behavior** **www.onsemi.com** **9** **NCV8412, NCV8412D** **==> picture [182 x 157] intentionally omitted <==** **----- Start of picture text -----**
RL
VIN
D +
RG VDD
G DUT −
S
IDS
**----- End of picture text -----**
**Figure 25. Resistive Load Switching Test Circuit** **Figure 26. Resistive Load Switching Waveforms** **www.onsemi.com** **10** **NCV8412, NCV8412D** **==> picture [251 x 223] intentionally omitted <==** **----- Start of picture text -----**
L
VDS
VIN
D +
RG VDD
G DUT −
S
t
p
IDS
**----- End of picture text -----**
**Figure 27. Inductive Load Switching Test Circuit** **==> picture [322 x 259] intentionally omitted <==** **----- Start of picture text -----**
5 V
VIN 0 V
tav
t
p
V(BR)DSS
Ipk
VDS VDD
VDS(on)
IDS 0
Time
**----- End of picture text -----**
**Figure 28. Inductive Load Switching Waveforms** **www.onsemi.com** **11** **NCV8412, NCV8412D** ## **DEVICE ORDERING INFORMATION** |**Device**|**Marking**|**Package**|**Shipping**†| |---|---|---|---| |NCV8412ASTT1G|8412A|SOT−223
(Pb−Free)|1,000 / Tape & Reel| |NCV8412ASTT3G|8412A|SOT−223
(Pb−Free)|1,000 / Tape & Reel| |NCV8412ADDR2G
(In Development)|8412AD|SOIC−8
(Pb−Free)|2,500 / Tape & Reel| †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. **www.onsemi.com** **12** **NCV8412, NCV8412D** ## **PACKAGE DIMENSIONS** **SOT−223 (TO−261)** CASE 318E−04 ISSUE R **==> picture [114 x 72] intentionally omitted <==** **==> picture [96 x 58] intentionally omitted <==** **==> picture [47 x 34] intentionally omitted <==** **==> picture [52 x 48] intentionally omitted <==** **==> picture [6 x 6] intentionally omitted <==** **----- Start of picture text -----**
�
**----- End of picture text -----**
**==> picture [7 x 8] intentionally omitted <==** **----- Start of picture text -----**
�
**----- End of picture text -----**
**www.onsemi.com** **13** **NCV8412, NCV8412D** ## **PACKAGE DIMENSIONS** **==> picture [468 x 463] intentionally omitted <==** **----- Start of picture text -----**
SOIC−8 NB
CASE 751−07
NOTES:
−X− ISSUE AK 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
a cters 5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
C N X 45 B 3.80 4.00 0.150 0.157
SEATING C 1.35 1.75 0.053 0.069
PLANE D 0.33 0.51 0.013 0.020
−Z− G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
0.10 (0.004) J 0.19 0.25 0.007 0.010
H D M J K 0.40 1.27 0.016 0.050
M 0 8 0 8
N 0.25 0.50 0.010 0.020
0.25 (0.010) M Z Y S X S S 5.80 6.20 0.228 0.244
STYLE 11:
PIN 1. SOURCE 1
SOLDERING FOOTPRINT* 2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
1.52 7. DRAIN 1
8. DRAIN 1
0.060
ane
7.0 4.0
0.275 ma 0.155
0.6 1.270
0.024 ao 0.050
SCALE 6:1 mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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