# Power MOSFET, N Channel, 42 V, 2.37 A, 0.165 ohm, SOT-223, Surface Mount ![Product image](https://novapart.co/image/farnell:2724401/) **URL**: https://novapart.co/products/NCV8402ASTT3G/power-mosfet-n-channel-42-v-237-a-0165-ohm-sot-223 **SKU**: NCV8402ASTT3G **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.3210 **Stock**: 1000+ **Lead Time**: 127 days (indicative) ## Description Transistor Polarity:N Channel; Continuous Drain Current Id:2.37A; Drain Source Voltage Vds:42V; On Resistance Rds(on):0.165ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:1. ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | No SVHC (25-Jun-2025) | | No. Of Pins | 4Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | AEC-Q101 | | Power Dissipation | 1.1W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | SOT-223 | | Drain Source Voltage Vds | 42V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 2.37A | | Drain Source On State Resistance | 0.165ohm | | Gate Source Threshold Voltage Max | 1.8V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2724401/) **DATA SHEET www.onsemi.com** ## Self-Protected Low Side Driver with Temperature and Current Limit NCV8402, NCV8402A NCV8402/A is a three terminal protected Low−Side Smart Discrete device. The protection features include overcurrent, overtemperature, ESD and integrated Drain−to−Gate clamping for overvoltage protection. This device offers protection and is suitable for harsh automotive environments. ## **Features** - Short−Circuit Protection - Thermal Shutdown with Automatic Restart - Overvoltage Protection - Integrated Clamp for Inductive Switching - ESD Protection - NCV8402AMNWT1G − Wettable Flanks Product - dV/dt Robustness - Analog Drive Capability (Logic Level Input) - NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable - These Devices are Pb−Free and are RoHS Compliant ## **Typical Applications** - Switch a Variety of Resistive, Inductive and Capacitive Loads - Can Replace Electromechanical Relays and Discrete Circuits - Automotive / Industrial **==> picture [183 x 149] intentionally omitted <==** **----- Start of picture text -----**
Drain
Overvoltage
Gate Protection
Input
ESD Protection
Temperature Current Current
Limit Limit Sense
Source
**----- End of picture text -----**
|**V(BR)DSS**
**(Clamped)**|**RDS(ON) TYP**|**ID MAX**| |---|---|---| |42 V|165 m�@ 10 V|2.0 A*| *Max current limit value is dependent on input condition. ## **MARKING DIAGRAMS** **==> picture [183 x 235] intentionally omitted <==** **----- Start of picture text -----**
DRAIN
4
4 SOT−223 AYW
1 2 CASE 318ESTYLE 3 xxxxx � �
3
1 2 3
GATE SOURCE
DRAIN
1 xxxxx
DFN6 AYWW
CASE 506AX �
1
1 xxxxx
DFN6 (WF) AYWW
CASE 506DK �
1
A = Assembly Location
Y = Year
W or WW = Work Week
xxxxx = V8402 or 8402A
� = Pb−Free Package
**----- End of picture text -----**
(Note: Microdot may be in either location) ## **DFN6 PACKAGE PIN DESCRIPTION** |G
|NC NC
7
PAD
S
S
2
3
5
4|**Pin #**|**Symbol**|**Description**| |---|---|---|---|---| |E
1
6|2
3|1|G|Gate Input| |||2|NC|No Connect| |||3|NC|No Connect| |||4|S*|Source| ||5
4|||| |S||5|S*|Source| |||6|S*|Source| |||7|EPAD|Drain| *Pins 4, 5, 6 are internally shorted together. It is recommended to short these pins externally. ## **ORDERING INFORMATION** See detailed ordering and shipping information on page 11 of this data sheet. Publication Order Number: **NCV8402/D** **1** © Semiconductor Components Industries, LLC, 2016 **August, 2021 − Rev. 27** **NCV8402, NCV8402A** ## **MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) |**MAXIMUM RATINGS**(TJ= 25°C unless otherwise noted)|||| |---|---|---|---| |**Rating**|**Symbol**|**Value**|**Unit**| |Drain−to−Source Voltage Internally Clamped|VDSS|42|V| |Drain−to−Gate Voltage Internally Clamped
(RG= 1.0 M�)|VDGR|42|V| |Gate−to−Source Voltage|VGS|±14|V| |Continuous Drain Current|ID|Internally Limited|| |Total Power Dissipation − SOT−223 Version
@ TA= 25°C (Note 1)
@ TA= 25°C (Note 2)
@ TS= 25°C)|PD|1.1
1.74
8.9|W| |Total Power Dissipation − DFN Version
@ TA= 25°C (Note 1)
@ TA= 25°C (Note 2)
@ TS= 25°C)|PD|0.76
1.78
8.9|W| |Maximum Continuous Drain Current − SOT−223 Version
@ TA= 25°C (Note 1)
@ TA= 25°C (Note 2)
@ TS= 25°C)|ID|1.54
1.94
6.75|A| |Maximum Continuous Drain Current − DFN Version
@ TA= 25°C (Note 1)
@ TA= 25°C (Note 2)
@ TS= 25°C)|ID|1.28
1.97
6.75|A| |Thermal Resistance
SOT223 Junction−to−Ambient Steady State (Note 1)
SOT223 Junction−to−Ambient Steady State (Note 2)
SOT223 Junction−to−Soldering Point Steady State
DFN Junction−to−Ambient Steady State (Note 1)
DFN Junction−to−Ambient Steady State (Note 2)
DFN Junction−to−Soldering Point Steady State|R�JA
R�JA
R�JS
R�JA
R�JA
R�JS|114
72
14
163
70
14|°C/W| |Single Pulse Drain−to−Source Avalanche Energy
(VDD= 32 V, VG= 5.0 V, IPK= 1.0 A, L = 300 mH, RG(ext)= 25�)|EAS|150|mJ| |Load Dump Voltage
(VGS= 0 and 10 V, RI= 2.0�, RL= 9.0�, td= 400 ms)|VLD|55|V| |Operating Junction Temperature|TJ|−40 to 150|°C| |Storage Temperature|Tstg|−55 to 150|°C| Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Surface−mounted onto min pad FR4 PCB, (2 oz. Cu, 0.06 ″ thick). 2. Surface−mounted onto 2 ″ sq. FR4 board (1 ″ sq., 1 oz. Cu, 0.06 ″ thick). **==> picture [289 x 193] intentionally omitted <==** **----- Start of picture text -----**
+
ID
DRAIN
IG
VDS
+ GATE
SOURCE
VGS
− −
**----- End of picture text -----**
**Figure 1. Voltage and Current Convention** **www.onsemi.com** **2** **NCV8402, NCV8402A** **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) |**ELECTRICAL CHARACTERISTICS**|(TJ= 25°C unless otherwise noted)|||||| |---|---|---|---|---|---|---| |**Parameter**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**| |**OFF CHARACTERISTICS**||||||| |Drain−to−Source Breakdown Voltage
(Note 3)|VGS= 0 V, ID= 10 mA, TJ= 25°C|V(BR)DSS|42|46|55|V| ||VGS= 0 V, ID= 10 mA, TJ= 150°C
(Note 5)||40|45|55|| |Zero Gate Voltage Drain Current|VGS= 0 V, VDS= 32 V, TJ= 25°C|IDSS||0.25|4.0|�A| |Zero Gate Voltage Drain Current|VGS= 0 V, VDS= 32 V, TJ= 150°C
(Note 5)|IDSS||1.1|20|�A| |Gate Input Current|VDS= 0 V, VGS= 5.0 V|IGSSF||50|100|�A| |**ON CHARACTERISTICS**(Note 3)||||||| |Gate Threshold Voltage|VGS= VDS, ID= 150�A|VGS(th)|1.3|1.8|2.2|V| |Gate Threshold Temperature Coefficient||VGS(th)/TJ||4.0||−mV/°C| |Static Drain−to−Source On−Resistance|VGS= 10 V, ID= 1.7 A, TJ= 25°C|RDS(on)||165|200|m�| ||VGS= 10 V, ID= 1.7 A, TJ= 150°C
(Note 5)|||305|400|| ||VGS= 5.0 V, ID= 1.7 A, TJ= 25°C|||195|230|| ||VGS= 5.0 V, ID= 1.7 A, TJ= 150°C
(Note 5)|||360|460|| ||VGS= 5.0 V, ID= 0.5 A, TJ= 25°C|||190|230|| ||VGS= 5.0 V, ID= 0.5 A, TJ= 150°C
(Note 5)|||350|460|| |Source−Drain Forward On Voltage|VGS= 0 V, IS= 7.0 A|VSD||1.0||V| |**SWITCHING CHARACTERISTICS**(Note 5)||||||| |Turn−On Time (10% VINto 90% ID)|VGS= 10 V, VDD= 12 V,
ID= 2.5 A, RL= 4.7�|ton||25|30|�s| |Turn−Off Time (90% VINto 10% ID)||toff||120|200|�s| |Turn−On Rise Time (10% IDto 90% ID)||trise||20|25|�s| |Turn−Off Fall Time (90% IDto 10% ID)||tfall||50|70|�s| |Slew−Rate ON (70% to 50% VDD)||−dVDS/dtON||0.8|1.2|V��s| |Slew−Rate OFF (50% to 70% VDD)||dVDS/dtOFF||0.3|0.5|V��s| |**SELF PROTECTION CHARACTERISTICS **(TJ= 25°C unless otherwise noted) (Note 4)||||||| |Current Limit|VDS= 10 V, VGS= 5.0 V, TJ= 25°C|ILIM|3.7|4.3|5.0|A| ||VDS= 10 V, VGS= 5.0 V, TJ= 150°C
(Note 5)||2.3|3.0|3.7|| ||VDS= 10 V, VGS= 10 V, TJ= 25°C||4.2|4.8|5.4|| ||VDS= 10 V, VGS= 10 V, TJ= 150°C
(Note 5)||2.7|3.6|4.5|| |Temperature Limit (Turn−off)|VGS= 5.0 V (Note 5)|TLIM(off)|150|175|200|°C| |Thermal Hysteresis|VGS= 5.0 V|�TLIM(on)||15||| |Temperature Limit (Turn−off)|VGS= 10 V (Note 5)|TLIM(off)|150|165|185|| |Thermal Hysteresis|VGS= 10 V|�TLIM(on)||15||| |**GATE INPUT CHARACTERISTICS**(Note 5)||||||| |Device ON Gate Input Current|VGS= 5 V ID= 1.0 A|IGON||50||�A| ||VGS= 10 V ID= 1.0 A|||400||| |Current Limit Gate Input Current|VGS= 5 V, VDS= 10 V|IGCL||0.05||mA| ||VGS= 10 V, VDS= 10 V|||0.4||| 3. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 4. Fault conditions are viewed as beyond the normal operating range of the part. 5. Not subject to production testing. **www.onsemi.com** **3** **NCV8402, NCV8402A** ## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) |**ELECTRICAL CHARACTERISTICS**|(TJ= 25°C unless otherwise noted)|||||| |---|---|---|---|---|---|---| |**Parameter**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**| |**GATE INPUT CHARACTERISTICS**(Note 5)||||||| |Thermal Limit Fault Gate Input Current|VGS= 5 V, VDS= 10 V|IGTL||0.15||mA| ||VGS= 10 V, VDS= 10 V|||0.7||| |**ESD ELECTRICAL CHARACTERISTICS **(TJ= 25°C unless otherwise noted) (Note 5)||||||| |Electro−Static Discharge Capability|Human Body Model (HBM)|ESD|4000|||V| ||Machine Model (MM)||400|||| 3. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 4. Fault conditions are viewed as beyond the normal operating range of the part. 5. Not subject to production testing. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. **www.onsemi.com** **4** **NCV8402, NCV8402A** ## **TYPICAL PERFORMANCE CURVES** **==> picture [238 x 170] intentionally omitted <==** **----- Start of picture text -----**
10
TJstart = 25 ° C
TJstart = 150 ° C
1
10 100
L (mH)
(A)
IL(max)
**----- End of picture text -----**
**Figure 2. Single Pulse Maximum Switch−off Current vs. Load Inductance** **==> picture [244 x 170] intentionally omitted <==** **----- Start of picture text -----**
1000
100 TJstart = 25 ° C
TJstart = 150 ° C
10
10 100
L (mH)
(mJ)
max
E
**----- End of picture text -----**
**Figure 3. Single Pulse Maximum Switching Energy vs. Load Inductance** **==> picture [235 x 167] intentionally omitted <==** **----- Start of picture text -----**
10
TJstart = 25 ° C
1 TJstart = 150 ° C
0.1
1 10
TIME IN CLAMP (ms)
(A)
IL(max)
**----- End of picture text -----**
**Figure 4. Single Pulse Maximum Inductive Switch−off Current vs. Time in Clamp** **==> picture [243 x 167] intentionally omitted <==** **----- Start of picture text -----**
1000
TJstart = 25 ° C
100
TJstart = 150 ° C
10
1 10
TIME IN CLAMP (ms)
(mJ)
max
E
**----- End of picture text -----**
**Figure 5. Single Pulse Maximum Inductive Switching Energy vs. Time in Clamp** **==> picture [232 x 171] intentionally omitted <==** **----- Start of picture text -----**
8
TA = 25 ° C 8 V 10 V
7
6 V
6
5 V
4 V
5
4 3.5 V
3
3 V
2
1 V GS = 2.5 V
0
0 1 2 3 4 5
VDS (V)
(A)
ID
**----- End of picture text -----**
**Figure 6. On−state Output Characteristics** **==> picture [243 x 171] intentionally omitted <==** **----- Start of picture text -----**
8
VDS = 10 V −40 ° C
7
6 25 ° C
5
100 ° C
4
3 150 ° C
2
1
0
1 2 3 4 5
VGS (V)
(A)
ID
**----- End of picture text -----**
**Figure 7. Transfer Characteristics** **www.onsemi.com** **5** **NCV8402, NCV8402A** ## **TYPICAL PERFORMANCE CURVES** **==> picture [238 x 169] intentionally omitted <==** **----- Start of picture text -----**
400
150 ° C, ID = 0.5 A
300 150 ° C, I D = 1.7 A
200 100 ° C, ID = 0.5 A 100 ° C, ID = 1.7 A
25 ° C, ID = 1.7 A 25 ° C, ID = 0.5 A
100
−40 ° C, ID = 1.7 A −40 ° C, ID = 0.5 A
0
4 5 6 7 8 9 10
VGS (V)
) �
(m
DS(on)
R
**----- End of picture text -----**
**Figure 8. RDS(on) vs. Gate−Source Voltage** **==> picture [241 x 170] intentionally omitted <==** **----- Start of picture text -----**
350
150 ° C, VGS = 5 V
300
150 ° C, VGS = 10 V
250
100 ° C, VGS = 5 V
200 100 ° C, VGS = 10 V
25 ° C, VGS = 5 V
150 °
25 C, V GS = 10 V
100 −40 ° C, VGS = 5 V
−40 ° C, VGS = 10 V
50
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
ID (A)
) �
(m
DS(on)
R
**----- End of picture text -----**
**Figure 9. RDS(on) vs. Drain Current** **==> picture [492 x 392] intentionally omitted <==** **----- Start of picture text -----**
2 8
ID = 1.7 A −40 ° C
1.75 7
1.5 VGS = 5 V 6 25 ° C
1.25 5
100 ° C
1 VGS = 10 V 4 150 ° C
0.75 3
VDS = 10 V
0.5 2
−40 −20 0 20 40 60 80 100 120 140 5 6 7 8 9 10
T ( ° C) VGS (V)
Figure 10. Normalized RDS(on) vs. Temperature Figure 11. Current Limit vs. Gate−Source
Voltage
8 10
VGS = 0 V
7 150 ° C
1
6 VGS = 10 V
0.1
5 100 ° C
0.01
4
VGS = 5 V 25 ° C −40 ° C
0.001
3
VDS = 10 V
2 0.0001
−40 −20 0 20 40 60 80 100 120 140 10 15 20 25 30 35 40
TJ ( ° C) VDS (V)
(A)
ILIM
(NORMIALZIZED)
DS(on)
R
A)
�
(A) (
ILIM IDSS
**----- End of picture text -----**
**Figure 12. Current Limit vs. Junction Temperature** **Figure 13. Drain−to−Source Leakage Current** **www.onsemi.com** **6** **NCV8402, NCV8402A** ## **TYPICAL PERFORMANCE CURVES** **==> picture [238 x 379] intentionally omitted <==** **----- Start of picture text -----**
1.2
ID = 150 � A
1.1 VGS = VDS
1
0.9
0.8
0.7
0.6
−40 −20 0 20 40 60 80 100 120 140
T ( ° C)
Figure 14. Normalized Threshold Voltage vs.
Temperature
200
ID = 2.5 A
VDD = 12 V
RG = 0 �
150
100
td(off)
50 tf
tr
td(on)
0
3 4 5 6 7 8 9 10
VGS (V)
(V)
GS(th)
NORMALIZED V
s)
�
TIME (
**----- End of picture text -----**
**Figure 16. Resistive Load Switching Time vs. Gate−Source Voltage** **==> picture [244 x 174] intentionally omitted <==** **----- Start of picture text -----**
1.1
1 −40 ° C
0.9 25 ° C
0.8 100 ° C
0.7
150 ° C
0.6
VGS = 0 V
0.5
1 2 3 4 5 6 7 8 9 10
IS (A)
(V)
SD
V
**----- End of picture text -----**
**Figure 15. Source−Drain Diode Forward Characteristics** **==> picture [225 x 171] intentionally omitted <==** **----- Start of picture text -----**
1
ID = 2.5 A
VDD = 12 V
0.8 RG = 0 �
0.6 −dVDS/dt(on)
0.4
dVDS/dt(off)
0.2
0
3 4 5 6 7 8 9 10
VGS (V)
**----- End of picture text -----**
**==> picture [9 x 156] intentionally omitted <==** **----- Start of picture text -----**
s)
�
DRAIN−SOURCE VOLTAGE SLOPE (V/
**----- End of picture text -----**
**Figure 17. Resistive Load Switching Drain−Source Voltage Slope vs. Gate−Source Voltage** **==> picture [240 x 172] intentionally omitted <==** **----- Start of picture text -----**
100
ID = 2.5 A
V DD = 12 V
td(off), (VGS = 10 V)
75
tr, (VGS = 5 V)
50 tf, (VGS = 10 V) tf, (VGS = 5 V)
t d(off) , (V GS = 5 V)
25 tr, (VGS = 10 V)
t d(on) , (V GS = 5 V)
0 td(on), (VGS = 10 V)
0 400 800 1200 1600 2000
RG ( � )
s)
�
TIME (
**----- End of picture text -----**
**Figure 18. Resistive Load Switching Time vs. Gate Resistance** **==> picture [244 x 171] intentionally omitted <==** **----- Start of picture text -----**
1
0.8 −dVDS/dt(on), VGS = 10 V
0.6
0.4
dVDS/dt(off), VGS = 5 V dVDS/dt(off), VGS = 10 V
0.2
−dVDS/dt(on), VGS = 5 V ID = 2.5 A
VDD = 12 V
0
0 500 1000 1500 2000
RG ( � )
s)
�
DRAIN−SOURCE VOLTAGE SLOPE (V/
**----- End of picture text -----**
**Figure 19. Drain−Source Voltage Slope during Turn On and Turn Off vs. Gate Resistance** **www.onsemi.com** **7** **NCV8402, NCV8402A** ## **TYPICAL PERFORMANCE CURVES** **==> picture [487 x 176] intentionally omitted <==** **----- Start of picture text -----**
100
50% Duty Cycle
20%
10 10%
5%
2%
1
1%
0.1
Single Pulse
0.01
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
PULSE WIDTH (sec)
C/W
°
2
788 mm
JA
�
R
**----- End of picture text -----**
**Figure 20. Transient Thermal Resistance − SOT−223 Package** **==> picture [487 x 176] intentionally omitted <==** **----- Start of picture text -----**
100
50% Duty Cycle
20%
10 10%
5%
2%
1
1%
0.1
Single Pulse
0.01
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
PULSE WIDTH (sec)
C/W
°
2
788 mm
JA
�
R
**----- End of picture text -----**
**Figure 21. Transient Thermal Resistance − DFN Package** **www.onsemi.com** **8** **NCV8402, NCV8402A** ## **TEST CIRCUITS AND WAVEFORMS** **==> picture [207 x 208] intentionally omitted <==** **----- Start of picture text -----**
RL
VIN
D +
RG VDD
G DUT −
S
IDS
**----- End of picture text -----**
**Figure 22. Resistive Load Switching Test Circuit** **==> picture [334 x 187] intentionally omitted <==** **----- Start of picture text -----**
90%
10%
VIN
VDS
90%
td(on) + trise td(off) + tfall
10%
90%
10%
IDS
**----- End of picture text -----**
**Figure 23. Resistive Load Switching Waveforms** **www.onsemi.com** **9** **NCV8402, NCV8402A** ## **TEST CIRCUITS AND WAVEFORMS** **==> picture [252 x 223] intentionally omitted <==** **----- Start of picture text -----**
L
VDS
VIN
D +
RG
VDD
G DUT −
S
tp
IDS
**----- End of picture text -----**
**Figure 24. Inductive Load Switching Test Circuit** **==> picture [326 x 260] intentionally omitted <==** **----- Start of picture text -----**
5 V
VIN 0 V
Tav
T
p
V(BR)DSS
Ipk
VDD
VDS
VDS(on)
IDS
0
**----- End of picture text -----**
**Figure 25. Inductive Load Switching Waveforms** **www.onsemi.com** **10** **NCV8402, NCV8402A** ## **ORDERING INFORMATION** |**ORDERING INFORMATION**||| |---|---|---| |**Device***|**Package**|**Shipping**†| |NCV8402STT1G|SOT−223
(Pb−Free)|1000 / Tape & Reel| |NCV8402ASTT1G||| |NCV8402STT3G|SOT−223
(Pb−Free)|4000 / Tape & Reel| |NCV8402ASTT3G||| |NCV8402AMNT2G|DFN6
(Pb−Free)|2000 / Tape & Reel| |NCV8402AMNWT1G|DFN6
(Pb−Free, Wettable Flank)|3000 / Tape & Reel| †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable. **www.onsemi.com** **11** MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **SOT−223 (TO−261)** CASE 318E−04 ISSUE R **SCALE 1:1** ## DATE 02 OCT 2018 **DOCUMENT NUMBER: 98ASB42680B** **DESCRIPTION: SOT−223 (TO−261)** Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **PAGE 1 OF 2** ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2018 DATE 02 OCT 2018 ## **SOT−223 (TO−261)** CASE 318E−04 ISSUE R STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5: PIN 1. BASE PIN 1. ANODE PIN 1. GATE PIN 1. SOURCE PIN 1. DRAIN 2. COLLECTOR 2. CATHODE 2. DRAIN 2. DRAIN 2. GATE 3. EMITTER 3. NC 3. SOURCE 3. GATE 3. SOURCE 4. COLLECTOR 4. CATHODE 4. DRAIN 4. DRAIN 4. GATE STYLE 6: STYLE 7: STYLE 8: STYLE 9: STYLE 10: PIN 1. RETURN PIN 1. ANODE 1 CANCELLED PIN 1. INPUT PIN 1. CATHODE 2. INPUT 2. CATHODE 2. GROUND 2. ANODE 3. OUTPUT 3. ANODE 2 3. LOGIC 3. GATE 4. INPUT 4. CATHODE 4. GROUND 4. ANODE STYLE 11: STYLE 12: STYLE 13: PIN 1. MT 1 PIN 1. INPUT PIN 1. GATE 2. MT 2 2. OUTPUT 2. COLLECTOR 3. GATE 3. NC 3. EMITTER 4. MT 2 4. OUTPUT 4. COLLECTOR **GENERIC MARKING DIAGRAM*** AYW XXXXX 1 ~~|~~ A = Assembly Location Y = Year W = Work Week XXXXX = Specific Device Code = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ ”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42680B** Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **DESCRIPTION: SOT−223 (TO−261) PAGE 2 OF 2** ~~—ee~~ ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2018 MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **==> picture [6 x 7] intentionally omitted <==** **----- Start of picture text -----**
1
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**==> picture [41 x 7] intentionally omitted <==** **----- Start of picture text -----**
SCALE 2:1
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## **DFNW6 3x3, 0.95P** CASE 506DK ISSUE A ## DATE 07 MAY 2021 **==> picture [147 x 145] intentionally omitted <==** **----- Start of picture text -----**
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYW
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
a = Pb−Free Package
(Note: Microdot may be in either location)
**----- End of picture text -----**
- *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ : ”, may or may not be present. Some products may not follow the Generic Marking. ## **DOCUMENT NUMBER:** ## **DESCRIPTION:** ## **98AON12549G** ## **DFNW6 3X3, 0.95P** Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **PAGE 1 OF 1** ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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