# LED Driver, AC / DC, 3A, 1 Output, 9.4V to 26V Input, 200V Output, -40 to 125 °C, SOIC-8 ![Product image](https://novapart.co/image/farnell:3608626/) **URL**: https://novapart.co/products/NCL30188ADR2G/led-driver-ac-dc-3a-1-output-94v-to-26v-input-200v **SKU**: NCL30188ADR2G **Manufacturer**: ONSEMI **Category**: LED Lighting Components || LED Driver ICs || AC / DC LED Driver ICs **Price**: €0.3570 **Stock**: 10+ ## Specifications | Parameter | Value | |---|---| | Ic Mounting | Surface Mount | | No. Of Pins | 8Pins | | No. Of Outputs | 1Outputs | | Device Topology | Buck-Boost, Flyback, SEPIC | | Driver Case Style | NSOIC | | Input Voltage Max | 26V | | Input Voltage Min | 9.4V | | Output Current Max | 3A | | Output Voltage Max | 200V | | Switching Frequency | 65kHz | | Operating Temperature Max | 125°C | | Operating Temperature Min | -40°C | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:3608626/) **Share Feedback DATA SHEET** Your Opinion Matters **www.onsemi.com** ## Power Factor Corrected Quasi-Resonant Primary Side Current-Mode Controller for LED Lighting with Thermal Foldback NCL30188 The NCL30188 is a controller targeting isolated and non−isolated “smart−dimmable” constant−current LED drivers. Designed to support flyback, buck−boost, and SEPIC topologies, its proprietary current−control algorithm provides near−unity power factor and tightly regulates a constant LED current from the primary side, thus eliminating the need for a secondary−side feedback circuitry or an optocoupler. Housed in the SOIC8, the NCL30188 is specifically intended for very compact space−efficient designs. The device is highly integrated with a minimum number of external components. A robust suite of safety protections is built in to simplify the design. To ensure reliable operations at elevated temperatures, a user configurable current foldback circuit is also provided. Pin−to−pin compatible to the NCL30088, the NCL30188 provides the same benefits with in addition, an increased resolution of the digital current−control algorithm for a 75% reduction in the LED current quantization ripple. ## **Features** - Quasi−resonant Peak Current−mode Control Operation - Constant Current Control with Primary Side Feedback - Tight LED Constant Current Regulation of  2% Typical ## 8 1 **SOIC−8 NB CASE 751** ## **MARKING DIAGRAM** **==> picture [116 x 129] intentionally omitted <==** **----- Start of picture text -----**
8
L30188x
ALYW
1
L30188x = Specific Device Code
x = A, B
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
= Pb-Free Package
**----- End of picture text -----**
## **PIN CONNECTIONS** **==> picture [133 x 82] intentionally omitted <==** **----- Start of picture text -----**
1
ZCD VCC
VS DRV
COMP GND
SD CS
(Top View)
**----- End of picture text -----**
## **ORDERING INFORMATION** See detailed ordering and shipping information in the package dimensions section on page 25 of this data sheet. NOTE: Some of the device on this data sheet have been **DISCONTINUED** . Please refer to the table on page 25 - Power Factor Correction - Line Feedforward for Enhanced Regulation Accuracy - Low Start−up Current (13 A typ.) - Wide Vcc Range - 300 mA / 500 mA Totem Pole Driver with 12 V Gate Clamp - Robust Protection Features - OVP on VCC - Programmable Over Voltage / LED Open Circuit Protection - Cycle−by−cycle Peak Current Limit - Winding Short Circuit Protection - Secondary Diode Short Protection - Output Short Circuit Protection - Shorted Current Sense Protection - User Programmable NTC Based Thermal Foldback - Thermal Shutdown - Vcc Undervoltage Lockout - Brown−out Protection - Pb−Free, Halide−Free Product - Latching−off (NCL30188A) or 4−s Auto−recovery (NCL30188B) Protection Modes (See Table 4) ## **Typical Applications** - Integral LED Bulbs and Tubes - LED Light Engines - LED Drivers/Power Supplies - Electronic Control Gear for LED Lighting Publication Order Number: **NCL30188/D** **1**  Semiconductor Components Industries, LLC, 2016 **January, 2025 − Rev. 1** **NCL30188** **==> picture [298 x 223] intentionally omitted <==** **----- Start of picture text -----**
.
Ll
Aux
. .
5
NCL30188
1 8
2 7
3 6
4 5
EER
RSENSE
(en
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**Figure 1. Typical Application Schematic in a Flyback Converter** **==> picture [280 x 190] intentionally omitted <==** **----- Start of picture text -----**
Aux
. .
NN 7X -
NCL30188
1 8
2 7
3 6
4 5
i lam
RSENSE
(ea
**----- End of picture text -----**
**Figure 2. Typical Application Schematic in a Buck−Boost Converter** **www.onsemi.com** ~~a~~ **2** **Share Feedback** Your Opinion Matters **NCL30188** **Table 1. PIN FUNCTION DESCRIPTION** |~~ey~~|~~ee es~~|~~es~~|| |---|---|---|---| |**Pin No.**
~~ey~~|**Pin Name**
~~ee es~~|**Function**
~~es~~|**Pin Description**| |1
~~ey~~
~~TT).~~|ZCD
~~ee es~~
~~TT).~~|Zero Crossing Detection
~~es~~
~~TT).~~|Connected to the auxiliary winding, this pin detects the core reset event.
~~TT).~~| |2
~~TT).~~|VS
~~TT).~~|Input Voltage Sensing
~~TT).~~|This pin observes the input voltage rail and protects the LED driver in case of
too low mains conditions (brown−out).
This pin also observes the input voltage rail for:
− Power Factor Correction
− Valley lockout
~~TT).~~| |3
~~ee~~|COMP
~~ee~~|Filtering Capacitor
~~ee~~|This pin receives a filtering capacitor for power factor correction. Typical values
ranges from 1 − 4.70 F
~~ee~~| |4
~~ee~~
~~ee~~|SD
~~ee~~|Thermal Foldback and
Shutdown
~~ee~~|Connecting an NTC to this pin allows the user to program thermal current fold-
back threshold and slope. A Zener diode can also be used to pull−up the pin
and stop the controller for adjustable OVP protection.
~~ee~~
~~>~~| |5
~~$+~~
~~ee~~|CS
~~$+~~|Current Sense
~~$+~~|This pin monitors the primary peak current.
~~$+~~
~~>~~| |6
~~$+~~
~~ee~~|GND
~~$+~~
~~es es~~|−
~~$+~~
~~es~~|Controller ground pin.
~~$+~~
~~>~~
~~te~~| |7
~~ee~~|DRV
~~es es~~|Driver Output
~~es~~|The driver’s output to an external MOSFET
~~>~~
~~te~~| |8
~~ee~~
~~a~~|VCC
~~es es~~
~~a~~|IC Supply Pin
~~es~~
~~ee~~|This pin is the positive supply of the IC. The circuit starts to operate when_VCC_
exceeds 18 V and turns off when_VCC_goes below 8.8 V (typical values). After
start−up, the operating range is 9.4 V up to 25.5 V (_VCC_(_OVP_)minimum level).
~~>~~
~~te~~
~~ee~~| **www.onsemi.com** ~~a~~ **3** **Share Feedback** Your Opinion Matters **NCL30188** **Internal Circuit Architecture** **==> picture [452 x 431] intentionally omitted <==** **----- Start of picture text -----**
Enable STOP VDD VREF
Over Voltage Protection
(Auto−recovery or Latched) Aux_SCP OFF
VCC
Fault UVLO
VCC Management
Management
Over Temp. Protection Latch
(Auto−recovery or Latched)
— — ae
Internal
SD Thermal ThermalShutdown VCC_max VCC Over VoltageProtection
Foldback VTF WOD_SCP
BO_NOK
a ———
DRV FF_mode VVS VREF
VCC
FF_mode
ZCD Zero Crossing Detection Logic (ZCD Blanking, Time−Out, ...) Valley Selection ClampCircuit
Frequency Foldback
Aux. Winding Short Circuit Prot. Aux_SCP S DRV
VVS VTF CS_ok Q
Q
Line R
feed−forward STOP VVS VREF
VTF
CS ali. LeadingEdge Power Factor andConstant−Current CS_reset |, Maximum
Blanking Control on time
Ipkmax STOP
Li Max. Peak Ipkmax a t on,max COMP
Current
Limit
CS Short CS_ok VVS 7
Protection BO_NOK VS
_ Brown−Out
UVLO t
on,max
Winding and
WOD_SCP GND
Output diode
Short Circuit :
Protection
a
**----- End of picture text -----**
## **Figure 3. Internal Circuit Architecture** > **www.onsemi.com Share Feedback** ~~Qe”~~ **4** Your Opinion Matters **NCL30188** **Table 2. MAXIMUM RATINGS TABLE** |**Symbol**|**Rating**|**Value**|**Unit**| |---|---|---|---| |VCC(MAX)
ICC(MAX)|Maximum Power Supply voltage, VCCpin, continuous voltage
Maximum current for VCCpin|−0.3 to 30
Internally limited|V
mA| |VDRV(MAX)
IDRV(MAX)|Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin|−0.3, VDRV(Note 1)
−300, +500|V
mA| |VMAX
IMAX|Maximum voltage on low power pins (except DRV and VCCpins)
Current range for low power pins (except DRV and VCCpins)|−0.3, 5.5 (Notes 2 and 5)
−2, +5|V
mA| |RJ−A|Thermal Resistance Junction−to−Air|180|C/W| |TJ(MAX)|Maximum Junction Temperature|150|C| ||Operating Temperature Range|−40 to +125|C| ||Storage Temperature Range|−60 to +150|C| ||ESD Capability, HBM model (Note 3)|3.5|kV| ||ESD Capability, MM model (Note 3)|250|V| ||ESD Capability, CDM model (Note 3)|2|kV| Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC otherwise. 2. These levels are low enough not to exceed the maximum ratings of the internal ESD 5.5−V Zener diode. More positive and negative voltages can be applied if the pin current stays within the −2−mA / 5−mA range. 3. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114E, Machine Model Method 250 V per JEDEC Standard JESD22−A115B, Charged Device Model 2000 V per JEDEC Standard JESD22−C101E. 4. This device contains latch−up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds 100 mA 5. **Recommended maximum VS voltage for optimal operation is 4 V. −0.3 V to +4.0 V is hence, the VS pin recommended range.** **Table 3. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V, VZCD = 0 V, VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V) |Supply Voltage
Startup Threshold
Minimum Operating Voltage
Hysteresis VCC(on)– VCC(off)
Internal logic reset
~~|~~|VCCrising
VCCrising
VCCfalling
~~|~~|VCC(on)
VCC(off)
VCC(HYS)
VCC(reset)
~~|~~|16.0
8.2
8
4
~~|~~|18.0
8.8
−
5
~~|~~|20.0
9.4
−
6
~~|~~|V
~~|~~| |---|---|---|---|---|---|---| |VCCOver Voltage Protection Threshold
~~|~~|~~|~~
~~ee~~|VCC(OVP)
~~|~~
~~ee~~|25.5
~~|~~
~~ee ee~~|26.8
~~|~~
~~ee~~|28.5
~~|~~
~~ee~~|V
~~|~~
~~ee~~| |VCC(off)noise filter
VCC(reset)noise filter
~~ee~~|~~ee~~
~~ee~~|tVCC(off)
tVCC(reset)
~~ee~~
~~ee~~|−
−
~~ee~~
~~ee ee~~|5
20
~~ee~~
~~ee~~|−
−
~~ee~~
~~ee~~|s
~~ee~~
~~ee~~| |Startup current
~~oe~~|~~ee~~
~~oe~~|ICC(start)
~~ee~~
~~oe~~|−
~~ee ee~~
~~oe~~|13
~~ee~~
~~oe~~|30
~~ee~~
~~oe~~|A
~~ee~~
~~oe~~| |Startup current in fault mode
~~oe~~|~~oe~~|ICC(~~s~~
~~F~~ault)
~~oe~~|~~oe~~|58
~~oe~~|75
~~oe~~|A
~~oe~~| |Supply Current
Device Disabled/Fault
Device Enabled/No output load on pin 7
Device Switching (FSW= 65 kHz)
~~po~~|VCC> VCC(off)
Fsw= 65 kHz
CDRV= 470 pF, Fsw= 65 kHz
~~po~~|ICC1
ICC2
ICC3
~~po~~|0.8
–
−
~~po~~|1.0
2.6
3.0
~~po~~|1.2
4.0
4.5
~~po~~|mA
~~po~~| 7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation. 8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 s to avoid detecting an OTP fault by allowing the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. > **www.onsemi.com Share Feedback** ~~Qe”~~ **5** Your Opinion Matters ## **NCL30188** **Table 3. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V, VZCD = 0 V, VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V) |**Description**
**Unit**
**Max**
**Typ**
**Min**
**Symbol**
**Test Condition**
**CURRENT SENSE**
~~ee~~| |---| |Propagation delay from current detection to gate
tILIM
−
100
150
ns| |off−state| |Maximum on−time
ton(MAX)
26
36
46
s
~~a~~| |Threshold for immediate fault protection activation
VCS(stop)
1.35
1.50
1.65
V
~~CO~~| |Leading Edge Blanking Duration for VCS(stop)
tBCS
−
150
−
ns
~~a~~| |Current source for CS to GND short detection
ICS(short)
400
500
600
A
Current sense threshold for CS to GND short de-
tection
VCSrising
VCS(low)
30
65
100
mV
~~a~~
~~GG OO~~| |**GATE DRIVE**| |Drive Resistance| |DRV Sink
RSNK
−
13
−| |DRV Source
RSRC
−
30
−| |Drive current capability
mA| |DRV Sink (Note 6)
ISNK
−
500
−| |DRV Source (Note 6)
ISRC
−
300
−| |Rise Time (10% to 90%)
CDRV= 470 pF
tr
–
40
−
ns
~~CC~~| |Fall Time (90% to 10%)
CDRV= 470 pF
tf
–
30
−
ns
DRV Low Voltage
VCC= VCC(off)+0.2 V
CDRV= 470 pF, RDRV=33 k
VDRV(low)
8
–
−
V
DRV High Voltage
VCC= VCC(MAX)
CDRV= 470 pF, RDRV=33 k
VDRV(high)
10
12
14
V
**ZERO VOLTAGE DETECTION CIRCUIT**
~~a~~
~~ee~~
~~ee ee~~
~~pe~~
~~et~~| |Upper ZCD threshold voltage
VZCDrising
VZCD(rising)
−
90
150
mV
~~CO~~| |Lower ZCD threshold voltage
VZCDfalling
VZCD(falling)
35
55
−
mV
~~a~~
~~CC~~| |ZCD hysteresis
VZCD(HYS)
15
−
−
mV
~~CO~~| |Propagation Delay from valley detection to DRV high
VZCDfalling
TDEM
−
100
300
ns
~~a~~| |Blanking delay after on−time
TZCD(blank1)
1.12
1.50
1.88
s
~~CO~~| |Timeout after last DEMAG transition
TTIMO
5.0
6.5
8.0
s
~~CO~~| |Pulling−down resistor
VZCD= VZCD(falling)
RZCD(PD)
−
200
−
k
~~a~~| |**CONSTANT CURRENT AND POWER FACTOR CONTROL**| |Reference Voltage at TJ= 25C
VREF
245
250
255
mV
~~CC~~| |Reference Voltage TJ= 25C to 100C
VREF
242.5
250.0
257.5
mV
~~CO~~| |Reference Voltage TJ= −40C to 125C
VREF
240
250
260
mV
~~CO~~| |Current sense lower threshold
VCSfalling
VCS(low)
20
55
100
mV
~~CC~~| |Vcontrolto current setpoint division ratio
Vratio
−
4
−
−
~~CO~~| |Error amplifier gain
VREFX=VREF
GEA
40
50
60
S
~~a~~| |Error amplifier current capability
VREFX=VREF
IEA
60
A
~~CO~~| |COMP Pin Start−up Current Source
COMP pin grounded
IEA_STUP
140
A
~~a~~| 6. Guaranteed by Design 7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation. 8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 s to avoid detecting an OTP fault by allowing the wu SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. **www.onsemi.com** **Share Feedback** Your Opinion Matters **6** ## **NCL30188** **Table 3. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V, VZCD = 0 V, VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V) |**FAULT PROTECTION**||||||| |---|---|---|---|---|---|---| |Thermal Shutdown (Note 6)
~~a~~|FSW= 65 kHz
~~a~~|TSHDN
~~a~~|130
~~a~~|150
~~a~~|170
~~a~~|C
~~a~~| |Thermal Shutdown Hysteresis|~~ee~~|TSHDN(HYS)|−|50|–|C| |Threshold voltage for output short circuit or
auxiliary winding short circuit detection
~~ee~~|~~ee~~
~~ee~~|VZCD(short)
~~ee~~|0.8
~~ee~~|1.0
~~ee~~|1.2
~~ee~~|V
~~ee~~| |Short circuit detection Timer
~~a~~|VZCD< VZCD(short)
~~ee~~
~~a~~|tOVLD
~~a~~|70
~~a~~|90
~~a~~|110
~~a~~|ms
~~a~~| |Auto−recovery timer duration
~~a~~|~~a~~|trecovery
~~a~~|3
~~a~~|4
~~a~~|5
~~a~~|s
~~a~~| |SD pin Clamp series resistor
~~a~~|~~a~~|RSD(clamp)
~~a~~|~~a~~|1.6
~~a~~|~~a~~|k
~~a~~| |Clamped voltage
~~a~~|SD pin open
~~a~~|VSD(clamp)
~~a~~|1.13
~~a~~|1.35
~~a~~|1.57
~~a~~|V
~~a~~| |SD pin detection level for OVP
~~a~~|VSDrising
~~a~~
~~ee~~|VOVP
~~a~~
~~ee~~|2.35
~~a~~
~~ee~~|2.50
~~a~~
~~ee~~|2.65
~~a~~|V
~~a~~| |Delay before OVP or OTP confirmation (OVP and
OTP)
~~ee~~|~~ee~~
~~ee~~
~~ee~~|TSD(delay)
~~ee~~
~~ee~~
~~ee~~|22.5
~~ee~~
~~ee~~
~~ee~~|30.0
~~ee~~
~~ee~~
~~ee~~|37.5
~~ee~~|s
~~ee~~| |Reference current for direct connection of an NTC
(Note 8)
~~ee~~|~~ee~~
~~ee~~
~~ee~~|IOTP(REF)
~~ee~~
~~ee~~
~~ee~~|80
~~ee~~
~~ee~~
~~ee~~|85
~~ee~~
~~ee~~
~~ee~~|90
~~ee~~|A
~~ee~~| |Fault detection level for OTP (Note 7)|VSDfalling
~~ee~~
~~ee~~|VOTP(off)
~~ee~~
~~ee~~|0.47
~~ee~~
~~ee~~|0.50
~~ee~~
~~ee~~|0.53|V| |SD pin level for operation recovery after an OTP
detection
~~ee~~|VSDrising
~~ee~~
~~ee~~
~~ee~~|VOTP(on)
~~ee~~
~~ee~~
~~ee~~|0.66
~~ee~~
~~ee~~
~~ee~~|0.70
~~ee~~
~~ee~~
~~ee~~|0.74
~~ee~~|V
~~ee~~| |OTP blanking time when circuit starts operating
(Note 8)
~~ee~~|~~ee~~
~~ee~~
~~ee~~|tOTP(start)
~~ee~~
~~ee~~
~~ee~~|250
~~ee~~
~~ee~~
~~ee~~|~~ee~~
~~ee~~
~~ee~~|370
~~ee~~|s
~~ee~~| |SD pin voltage at which thermal fold−back starts
(VREFis decreased)|~~ee~~|VTF(start)
~~ee~~|0.94
~~ee~~|1.00
~~ee~~|1.06|V| |SD pin voltage at which thermal fold−back stops
(VREFis clamped to VREF50)||VTF(stop)|0.64|0.69|0.74|V| |VTF(start)over IOTP(REF)ratio (Note 7)
~~a~~|TJ= +25C to +125C
~~a~~|RTF(start)
~~a~~|10.8
~~a~~|11.7
~~a~~|12.6
~~a~~|k
~~a~~| |VTF(stop)over IOTP(REF)ratio (Note 7)
~~a~~|TJ= +25C to +125C
~~a~~|RTF(stop)
~~a~~|7.4
~~a~~|8.1
~~a~~|8.8
~~a~~|k
~~a~~| |VOTP(off)over IOTP(REF)ratio (Note 7)
~~a~~|TJ= +25C to +125C
~~a~~|ROTP(off)
~~a~~|5.4
~~a~~|5.9
~~a~~|6.4
~~a~~|k
~~a~~| |VOTP(on)over IOTP(REF)ratio (Note 7)
~~a~~|TJ= +25C to +125C
~~a~~|ROTP(on)
~~a~~|7.5
~~a~~|8.1
~~a~~|8.7
~~a~~|k
~~a~~| |VREF@ VSD= 600 mV (SD pin falling no OTP
detection) (percent of VREF)
~~a~~|~~a~~|VREF(50)
~~a~~|40
~~a~~|50
~~a~~|60
~~a~~|%
~~a~~| 6. Guaranteed by Design 7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation. 8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 s to avoid detecting an OTP fault by allowing the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. **www.onsemi.com** **Share Feedback** Your Opinion Matters **7** **NCL30188** **Table 3. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V, VZCD = 0 V, VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V) **Description Test Condition Symbol Min Typ Max Unit** ~~GO~~ **BROWN−OUT** BO comparators delay tBO(delay) 30 s ~~a (nt (I I I CO~~ Brown−Out blanking time tBO(blank) 15 25 35 ms ~~a (I ( nD~~ VS pin Pulling−down Current ~~Dn~~ VS = VBO(on) ~~(DI~~ IBO(bias) 50 250 ~~I~~ 450 ~~I~~ nA 6. Guaranteed by Design 7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation. 8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 s to avoid detecting an OTP fault by allowing the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. ## **TYPICAL CHARACTERISTICS** **==> picture [489 x 382] intentionally omitted <==** **----- Start of picture text -----**
20.0 9.4
9.3
19.5
9.2
19.0 9.1
PEPPER 9.0 GEEEEEEE
18.5
8.9
18.0 8.8
17.5 a 8.7
8.6
17.0 8.5
16.5 PERERA 8.4 BEEEEEEE
8.3
16.0 TP 8.2 eee
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
Figure 4. VCC Start−up Threshold vs. Figure 5. VCC Minimum Operating Voltage vs.
Temperature Temperature
11.5 6.0
ToL LLLL 5.8 fee
11.0
5.6
10.5
5.4
P|} SSS
10.0
5.2
9.5 5.0
9.0 ECEEEECE| a a 4.8 aEEREEEREee ee ee ee ee
4.6
8.5
4.4
SPEER) EEE EERE
8.0
4.2
7.5 TEE 4.0 Ee
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
(V) (V)
CC(on) CC(off)
V V
(V) (V)
CC(hys) CC(reset)
V V
**----- End of picture text -----**
**Figure 6. Hysteresis (VCC(on) − VCC(off)) vs. Temperature** **Figure 7. VCC(reset) vs. Temperature** **www.onsemi.com 8** ~~—~~ **Share Feedback** Your Opinion Matters **NCL30188** ## **TYPICAL CHARACTERISTICS** **==> picture [243 x 366] intentionally omitted <==** **----- Start of picture text -----**
28.0
27.8
ee
A
27.627.4 A
a
27.2
a a
A
27.0
26.8 a OO
26.6
ee ee ee
26.4
TLL LL
OO
26.2
a
26.0
a ee
OO
25.8
25.6 oT Eo
−50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
Figure 8. VCC Over Voltage Protection
Threshold vs. Temperature
150
125
100
oa 75 ee
50 Fs
25
0
−50 −25 0 25 50 75 100 125 150
(V)
CC(ovp)
V
A)
(
ICC(sfault)
**----- End of picture text -----**
**==> picture [133 x 9] intentionally omitted <==** **----- Start of picture text -----**
TJ, JUNCTION TEMPERATURE (C)
**----- End of picture text -----**
**Figure 10. Start−up Current in Fault Mode vs. Temperature** **==> picture [238 x 173] intentionally omitted <==** **----- Start of picture text -----**
4035 P| | | | | | ft
30
P| | | | [| | ft
25 P| | | | f ff
2015 —— P|P| || || —|| [|[| fffeeee |
+—
10
| dT
5 P| | | | [| ff
0 P| | | | | | ff
−50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
A)
(
ICC(start)
**----- End of picture text -----**
**Figure 9. Start−up Current vs. Temperature** **==> picture [239 x 156] intentionally omitted <==** **----- Start of picture text -----**
2.0
1.8
1.6
1.4
1.2 EES
1.0
0.8
0.6
0.4
−50 −25 0 25 50 75 100 125 150
(mA)
ICC1
**----- End of picture text -----**
**==> picture [133 x 9] intentionally omitted <==** **----- Start of picture text -----**
TJ, JUNCTION TEMPERATURE (C)
**----- End of picture text -----**
**Figure 11. ICC1 vs. Temperature** **==> picture [490 x 188] intentionally omitted <==** **----- Start of picture text -----**
3.8 5.0
3.6
fFa{| ffA { f ff 4.5 rT | | | | [| | ft
3.4
3.2 sO 4.0 fF | | | J ft ft
3.0
2.8 sOee ee 3.5 P| | | | [| | ft
2.6
a 3.0 P| | | | ft | ft
2.4 ee ee ee ee ee ee
2.2 a 2.5 ee
2.0
1.8 }_{ee _} ff { —} 2.0 Pt | fF ft tf
1.6
a OO 1.5 P| | Ff ft ff
1.4
1.2 ee————— 1.0 P| | | | [| | ft
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
Figure 12. ICC2 vs. Temperature Figure 13. ICC3 vs. Temperature
(mA) (mA)
ICC2 ICC3
**----- End of picture text -----**
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1.051.04 ee ee ee ee
1.03 ee
1.02 ee ee e e
1.01 ee ee e e
1.00 ee ee e e
0.99 a
0.98 mt eee
0.970.950.96 aaa | eeee|eeeeee| | ee[| fyee ee
−50 −25 0 25 50 75 100 125 150
(V)
ILIM
V
**----- End of picture text -----**
TJ, JUNCTION TEMPERATURE (C) **Figure 14. Maximum Internal Current Limit vs. Temperature** **==> picture [238 x 156] intentionally omitted <==** **----- Start of picture text -----**
400380 PF | fl
360 EE
340 P| tf EE
320 P| tf EE
300 P|atf EE
280 ee
260 a ee
240220 P|P|Pt tTtTtfEEEEEE
200 a eeee
−50 −25 0 25 50 75 100 125 150
(ns)
LEB
T
**----- End of picture text -----**
TJ, JUNCTION TEMPERATURE (C) **Figure 15. Leading Edge Blanking vs. Temperature** **==> picture [490 x 381] intentionally omitted <==** **----- Start of picture text -----**
150 50
140 a a 48 a
130
120 46
110 a
44
100
90 42
80 ee
40
70
60 38
50 ee
36
40
30 34
20 pe ps
32
10
0 30
- +} + a
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
Figure 16. Current Limit Propagation Delay vs. Figure 17. Maximum On−time vs. Temperature
Temperature
1.581.60 ee ee 220210 a ee
1.56 ae e e 200 ae ee ee ee
ee 190 ee ee ee eeeee
1.54
es 180 ee ee ee eeeee
1.52
ee 170 ee ee ee ee ee ee
1.50
ee ee ee a
160
1.48 PTE 150 a ee
1.46 ee ee
140
a ee ee a
1.44 ee ee eee 130 a
1.42 120
1.40 110
1.38 BEERee ERRee R Y 100 EER EEEEE
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
s)
(
(ns)
ILIM
T ON(max)
T
(V)
(ns)
BCS
CS(stop) T
V
**----- End of picture text -----**
**Figure 18. VCS(stop) vs. Temperature** **Figure 19. Leading Edge Blanking Duration for VCS(stop) vs. Temperature** **www.onsemi.com** **Share Feedback** Your Opinion Matters **10** **NCL30188** ## **TYPICAL CHARACTERISTICS** **==> picture [489 x 366] intentionally omitted <==** **----- Start of picture text -----**
600 100
580 Pot JT [ JT yt yy] 90 rT | | J Jfff]
560
PF | | | cf | 80 ry TUT UU
540
a 520 PfA OO OOff pee f 4 70 Pf[|| | ffa a ffeee
500 | 60
480
eee 50 P| [| | | | | ff
460
40
a
440
ee 30 P| | | ff
420
400 ee 20 | | | | | |ff| ft |
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
Figure 20. ICS(short) vs. Temperature Figure 21. VCS(low), VCS Rising vs.
Temperature
20 40
38
18
36
16 Ff [| | tf ft ff 34 a ee ee
32
14
30
12 28
26 el —_|
10 24 a es es
8 eee 22 eeeeee ee ee ee
20
6
| |feeLifeeLiLi 18 ee
4 H+; | | | [| | | 16 a
14
20 eeaa 1012 Jaa
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
A)
( (mV)
ICS(short) VCS(low)
) )
( (
SNK SRC
R R
**----- End of picture text -----**
**==> picture [490 x 382] intentionally omitted <==** **----- Start of picture text -----**
20 40
38
18
36
16 Ff [| | tf ft ff 34 a ee ee
32
14
30
12 28
26 el —_|
10 24 a es es
8 eee 22 eeeeee ee ee ee
20
6
| |feeLifeeLiLi 18 ee
4 H+; | | | [| | | 16 a
14
12
020 eeaa 1012 Jaa
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
Figure 22. Sink Gate Drive Resistance vs. Figure 23. Source Gate Drive Resistance vs.
Temperature Temperature
455040 ToteeJT ee| fT eeyt tT 7 504540 ToteetT ee| fT eeyt yt
ee ee ee ee ee
35 ee ee ee 35 ee ee
30 ee ee ee 30 ee ee
25 25
2015 eeeee ee ee 1520 eeee ee
10 ne ee 10 -—+—-—ee
ee | | | [| | |
5 5
0 | | | ee| Ff eeft ff 0 |ee| | ee| tf eeff fl
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
) )
( (
SNK SRC
R R
(ns)tr (ns)tF
**----- End of picture text -----**
**Figure 24. Gate Drive Rise Time vs. Temperature** **==> picture [139 x 20] intentionally omitted <==** **----- Start of picture text -----**
Figure 25. Gate Drive Fall Time
(CDRV = 470 pF) vs. Temperature
**----- End of picture text -----**
**www.onsemi.com** **Share Feedback** Your Opinion Matters **11** **NCL30188** ## **TYPICAL CHARACTERISTICS** **==> picture [489 x 173] intentionally omitted <==** **----- Start of picture text -----**
9.8 15.0
9.6 PF | Jf J fo f ff] 14.5 PF | | | fF ff
14.0
9.4 Ty oF oT UE UT TS a ee ee
13.5
PEPE
9.2
9.0 | | | e y 12.513.0 aKe SS
12.0
8.8 ee eee | |
11.5
8.6 Pf [ | | ft ft ce
11.0
e e
8.4
10.5
8.2 | ft | | | | ft | 10.0 aeea eeee
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
(V) (V)
DRV(low) DRV(high)
V V
**----- End of picture text -----**
**Figure 26. DRV Low Voltage vs. Temperature** **Figure 27. DRV High Voltage vs. Temperature** **==> picture [490 x 157] intentionally omitted <==** **----- Start of picture text -----**
150140 Os 8075
130
70
120
65
110 Os
100 Se 60 re
90 55
80 aSees 50 Cee
70 ee ee ee 45 es ee
60
40
50 Os
40 Os 35 ee
30 Ss 30 | | {| | | | [| [| |
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
(mV) (mV)
ZCD(rising) ZCD(falling)
V V
**----- End of picture text -----**
TJ, JUNCTION TEMPERATURE (C) **Figure 28. Upper ZCD Threshold Voltage vs. Temperature** **==> picture [133 x 9] intentionally omitted <==** **----- Start of picture text -----**
TJ, JUNCTION TEMPERATURE (C)
**----- End of picture text -----**
**Figure 29. Lower ZCD Threshold vs. Temperature** **==> picture [490 x 172] intentionally omitted <==** **----- Start of picture text -----**
4550 a ee e 2.01.9 FP | | fl
40 PF 1.8 EE
35 PF | | fl ft 1.7 ee
30 FP | | ct rE 1.6 ee
| | | | | | | | =z pot of of | dT
ee ee -—+——__+—+
2025 PF | | ct rE 1.51.4 PF | | ff
15 PF | | ct rE 1.3 PF | | tf flET
10 PF | | [| | [| | ff 1.2 PF | | tf flTT
5 PF | | | fF ff 1.1 PF | | tf flTT
0 | | {| | | | [ {[ | 1.0 | | {| | |TT| [| [ |
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
s)
(
(mV)
VZCD(HYS) tZCD(blank1)
**----- End of picture text -----**
**Figure 30. ZCD Hysteresis vs. Temperature** **Figure 31. ZCD Blanking Delay vs. Temperature** **www.onsemi.com** **Share Feedback** Your Opinion Matters **12** **NCL30188** ## **TYPICAL CHARACTERISTICS** **==> picture [242 x 173] intentionally omitted <==** **----- Start of picture text -----**
7.8
7.6
7.4
7.2
7.0
~ 6.8 { | | | | | ft ff
6.6
6.4 ee ee ee
6.2
6.0
5.8
−50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
s)
(
TIMO
T
**----- End of picture text -----**
**Figure 32. ZCD Time−out vs. Temperature** **==> picture [238 x 173] intentionally omitted <==** **----- Start of picture text -----**
256
255
254
253
252
251
250 a
249
248
ee
247
246
245
244
−50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
(mV)
REF
V
**----- End of picture text -----**
**Figure 33. Reference Voltage vs. Temperature** **==> picture [243 x 156] intentionally omitted <==** **----- Start of picture text -----**
110
100
90
80
70
60 a
50 ——
40
po | | | ft
30
20
10
−50 −25 0 25 50 75 100 125 150
(mV)
CS(low)
V
**----- End of picture text -----**
**==> picture [133 x 9] intentionally omitted <==** **----- Start of picture text -----**
TJ, JUNCTION TEMPERATURE (C)
**----- End of picture text -----**
**Figure 34. Current Sense Lower Threshold (VCS Falling) vs. Temperature** **==> picture [239 x 156] intentionally omitted <==** **----- Start of picture text -----**
60
58
56
54
52
50
ee eeeee
48
pf i} ft ft jt ft
46
44
42
−50 −25 0 25 50 75 100 125 150
S)
(
EA
G
**----- End of picture text -----**
**==> picture [133 x 9] intentionally omitted <==** **----- Start of picture text -----**
TJ, JUNCTION TEMPERATURE (C)
**----- End of picture text -----**
**Figure 35. Error Amplifier Trans−conductance Gain vs. Temperature** **==> picture [490 x 172] intentionally omitted <==** **----- Start of picture text -----**
22.0 44
21.5 43
21.0 42
20.5 41
20.0 40
So ee
19.5 39
Oa ee———_— | &+| .°»4| ee = ee|__ eeee —
19.0 38
18.5 37
18.0 36
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
S)
A)
(
(
KLFF IFF
**----- End of picture text -----**
**Figure 36. Feedforward VVS to ICS(offset) Conversion Ratio vs. Temperature** **Figure 37. Line Feedforward Current on CS Pin (@ VVS = 2 V) vs. Temperature** **www.onsemi.com** **Share Feedback** Your Opinion Matters **13** **NCL30188** ## **TYPICAL CHARACTERISTICS** **==> picture [242 x 156] intentionally omitted <==** **----- Start of picture text -----**
120
115
110
105
100
95 eee
90
85
80
−50 −25 0 25 50 75 100 125 150
A)
(
Ioffset(MAX)
**----- End of picture text -----**
**==> picture [133 x 9] intentionally omitted <==** **----- Start of picture text -----**
TJ, JUNCTION TEMPERATURE (C)
**----- End of picture text -----**
**Figure 38. Ioffset(MAX) vs. Temperature** **==> picture [243 x 156] intentionally omitted <==** **----- Start of picture text -----**
2.60
2.55
2.50
2.45
2.40
2.35
fF | | | | | ff
ee
2.30
2.25 fo
2.20
−50 −25 0 25 50 75 100 125 150
(V)
LL
V
**----- End of picture text -----**
**==> picture [133 x 9] intentionally omitted <==** **----- Start of picture text -----**
TJ, JUNCTION TEMPERATURE (C)
**----- End of picture text -----**
**Figure 40. Threshold for Low−line Range Detection vs. Temperature** **==> picture [243 x 172] intentionally omitted <==** **----- Start of picture text -----**
1.20
1.15
1.10
1.05
0.950.901.00 fFa| | | [| | jf ff
0.85
0.80
−50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
(V)
ZCD(short)
V
**----- End of picture text -----**
**Figure 42. Threshold Voltage for Output Short Circuit Detection vs. Temperature** **==> picture [238 x 156] intentionally omitted <==** **----- Start of picture text -----**
2.55
2.50
2.45
2.40 [| 7 Ti
2.35
2.30
2.25
−50 −25 0 25 50 75 100 125 150
(V)
HL
V
**----- End of picture text -----**
TJ, JUNCTION TEMPERATURE (C) **Figure 39. Threshold for High−line Range Detection vs. Temperature** **==> picture [239 x 382] intentionally omitted <==** **----- Start of picture text -----**
40
38
36
34
32
30
28
26 a
—
24
22 ee ee ee
20
−50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
Figure 41. Blanking Time for Low−line Range
Detection vs. Temperature
115
110
105
100
959085 |fF || || || 7[| || fT| [[fff
80
75
−50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
(ms)
HL(blank)
T
(ms)
tOVLD
**----- End of picture text -----**
**Figure 43. Short Circuit Detection Timer vs. Temperature** **www.onsemi.com** **Share Feedback** Your Opinion Matters **14** **NCL30188** ## **TYPICAL CHARACTERISTICS** **==> picture [489 x 173] intentionally omitted <==** **----- Start of picture text -----**
5.00 2.20
2.10
4.75 Pf | | fF ft ft pj of if of of ff
2.00
4.50 Pf | | | ft | ft 1.90 a
1.80
4.25 e e e
1.70
4.00 > HH C T 1.60 a
ee 1.50 Sa
3.75
1.40
3.50 P| 1.30 a
1.20
3.25 P| | | |tf ft f ft a
1.10
3.00 P| | | tf ft ff 1.00 a
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
)
(s) (k
recovery
T SD(clamp)
R
**----- End of picture text -----**
**Figure 44. Auto−recovery Timer Duration vs. Temperature** **Figure 45. SD Pin Clamp Series Resistor vs. Temperature** **==> picture [490 x 382] intentionally omitted <==** **----- Start of picture text -----**
1.60 2.58
1.55 PF | [| tf tf ff 2.56 | | [| | | | | | |
1.50 2.54
1.45 PF | [| ft eeee
1.40 PF | [| ft 2.52
2.50
1.35 e e
i 2.48 eS
1.30 TT Td ee
1.25 es 2.46 ee
i es 2.44 ee a ee
1.20
1.15 a ee 2.42 | | | | | | fT |
1.10 ee e e eee ee 2.40 PFFf| | [|| ftjf f t fft ff
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
Figure 46. SD Pin Clamp Voltage vs. Figure 47. SD Pin OVP Threshold Voltage vs.
Temperature Temperature
38 91
90
ee PLL LLL LL
36
89
34 P| 88 a
87
32 P| || [|| || ftf ffff a——————
86
30 85
84
28 P| | | | [| | 7 eeee eee
83
26 P| 82 gO
81
24 P| | [| | f t ff| ft a ee
80
22 P| | | ft tf ff 79 a
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
(V)
(V)
OVP
V
SD(clamp)
V
s) A)
( (
TSD(delay) IOTP(REF)
**----- End of picture text -----**
**Figure 48. TSD(delay) vs. Temperature** **Figure 49. IOTP(REF) vs. Temperature** **www.onsemi.com** **Share Feedback** Your Opinion Matters **15** **NCL30188** ## **TYPICAL CHARACTERISTICS** **==> picture [242 x 173] intentionally omitted <==** **----- Start of picture text -----**
12.5
12.4 sO
12.3 es
12.2
Ds sO
12.1
A Cs
12.0
a 11.9 a ee ee ee
11.8 a ee
a ee ee
11.7
11.6
a Cs
11.5
11.4 ee ee ee ee ee ee
11.3 a ee
11.2
11.011.1 a(sOa sO
−50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
)
(k
TF(start)
R
**----- End of picture text -----**
**Figure 50. RTF(start) vs. Temperature** **==> picture [238 x 173] intentionally omitted <==** **----- Start of picture text -----**
8.88.78.6 aa esse es
8.5 es
es
8.4
a
8.28.3 aaeei eeeeee eeee oeeeeeee
8.1
Pf PTee ee ee
8.07.9 eea eeeeee ee ee
7.8
7.7 es
7.6 a ee
−50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
)
(k
TF(stop)
R
**----- End of picture text -----**
**Figure 51. RTF(stop) vs. Temperature** **==> picture [490 x 382] intentionally omitted <==** **----- Start of picture text -----**
6.46.3 rT | | | Jf | fff 8.88.7 aeeeee e e
8.6
6.2
e e
8.5
6.1 a a a a a e e 8.4 ee
eo 6.0 Lf | ff te 8.3
5.9 —| ye) eg 8.2
5.8 a | | | | 8.1 ee eeee
5.7 os ee ee ee 8.0 aee
7.9
a ee ee e e
5.6
7.8
5.5 po | | a fta a | 7.7 a
5.4 ee ee 7.6 a
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
Figure 52. ROTP(off) vs. Temperature Figure 53. ROTP(on) vs. Temperature
55 a ee eee 1.05 a eee
54 a ee eee 1.04 a eee
53 1.03
5251 aa eeee eeee 1.021.01 aa eeee eeeeee
50 ee ee 1.00 a ee eee
49 a 0.99 ||
48 a ee ee 0.98 oesee
47 a ee ee 0.97 a ee e e ee
46 a ee ee ee 0.96 a ee ee
45 Pt | EE 0.95 eeee
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
) )
(k (k
OTP(off) OTP(on)
R R
(%) (V)
VREF(50) VBO(on)
**----- End of picture text -----**
**Figure 54. Ratio VREF(50) over VREF vs. Temperature** **Figure 55. Brown−out ON Level vs. Temperature** **www.onsemi.com** **Share Feedback** Your Opinion Matters **16** **NCL30188** ## **TYPICAL CHARACTERISTICS** **==> picture [489 x 173] intentionally omitted <==** **----- Start of picture text -----**
0.95 35
Te 34
0.94
0.93 ee ee e e 3332 a a
31
0.920.91 Teeee ee e e 2930 aeeea
28
0.90 ee
0.89 —rT | | | | [| ft | 2726 a
25
0.88
24
Teer | 6
0.87 a ee ee e e 23 a
22
0.86
0.85 a ee 2021 a
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
(V) (ms)
BO(off)
V
tBO(blank)
**----- End of picture text -----**
**Figure 56. Brown−out OFF Level vs. Temperature** **Figure 57. Brown−out Blanking Time vs. Temperature** **==> picture [243 x 172] intentionally omitted <==** **----- Start of picture text -----**
500 a
450 a a
400 aa
350 a
300
250 PF oT | a |
150100200500 foP|P|P|a ee|||EEEEEE
−50 −25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
(nA)
IBO(bias)
**----- End of picture text -----**
**Figure 58. VS Pin Pulling−down Current vs. Temperature** **www.onsemi.com 17** ~~oo~~ **Share Feedback** Your Opinion Matters **NCL30188** ## **Application Information** The NCL30188 is a driver for power−factor corrected flyback and non−isolated buck−boost and SEPIC converters. Its current−mode, quasi−resonant architecture optimizes the efficiency by turning on the MOSFET when its drain−source voltage is minimal (valley). At high line, the circuit delays the MOSFET turn on until the second valley is detected to reduce the switching losses. A proprietary circuitry ensures both accurate regulation of the output current (without the need for a secondary−side feedback) and near−unity power factor correction. The circuit contains a suite of powerful protections to ensure a robust LED driver design without the need for extra components or overdesign. - **Quasi−Resonance Current−Mode Operation:** implementing quasi−resonance operation in peak current−mode control, the NCL30188 optimizes the efficiency by turning on the MOSFET when its drain−source voltage is minimal (valley). In light−load conditions, the circuit changes valleys to reduce the switching losses. For stable operation, the valley at which the MOSFET switches on remains locked until the input voltage or the output current set−point significantly changes. - **Primary−Side Constant−Current Control with Power Factor Correction:** a proprietary circuitry allows the LED driver to achieve both near−unity power factor correction and accurate regulation of the output current without requiring any secondary−side feedback (no optocoupler needed). A power factor as high as 0.99 and an output current deviation below  2% are typically obtained. - **Main protection features:** - **Over Temperature Thermal Fold−back / Shutdown/ Over Voltage Protection:** the NCL30188 features a gradual current foldback to protect the driver from excessive temperature down to 50% of the programmed current. This represents a power reduction of the LED by more than 50%. If the temperature continues to rise after this point to a second level, the controller stops operating. This mode would only be expected to be reached if there is a severe fault. The first and second temperature thresholds depend on the value of the NTC connected to the SD pin. Note, the SD pin can also be used to shutdown the device by pulling this pin below the V min level . A Zener diode can OTP(off) also be used to pull−up the pin and stop the controller for adjustable OVP protection. Both protections are latching−off (A version) or auto−recovery (the circuit can recover operation after 4−s delay has elapsed − B version). - **Cycle−by−cycle peak current limit:** when the current sense voltage exceeds the internal threshold VILIM, the MOSFET is immediately turned off (cycle−by−cycle current limitation). - **Winding or Output Diode Short−Circuit Protection:** an additional comparator senses the CS signal and stops the controller if it exceeds 150% x VILIM for 4 consecutive cycles. This feature can protect the converter if a winding is shorted or if the output diode is shorted or simply if the transformer saturates. This protection is latching−off (A version) or auto−recovery (B version). - **Output Short−circuit protection:** if the ZCD pin voltage remains low for a 90−ms time interval, the controller detects that the output or the ZCD pin is grounded and hence, stops operation. This protection is latching−off (A version) or auto−recovery (B version). - **Open LED protection:** if the VCC pin voltage exceeds the OVP threshold, the controller shuts down and waits 4 seconds before restarting switching operation. - **Floating or Short Pin Detection:** the circuit can detect most of these situations which helps pass safety tests. ## **Power Factor and Constant Current Control** The NCL30188 embeds an analog/digital block to control the power factor and regulate the output current by monitoring the ZCD, VS and CS pin voltages (signals ZCD, VS and VCS of Figure 59). This circuitry generates the current setpoint (VCONTROL/4) and compares it to the current sense signal (VCS) to dictate the MOSFET turning off event when VCS exceeds VCONTROL/4. **==> picture [346 x 107] intentionally omitted <==** **----- Start of picture text -----**
ZCD STOP VVS VREFX
VCS Power Factor and PWM Latch reset
Constant−Current
Control
COMP
__________ {} C1
**----- End of picture text -----**
**Figure 59. Power Factor and Constant−Current Control** **www.onsemi.com 18** ~~—~~ **Share Feedback** Your Opinion Matters **NCL30188** As illustrated in Figure 59, the VS pin provides the sinusoidal reference necessary for shaping the input current. The obtained current reference is further modulated so that when averaged over a half−line period, it is equal to the output current reference (VREFX). This averaging process is made by an internal Operational Trans−conductance Amplifier (OTA) and the capacitor connected to the COMP pin (C1 of Figure 59). Typical COMP capacitance is 1 F u and should not be less than 470 nF to ensure stability. The COMP ripple does not affect the power factor performance as the circuit digitally eliminates it when generating the current setpoint. If the VS pin properly conveys the sinusoidal shape, power factor will be close to unity and the Total Harmonic Distortion (THD) will be low. In any case, the output current will be well regulated following the equation below: **==> picture [213 x 23] intentionally omitted <==** Where: - NPS is the secondary to primary transformer turns NPS = NS/NP. NPS is 1 in the case of non−isolated buck−boost or SEPIC converter. - Rsense is the current sense resistor (see Figure 1). - VREFX is the output current internal reference. VREFX = VREF (250 mV, typically) at full load. The output current reference (VREFX) is VREF unless the temperature is high enough to activate the thermal fold−back (see “protections” section). If a major fault is detected, the circuit enters the latched−off or auto−recovery mode and the COMP pin is grounded (except in an UVLO condition). This ensures a clean start−up when the circuit resumes operation. ## **Start−up Sequence** Generally an LED lamp is expected to emit light in < 1 sec and typically within 300 ms. The start−up phase consists of the time to charge the VCC capacitor, begin switching and the time to charge the output capacitor until sufficient current flows into the LED string. To speed−up this phase, the following defines the start−up sequence: - The COMP pin is grounded when the circuit is off. The average COMP voltage needs to exceed the VS pin peak value to have the LED current properly regulated (whatever the current target is). To speed−up the COMP capacitance charge and shorten the start−up phase, an internal 80−A current source adds to the OTA sourced u current (60 A max typically) to charge up the COMP u capacitance. The 80−A current source remains on until u the OTA starts to sink current as a result of the COMP pin voltage sufficient rise. At that moment, the COMP pin being near its steady−state value, it is only driven by the OTA. - If VCC drops below the VCC(off) threshold because the circuit fails to start−up properly on the first attempt, a new try takes place as soon as VCC is recharged to VCC(on). The COMP voltage is not reset at that moment. Instead, the new attempt starts with the COMP level obtained at the end of the previous operating phase. - If the load is shorted, the circuit will operate in hiccup mode with VCC oscillating between VCC(off) and VCC(on) until the AUX_SCP protection trips (AUX_SCP is triggered if the ZCD pin voltage does not exceed 1 V within a 90−ms operation period of time thus indicating a short to ground of the ZCD pin or an excessive load preventing the output voltage from rising). The NCL30188A latches off in this case. With the B version, the AUX_SCP protection forces the 4−s auto−recovery delay to reduce the operation duty−ratio. Figure 60 illustrates a start−up sequence with the output shorted to ground, in this second case. **www.onsemi.com** **Share Feedback** Your Opinion Matters **19** **NCL30188** **==> picture [441 x 225] intentionally omitted <==** **----- Start of picture text -----**
V
eece eeede pe eee CC(on) eel Ld eeebe
VCC
i\ i\ i V ii\ i \ ii ii
CC(off)
ii ii i iii ii il ii
ii ii i iii ii il ii
ii ii i iii ii il ii
ii i i iii i i ii
ii i i  itl i i  ii
ii i i iii ii il i
i i i it i i ii
time
AUX_SCPtrips
tl tl Vl tol tl VI Vl
as t 1  t 2  t 3  tOVLD
DRV  tOVLD = 90 ms 
[t] 1 ii iti [t] 3 [t] 1 iii ii [t] 3 1 i time ,
[t] 2 [t] 2
ii HE ii ii i HE i ii
trecovery  s  trecovery  s 
**----- End of picture text -----**
**Figure 60. Start−up Sequence in a Load Short−circuit Situation (auto−recovery version)** ## **Zero Crossing Detection Block** The ZCD pin detects when the drain−source voltage of the power MOSFET reaches a valley by crossing below the 55−mV internal threshold. At startup or in case of extremely damped free oscillations, the ZCD comparator may not be able to detect the valleys. To avoid such a situation, the NCL30188 features a time−out circuit that generates pulses if the voltage on ZCD pin stays below the 55−mV threshold for 6.5 u s. The time−out also acts as a substitute clock for the valley detection and simulates a missing valley in case the free oscillations are too damped. **Figure 61. Zero Current Detection Block** **www.onsemi.com** **Share Feedback** Your Opinion Matters **20** **NCL30188** If the ZCD pin or the auxiliary winding happen to be shorted, the time−out function would normally make the controller keep switching and hence lead to improper LED current value. The “AUX_SCP” protection prevents such a stressful operation: a secondary timer starts counting that is only reset when the ZCD voltage exceeds the VZCD(short) threshold (1 V typically). If this timer reaches 90 ms (no ZCD voltage pulse having exceeded VZCD(short) for this time period), the controller detects a fault and stops operation for 4 seconds (B version) or latches off (A version). The “clock” shown in Figure 61 is used by the “valley selection frequency foldback” circuitry of the block diagram (Figure 3), to generate the next DRV pulse (if no fault prevents it): - Immediately when the clock occurs in QR mode at low line or valley 2 at high line (full load) - After the appropriate number of “clock” pulses in thermal foldback mode **For an optimal operation, the maximum ZCD level should be maintained below 5 V to stay safely below the built in clamping voltage of the pin.** ## **Line Range Detection** As sketched in Figure 62, this circuit detects the low−line range if the VS pin remains below the VLL threshold (2.3 V typical) for more than the 25−ms blanking time. High−line is detected as soon as the VS pin voltage exceeds VHL (2.4 V typical). These levels roughly correspond to 184−V rms and 192−V rms line voltages if the external resistors divider applied to the VS pin is designed to provide a 1−V peak value at 80 V rms. **Figure 62. Line Range Detection** In the low-line range, conduction losses are generally dominant. Adding a dead-time would further increase these losses. Hence, only a short dead-time is necessary to reach the MOSFET valley. In high-line conditions, switching losses generally are the most critical. It is thus efficient to skip one valley to lower the switching frequency. Hence, under normal operation, the NCL30188 optimizes the efficiency over the line range by turning on the MOSFET at the first valley in low-line conditions and at the second valley in the high-line case. This is illustrated by Figure 63 that sketches the MOSFET Drain-source voltage in both cases. In the event that thermal foldback is activated, additional valleys can be skipped as the power is reduced. **Figure 63. Full−load Operation − Quasi−resonant Mode in low line (left), turn on at valley 2 when in high line (right)** ## **Line Feedforward** As illustrated by Figure 64, the input voltage is sensed by the VS pin and converted into a current. By adding an external resistor in series between the sense resistor and the CS pin, a voltage offset proportional to the input voltage is added to the CS signal for the MOSFET on−time. **www.onsemi.com** **Share Feedback** Your Opinion Matters **21** **NCL30188** **==> picture [285 x 118] intentionally omitted <==** **----- Start of picture text -----**
Bulk rail
vDD
|
VS
i;
I CS(offset) CS RCS
Rsense
pO Q_drv ee ee
**----- End of picture text -----**
**Figure 64. Line Feed−Forward Schematic** In Figure 64, Q_drv designates the output of the PWM latch which is high for the on−time and low otherwise. ## **Protections** The circuit incorporates a large variety of protections to make the LED driver very rugged. Among them, we can list: ## **Output Short Circuit Situation** An overload fault is detected if the ZCD pin voltage remains below VZCD(short) for 90 ms. In such a situation, the circuit stops generating pulses until the 4−s delay auto−recovery time has elapsed (B version) or latches off (A version). ## **Winding or Output Diode Short Circuit Protection** If a transformer winding happens to be shorted, the primary inductance will collapse leading the current to ramp up in a very abrupt manner. The VILIM comparator (current limitation threshold) will trip to open the MOSFET and eventually stop the current rise. However, because of the abnormally steep slope of the current, internal propagation delays and the MOSFET turn−off time will make possible the current rise up to 50% or more of the nominal maximum value set by VILIM. As illustrated in Figure 65, the circuit uses this current overshoot to detect a winding short circuit. The leading edge blanking (LEB) time for short circuit protection (LEB2) is significantly faster than the LEB time for cycle−by−cycle protection (LEB1). Practically, if four consecutive switching periods lead the CS pin voltage to exceed (VCS(stop)=150% *VILIM), the NCL30188B enters the auto−recovery mode (4−s interruption of operation between the active bursts) while the NCL30188A latches off the LED driver until it is reset. Similarly, this function can also protect the power supply if the output diode is shorted or if the transformer simply saturates. **==> picture [490 x 222] intentionally omitted <==** **----- Start of picture text -----**
S
Q DRV Vdd UVLO aux
Q
TSD
CS R BONOK Vcc VCC
LEB1 + PWMreset UVLO management
Vcontrol / 4 −
latch
4−s timer VCCreset
Nine + Ipkmax pA STOP a (grandreset)
−
: «Lf
VILIMIT
AUX_SCP
SD Pin OVP
= LEB2 + WOD_SCP 4−pulse (OVP2) VCC(ovp) —>
counter
−
>t} OTP =
VCS(stop) S OFF S latch
Q Q
Q Q
AUTO−RECOVERY LATCHING−OFF
R (NCL30188B) R (NCL30188A)
4−s timer VCCreset
**----- End of picture text -----**
**Figure 65. Winding Short Circuit Protection, Max. Peak Current Limit Circuits** **www.onsemi.comonsemi.com 22** ~~——~~ **www.onsemi.comonsemi.com 22** **Share Feedback** Your Opinion Matters **NCL30188** ## **VCC Over Voltage Protection** The circuit stops generating pulses if VCC exceeds VCC(OVP) and enters auto−recovery mode. This feature protects the circuit if the output LED string happens to open or is disconnected. ## **Programmable Over Voltage Protection (OVP2)** Connect a Zener diode between VCC and the SD pin to set a programmable VCC OVP (DZ of Figure 66). The triggering level is (VZ+VOVP) where VOVP is the 2.5−V internal threshold. If this protection trips, the NCL30188A latches off while the NCL30188B enters the auto−recovery mode (see Figure 66). **==> picture [402 x 317] intentionally omitted <==** **----- Start of picture text -----**
Vdd
NCL30188B
IOTP(REF) SD Pin OVP (OVP2) DETECTION (auto−recovery version)
S
(c o + e P L Q . OFF
VCC − Q
VOVP
DZ TSD(delay) R
SD
4−s Timer
OTP DETECTION
i NTC Tbe, [ia
NCP30188A
TOTP(start) (latching−off version)
VOTP(off) / VOTP(on)
S
Q Latch
Q
Thermal VTF R
Foldback
=
grand reset
Rclamp
Vclamp
|
Clamp
−
+
**----- End of picture text -----**
## **Figure 66. Thermal Foldback and OVP/OTP Circuitry** **==> picture [236 x 106] intentionally omitted <==** typically, to trigger the OVP protection. This current helps ensure an accurate detection by using the Zener diode far from its knee region. ## **Programmable Over Temperature Foldback Protection (OTP)** Connect an NTC between the SD pin and ground to detect an over−temperature condition. In response to a high temperature (detected if VSD drops below VTF(start)), the circuit gradually reduces the LED current down 50% of its nominal value when VSD reaches VTF(stop), in accordance with the characteristic of Figure 67. If this thermal foldback cannot prevent the temperature from rising (testified by VSD drop below VOTP), the circuit latches off (NCL30188A) or enters auto−recovery mode (NCL30188B) and cannot resume operation until VSD exceeds VOTP(on) to provide some temperature hysteresis (around 10  C typically). The OTP thresholds nearly correspond to the following resistances of the NTC: - Thermal foldback starts when RNTC  RTF(start) - (11.7 k typically) - Thermal foldback stops when RNTC  RTF(stop) (8.0 k typically) - OTP triggers when RNTC  ROTP(off) (5.9 k typically) - OTP is removed when RNTC  ROTP(on) (8.0 k typically) (Note 9) 9. This condition is sufficient for operation recovery of the B version. For the A version which latches off when OTP triggers, the circuit further needs to be reset by a VCC drop below VCC(reset). An online EXCEL[] −based design tool is available to aid in selecting the appropriate NTC value. > **www.onsemi.com Share Feedback** ~~Qe”~~ **23** Your Opinion Matters **NCL30188** At startup, when VCC reaches VCC(on), the OTP comparator is blanked for at least 250 mn s in order to allow the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. This avoids flickering of the LED light during turn on. ## **Brown−Out Protection** **Figure 67. Output Current Reduction versus SD Pin Voltage** The NCL30188 prevents operation when the line voltage is too low for proper operation. As illustrated in Figure 68, the circuit detects a brown−out situation if the VS pin remains below the VBO(off) threshold (0.9 V typical) for more than the 25−ms blanking time. In this case, the controller stops operating. Operation resumes as soon as the VS pin voltage exceeds VBO(on) (1.0 V typical) and VCC is higher than VCC(on). To ease recovery, the circuit overrides the VCC normal sequence (no need for VCC cycling down below VCC(off)). Instead, its consumption immediately reduces to ICC(start) so that VCC rapidly charges up to VCC(on). Once done, the circuit re−starts operating. **Figure 68. Brown−out Circuit** ## **Die Over Temperature (TSD)** The circuit stops operating if the junction temperature (TJ) exceeds 150  C typically. The controller remains off until TJ goes below nearly 100  C. ## **Pin Connection Faults** The circuit addresses most pin connection fault cases: ##  **CS pin short to ground** The circuit senses the CS pin impedance every time it starts−up and after DRV pulses terminated by the 36−s M maximum on−time. If the measured impedance does not exceed 120 ohm typically, the circuit stops operating. In practice, it is recommended to place a minimum of 250−ohm in series between the CS pin and the current sense resistor to take into account possible parametric deviations. - **Fault of the GND connection** If the GND pin is properly connected, the supply current drawn from the positive terminal of the _VCC_ capacitor, flows out of the GND pin to return to the negative terminal of the _VCC_ capacitor. If the GND pin is not connected, the circuit ESD diodes offer another return path. The accidental non−connection of the GND pin is monitored by detecting that one of the ESD diode is conducting. Practically, the ESD diode of CS pin is monitored. If such a fault is detected for 200 s, the m circuit stops generating DRV pulses. **More generally, incorrect pin connection situations (open, grounded, shorted to adjacent pin) are covered by AND9204/D.** **www.onsemi.com** **Share Feedback** Your Opinion Matters **24** **NCL30188** ## **Fault Modes** The circuit turns off whenever a major faulty condition prevents it from operating: - Severe OTP (VSD level below VOTP(off)) - VCC OVP - OVP2 (additional OVP provided by SD pin) - Output diode short circuit protection: “WOD_SCP high” - Output / Auxiliary winding Short circuit protection: “Aux_SCP high” - Die over temperature (TSD) In this mode, the DRV pulses generation is interrupted. In the case of a latching−off fault, the circuit stops pulsing until the LED driver is unplugged and VCC drops below VCC(reset). At that moment, the fault is cleared and the circuit could resume operation. In the auto−recovery case, the circuit cannot generate DRV pulses for the auto−recovery 4−s delay. When this time has elapsed, the circuit recovers operation as soon as the VCC voltage has exceeded VCC(on). In the B version, all these protections are auto−recovery. The SD pin OTP and OVP, WOD_SCP and AUX_SCP are latching off in the A version (see Table 4). ## **Table 4. PROTECTION MODES** |**Table 4. PROTECTION MODES**|**Table 4. PROTECTION MODES**|||| |---|---|---|---|---| ||**AUX_SCP**|**WOD_SCP**|**SD Pin OTP**|**SD Pin OVP**| |NCL30188A*|Latching off|Latching off|Latching off|Latching off| |NCL30188B|Auto−recovery|Auto−recovery|Auto−recovery|Auto−recovery| **ORDERING INFORMATION** **Device Package Type Shipping** SOIC−8 NCL30188BDR2G 2500 / Tape & Reel (Pb−Free/Halide Free) ~~ee~~ *Please contact local sales representative for availability. **DISCONTINUED** (Note 10) |**Device**
~~e~~|**Package**
~~ee~~|**Shipping**†
~~e~~| |---|---|---| |NCL30188ADR2G*
~~e~~|SOIC−10
(Pb−Free/Halide Free)
~~ee~~|2500 / Tape & Reel
~~e~~| 10. **DISCONTINUED:** This device is not recommended for new design. Please contact your **onsemi** representative for information. The most current information on this device may be available on www.onsemi.com. **www.onsemi.com** **Share Feedback** Your Opinion Matters **25** MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **==> picture [34 x 28] intentionally omitted <==** **----- Start of picture text -----**
8
1
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SCALE 1:1
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**SOIC−8 NB** CASE 751−07 ISSUE AK **==> picture [79 x 7] intentionally omitted <==** **----- Start of picture text -----**
DATE 16 FEB 2011
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**==> picture [471 x 425] intentionally omitted <==** **----- Start of picture text -----**
NOTES:
−X− 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
C N X 45 � B 3.80 4.00 0.150 0.157
SEATING C 1.35 1.75 0.053 0.069
PLANE D 0.33 0.51 0.013 0.020
−Z− G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
0.10 (0.004) J 0.19 0.25 0.007 0.010
H D M J MK 0.400 � 1.278 � 0.0160 � 0.0508 �
N 0.25 0.50 0.010 0.020
0.25 (0.010) M Z Y S X S S 5.80 6.20 0.228 0.244
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8 8 8 8
XXXXX XXXXX XXXXXX XXXXXX
1.52 ALYWX ALYWX � AYWW AYWW �
0.060
1 1 1 1
IC IC Discrete Discrete
(Pb−Free) (Pb−Free)
7.0 4.0
XXXXX = Specific Device Code XXXXXX = Specific Device Code
0.275 0.155
A = Assembly Location A = Assembly Location
L = Wafer Lot Y = Year
Y = Year WW = Work Week
W = Work Week � = Pb−Free Package
� = Pb−Free Package
0.6 1.270 *This information is generic. Please refer to
0.024 0.050 device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ � ”, may
or may not be present. Some products may
SCALE 6:1
� inches [mm] � not follow the Generic Marking.
**----- End of picture text -----**
- *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ � ”, may or may not be present. Some products may not follow the Generic Marking. *For additional information on our Pb−Free strategy and soldering details, please download the **onsemi** Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ## **STYLES ON PAGE 2** Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42564B** Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **DESCRIPTION: SOIC−8 NB PAGE 1 OF 2** **onsemi** and are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2019 **SOIC−8 NB** CASE 751−07 ISSUE AK **==> picture [79 x 7] intentionally omitted <==** **----- Start of picture text -----**
DATE 16 FEB 2011
**----- End of picture text -----**
|STYLE 1:|STYLE 1:|STYLE 2:||STYLE 3:|STYLE 3:||STYLE 4:|STYLE 4:| |---|---|---|---|---|---|---|---|---| |PIN 1.|EMITTER|PIN 1.|COLLECTOR, DIE, #1|PIN 1.||DRAIN, DIE #1|PIN 1.|ANODE| |2.|COLLECTOR|2.|COLLECTOR, #1|2.||DRAIN, #1|2.|ANODE| |3.|COLLECTOR|3.|COLLECTOR, #2|3.||DRAIN, #2|3.|ANODE| |4.|EMITTER|4.|COLLECTOR, #2|4.||DRAIN, #2|4.|ANODE| |5.|EMITTER|5.|BASE, #2|5.||GATE, #2|5.|ANODE| |6.|BASE|6.|EMITTER, #2|6.||SOURCE, #2|6.|ANODE| |7.|BASE|7.|BASE, #1|7.||GATE, #1|7.|ANODE| |8.|EMITTER|8.|EMITTER, #1|8.||SOURCE, #1|8.|COMMON CATHODE| |STYLE 5:||STYLE 6:||STYLE 7:|||STYLE 8:|| |PIN 1.|DRAIN|PIN 1.|SOURCE|PIN 1.||INPUT|PIN 1.|COLLECTOR, DIE #1| |2.|DRAIN|2.|DRAIN|2.||EXTERNAL BYPASS|2.|BASE, #1| |3.|DRAIN|3.|DRAIN|3.||THIRD STAGE SOURCE|3.|BASE, #2| |4.|DRAIN|4.|SOURCE|4.||GROUND|4.|COLLECTOR, #2| |5.|GATE|5.|SOURCE|5.||DRAIN|5.|COLLECTOR, #2| |6.|GATE|6.|GATE|6.||GATE 3|6.|EMITTER, #2| |7.|SOURCE|7.|GATE|7.||SECOND STAGE Vd|7.|EMITTER, #1| |8.|SOURCE|8.|SOURCE|8.||FIRST STAGE Vd|8.|COLLECTOR, #1| |STYLE 9:||STYLE 10:||STYLE 11:|||STYLE 12:|| |PIN 1.|EMITTER, COMMON|PIN 1.|GROUND|PIN 1.||SOURCE 1|PIN 1.|SOURCE| |2.|COLLECTOR, DIE #1|2.|BIAS 1|2.||GATE 1|2.|SOURCE| |3.|COLLECTOR, DIE #2|3.|OUTPUT|3.||SOURCE 2|3.|SOURCE| |4.|EMITTER, COMMON|4.|GROUND|4.||GATE 2|4.|GATE| |5.|EMITTER, COMMON|5.|GROUND|5.||DRAIN 2|5.|DRAIN| |6.|BASE, DIE #2|6.|BIAS 2|6.||DRAIN 2|6.|DRAIN| |7.|BASE, DIE #1|7.|INPUT|7.||DRAIN 1|7.|DRAIN| |8.|EMITTER, COMMON|8.|GROUND|8.||DRAIN 1|8.|DRAIN| |STYLE 13:||STYLE 14:||STYLE 15:|||STYLE 16:|| |PIN 1.|N.C.|PIN 1.|N−SOURCE|PIN 1.|ANODE 1||PIN 1.|EMITTER, DIE #1| |2.|SOURCE|2.|N−GATE|2.|ANODE 1||2.|BASE, DIE #1| |3.|SOURCE|3.|P−SOURCE|3.|ANODE 1||3.|EMITTER, DIE #2| |4.|GATE|4.|P−GATE|4.|ANODE 1||4.|BASE, DIE #2| |5.|DRAIN|5.|P−DRAIN|5.|CATHODE, COMMON||5.|COLLECTOR, DIE #2| |6.|DRAIN|6.|P−DRAIN|6.|CATHODE, COMMON||6.|COLLECTOR, DIE #2| |7.|DRAIN|7.|N−DRAIN|7.|CATHODE, COMMON||7.|COLLECTOR, DIE #1| |8.|DRAIN|8.|N−DRAIN|8.|CATHODE, COMMON||8.|COLLECTOR, DIE #1| |STYLE 17:||STYLE 18:||STYLE 19:|||STYLE 20:|| |PIN 1.|VCC|PIN 1.|ANODE|PIN 1.||SOURCE 1|PIN 1.|SOURCE (N)| |2.|V2OUT|2.|ANODE|2.||GATE 1|2.|GATE (N)| |3.|V1OUT|3.|SOURCE|3.||SOURCE 2|3.|SOURCE (P)| |4.|TXE|4.|GATE|4.||GATE 2|4.|GATE (P)| |5.|RXE|5.|DRAIN|5.||DRAIN 2|5.|DRAIN| |6.|VEE|6.|DRAIN|6.||MIRROR 2|6.|DRAIN| |7.|GND|7.|CATHODE|7.||DRAIN 1|7.|DRAIN| |8.|ACC|8.|CATHODE|8.||MIRROR 1|8.|DRAIN| |STYLE 21:||STYLE 22:||STYLE 23:|||STYLE 24:|| |PIN 1.|CATHODE 1|PIN 1.|I/O LINE 1|PIN 1.||LINE 1 IN|PIN 1.|BASE| |2.|CATHODE 2|2.|COMMON CATHODE/VCC|2.||COMMON ANODE/GND|2.|EMITTER| |3.|CATHODE 3|3.|COMMON CATHODE/VCC|3.||COMMON ANODE/GND|3.|COLLECTOR/ANODE| |4.|CATHODE 4|4.|I/O LINE 3|4.||LINE 2 IN|4.|COLLECTOR/ANODE| |5.|CATHODE 5|5.|COMMON ANODE/GND|5.||LINE 2 OUT|5.|CATHODE| |6.|COMMON ANODE|6.|I/O LINE 4|6.||COMMON ANODE/GND|6.|CATHODE| |7.|COMMON ANODE|7.|I/O LINE 5|7.||COMMON ANODE/GND|7.|COLLECTOR/ANODE| |8.|CATHODE 6|8.|COMMON ANODE/GND|8.||LINE 1 OUT|8.|COLLECTOR/ANODE| |STYLE 25:||STYLE 26:||STYLE|27:||STYLE 28:|| |PIN 1.|VIN|PIN 1.|GND|PIN 1.||ILIMIT|PIN 1.|SW_TO_GND| |2.|N/C|2.|dv/dt|2.||OVLO|2.|DASIC_OFF| |3.|REXT|3.|ENABLE|3.||UVLO|3.|DASIC_SW_DET| |4.|GND|4.|ILIMIT|4.||INPUT+|4.|GND| |5.|IOUT|5.|SOURCE|5.||SOURCE|5.|V_MON| |6.|IOUT|6.|SOURCE|6.||SOURCE|6.|VBULK| |7.|IOUT|7.|SOURCE|7.||SOURCE|7.|VBULK| |8.|IOUT|8.|VCC|8.||DRAIN|8.|VIN| |STYLE 29:||STYLE 30:||||||| |PIN 1.|BASE, DIE #1|PIN 1.|DRAIN 1|||||| |2.|EMITTER, #1|2.|DRAIN 1|||||| |3.|BASE, #2|3.|GATE 2|||||| |4.|EMITTER, #2|4.|SOURCE 2|||||| |5.|COLLECTOR, #2|5.|SOURCE 1/DRAIN 2|||||| |6.|COLLECTOR, #2|6.|SOURCE 1/DRAIN 2|||||| |7.|COLLECTOR, #1|7.|SOURCE 1/DRAIN 2|||||| |8.|COLLECTOR, #1|8.|GATE 1|||||| Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42564B** Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **DESCRIPTION: SOIC−8 NB PAGE 2 OF 2** **onsemi** and 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