# Non Isolated POL DC/DC Converter, 300 W, 4 V, 6 V, 60 A, Adjustable

![Product image](https://novapart.co/image/farnell:3818909/)

**URL**: https://novapart.co/products/MPC1100A-54-0000-Z/non-isolated-pol-dc-converter-300-w-4-v-6-60-a
**SKU**: MPC1100A-54-0000-Z
**Manufacturer**: MONOLITHIC POWER SYSTEMS (MPS)
**Category**: Power & Line Protection || Power Supplies || DC / DC Converters || DC / DC Non Isolated Board Mount Converters - Adjustable Output
**Price**: €83.9300
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| Depth | 27mm |
| Width | 18mm |
| Height | 6mm |
| Output Power Max | 300W |
| Output Current Max | 60A |
| Output Voltage Max | 6V |
| Output Voltage Min | 4V |
| Input Voltage Dc Max | 60V |
| Input Voltage Dc Min | 40V |
| Dc / Dc Converter Type | Module |
| Dc / Dc Converter Output Type | Adjustable |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3818909/)

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mes<br>DESCRIPTION<br>**----- End of picture text -----**<br>


## _**MPC1100A-54-0000**_ **High-Efficiency, Non-Isolated, Fixed Ratio, 300W, Digital DC/DC Power Module** sy 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **FEATURES** 

The MPC1100A-54-0000 is a high-efficiency, non-isolated LLC-DCX power card module with a fixed 10:1 transformer turns ratio. The device operates from a 40V to 60V DC primary bus and a 4V to 6V output voltage. It can deliver up to 300W of power. 

- Up to 60A Continuous Secondary Current 

- PMBus/I[2] C Compatible 

- Built-In MTP to Store Custom Configurations 

- Monitoring for Input Voltage, Output Voltage, Output Current, Output Power, and Temperature 

The MPC1100A-54-0000 employs MPS’s MP2981 (a digital LLC controller) and MP8500 (a smart synchronous rectifier). These devices can adjust the PWM to optimize the MPC1100A54-0000, and ensure that the MPC1100A-540000 works at the resonant frequency. 

- Protections Including VIN UVLO, Output OVP/UVP, OCP_TDC, OCP_SPIKE, and OTP 

- Available in a Surface-Mount (27mmx18mmx6mm) Package 

## **APPLICATIONS** 

The built-in multiple-time programmable (MTP) memory can store and restore device configurations. The fault status, input and output voltage, current, and temperature can be easily monitored via the PMBus/I[2] C interface. 

- Datacenters 

- DC Power Distribution 

- High-End Computing Systems 

All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are trademarks of Monolithic Power Systems, Inc. or its subsidiaries. 

The MPC1100A-54-0000 is available in a surface-mount (27mmx18mmx6mm) package. 

## **TYPICAL APPLICATION** 

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**----- Start of picture text -----**<br>
3.3V<br>5V<br>VCC33<br>VCC5V<br>PG<br>PG<br>SDA<br>SDA<br>SCL MPC1100A-<br>SCL<br>GND GND 54-0000<br>EN<br>EN<br>VIN<br>VOUT<br>VIN VOUT<br>GND ADDR PSYS GND<br>**----- End of picture text -----**<br>


**1** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com 

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. 

© 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** MPS _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **ORDERING INFORMATION** 

**Part Number* Package Top Marking MSL Rating** ~~—~~ MPC1100A-54-0000 Surface-Mount MPC1100A-54 3 *For Tape & Reel, add suffix –Z (e.g. MPC1100A-54-0000–Z). 

## **TOP MARKING** 

Date code Vendor’s serial number LOT ID MPC1100A-54 

## **PACKAGE REFERENCE** 

**==> picture [263 x 262] intentionally omitted <==**

**----- Start of picture text -----**<br>
TOP VIEW<br>13 14 15 16 17 18<br>VOUT GND VOUT GND VOUT GND<br>PG EN 3.3V GND 5V VIN GND ADDR GND SDA SCL PSYS<br>12 11 10 9 8 7 6 5 4 3 2 1<br>Surface-Mount (27mmx18mmx6mm)<br>**----- End of picture text -----**<br>


**2** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com 

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **PIN FUNCTIONS** 

|**Pin #**<br>~~a ~~|**Name**<br> ~~a~~|**I/O**<br>~~se~~|**Description**<br>~~se~~|
|---|---|---|---|
|1<br>~~a~~|PSYS<br>~~a~~|A[O]<br>~~ee~~|**Output power indicator.**Current-source output. Connect a resistor from PSYS<br>to GND to convert this current to a voltage signal.<br>~~ee~~|
|2<br>~~——~~|SCL<br>~~——~~|D[I/O]|**PMBus/I2C clock signal.**|
|3<br>~~——~~|SDA<br>~~——~~|D[I]|**PMBus/I2C data signal.**|
|5<br>~~——~~<br>~~a~~|ADDR<br>~~——~~<br>~~a~~|A[I]|**PMBus/I2C address 4-LSBpin setting.**|
|7<br>~~a~~<br>~~a~~|VIN<br>~~a~~<br>~~a~~|Power|**Input mainpower supply.**|
|8<br>~~a~~<br>~~a~~|5V<br>~~a~~<br>~~a~~|Power|**5V power supply input.**5V is the power supply for the primary-side driver.<br>Connect a 1µF capacitor from 5V toground.|
|10<br>~~a~~<br>~~PoP~~|3.3V<br>~~a~~<br>~~PoP~~|Power<br>~~PoP~~|**3.3V power supply input.**3.3V is the power supply for the controller (MP2981)<br>and synchronous rectifier (MP8500). Connect a 4.7µF capacitor from 3.3V to<br>ground.<br>~~PoP~~|
|11<br>~~PoP~~|EN<br>~~PoP~~|D[I]<br>~~PoP~~|**Enable control.**<br>~~PoP~~|
|12|PG|D[O]|**Power good output.**The output of PG is an open-drain signal.|
|13,15,17 VOUT<br>~~a~~|17 VOUT<br>~~a~~|Power<br>~~a~~|**Secondary-sidepower output.**|
|4, 6, 9, 14,<br>16,18<br>~~a~~|GND<br>~~a~~|Power<br>~~a~~|**Power ground.**|



## **ABSOLUTE MAXIMUM RATINGS**[(1)] 

Supply voltage (VIN) ...................... -0.3V to +80V Aux voltage (VCC33) ...................... -0.3V to +4.0V Aux voltage (VCC5V) ...................... -0.3V to +6.5V Address pin (ADDR) .................... -0.3V to +2.0V Output voltage (VOUT) ................... -0.3V to +7.0V All other pins ..................... -0.3V to VCC33 + 0.3V Junction temperature ................................ 150°C Lead temperature ..................................... 260°C 

## _**Recommended Operating Conditions**_[(2)] 

Supply voltage (VIN) .......................... 40V to 60V Aux voltage (VCC33) ..................... 3.15V to 3.45V Aux voltage (VCC5V) ......................... 4.5V to 5.5V Operating junction temp (TJ) .....-40°C to +125°C 

## **Notes:** 

- 1) Exceeding these ratings may damage the device. 

- 2) The device is not guaranteed to function outside of its operating conditions. 

**3** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** MPS _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **ELECTRICAL CHARACTERISTICS** 

|**Parameter**<br>~~GG~~|**Symbol**<br>~~GG~~|**Condition**<br>~~GG~~|**Min**<br>~~GG~~|**Typ**<br>~~GG~~|**Max**<br>~~GG~~|**Units**<br>~~GG~~|
|---|---|---|---|---|---|---|
|**Input**<br>~~—————————~~|||||||
|Input voltage<br>~~—————————~~|VIN<br>~~—————————~~|~~—————————~~|40<br>~~—————————~~|54<br>~~—————————~~|59.5<br>~~—————————~~|V<br>~~—————————~~|
|Input current (VINquiescent<br>current)<br>~~—————————~~<br>~~a~~|IVIN_Q<br>~~—————————~~|Disabled, VIN= 54V, EN low,<br>VCC33= 3.3V,VCC5V= 5V<br>~~—————————~~|~~—————————~~|~~—————————~~|200<br>~~—————————~~|µA<br>~~—————————~~|
|Input current at no load<br>~~a~~<br>~~a~~<br>~~i~~|IVIN_NO_LOAD<br>~~a~~<br>~~ee ee~~|Enabled, VIN= 54V, EN high,<br>VCC33= 3.3V,VCC5V= 5V<br>~~ee~~|~~oe~~|28<br>~~oe~~|ee|mA|
|**Auxiliary 3.3V Supply**<br>~~a~~<br>~~a~~<br>~~es~~<br>~~ee eeoeoe~~ee<br>~~i~~|||||||
|Supplyvoltage<br>~~es~~<br>~~i~~|VCC33<br>~~es~~<br>~~ee ee~~|~~es~~<br>~~ee~~|3.15<br>~~es~~<br>~~oe~~|3.3<br>~~es~~<br>~~oe~~|3.45<br>~~es~~<br>ee|V<br>~~es~~|
|Supply current (VCC33<br>quiescent current)<br>~~i~~|IVCC33_Q<br>~~ee ee~~|Disabled, VIN= 54V, EN low,<br>VCC33= 3.3V,VCC5V= 5V<br>~~ee~~|~~oe ~~|35<br> ~~oe~~|ee|mA|
|Supply current at no load<br>~~a~~<br>~~i~~|IVCC33_NO_LOAD <br><br>~~ee~~<br>|Enabled, VIN= 54V, EN high,<br>VCC33= 3.3V,VCC5V= 5V<br><br>~~ee~~<br>|~~oe~~<br>|142<br><br>~~oe~~<br>|ee<br>|mA<br><br>|
|**Auxiliary 5V Supply**<br>~~es~~<br>~~ee~~<br>~~eeoeoe~~ee<br>~~i~~|||||||
|Supplyvoltage<br>~~es~~<br>~~i~~|VCC5V<br>~~es~~<br>~~ee~~<br>|~~es~~<br>~~ee~~<br>|4.5<br>~~es~~<br>~~oe~~<br>|5<br>~~es~~<br>~~oe~~<br>|5.5<br>~~es~~<br>ee<br>|V<br>~~es~~<br>|
|Supply current (VCC5V<br>quiescent current)<br>~~i~~|IVCC5V_Q<br>~~ee~~<br>|Disabled, VIN= 54V, EN low,<br>VCC33= 3.3V,VCC5V= 5V<br>~~ee~~ <br>|~~oe ~~<br>|~~oe~~ <br>|280<br> ee<br>|µA<br>|
|Supply current at no-load<br>~~es~~<br>~~Se~~|IVCC5V_NO_<br>LOAD<br>~~es~~|Enabled, VIN= 54V, EN high,<br>VCC33= 3.3V,VCC5V= 5V<br>~~es~~|~~es~~|26<br>~~es~~|~~es~~|mA<br>~~es~~|
|**Output**<br>~~es~~<br>~~Se~~|||||||
|Transformer ratio<br>~~Sees~~|K|Primary side to secondary side,<br>VIN= 54V,IOUT= 0A,K = VOUT/ VIN<br>~~ee~~|~~ie~~|1/10<br>~~ee~~|~~ee~~||
|Continuous output current(3)<br>~~Sees~~|IOUT_DC|VIN= 54V,TA= 25°C<br>~~ee~~|~~ie~~|47<br>~~ee~~|~~ee~~|A|
|Output currentpulse(3)<br>~~es~~|IOUT_DC_PULSE500|500µspulse,40V < VIN< 59.5V<br>~~ee~~|90<br>~~ie~~|~~ee~~|~~ee~~|A|
|Output resistance(3)<br>~~es~~<br>~~po~~|RLL<br>~~po~~|VIN= 54V,IOUT= 15A<br>~~ee ~~<br>~~po~~|~~ie ~~<br>~~po~~|3<br> ~~ee~~<br>~~po~~|~~ee~~<br>~~po~~|mΩ<br>~~po~~|
|Switchingfrequency<br>~~po~~<br>~~GG~~|fSW<br>~~po~~<br>~~GG~~|PMBus/I2C readingtON,VIN,IOUT= 1A<br>~~po~~<br>~~GG~~|~~po~~<br>~~GG~~|813<br>~~po~~<br>~~GG~~|~~po~~<br>~~GG~~|kHz<br>~~po~~<br>~~GG~~|
|Ambient efficiency <br>~~GG~~<br>~~OO~~|η<br>~~GG~~<br>~~OO~~|VIN= 54V,IOUT= 7.5A,TA= 25°C<br>~~GG~~<br>~~OO~~|~~GG~~<br>~~OO~~|94<br>~~GG~~<br>~~OO~~|~~GG~~<br>~~OO~~|%<br>~~GG~~<br>~~OO~~|
|**Protections**<br>~~OO~~|||||||
|Input voltage under-voltage<br>lockout(UVLO)<br>~~OO~~<br>~~eC~~|VIN_UVLO<br>~~OO~~<br>~~eC~~|IOUT= 0A<br>~~OO~~<br>~~eC~~|35.5<br>~~OO~~<br>~~eC~~|37<br>~~OO~~<br>~~eC~~|39.5<br>~~OO~~<br>~~eC~~|V<br>~~OO~~<br>~~eC~~|
|Input voltage over-voltage<br>protection(OVP)<br>~~eC~~<br>~~a~~<br>~~a~~|VIN_OVP<br>~~eC~~<br><br>~~ee ee~~|Latch mode, IOUT= 0A<br>~~eC~~<br><br>~~ee~~|60<br>~~eC~~<br><br>~~ee~~|63<br>~~eC~~<br><br>~~ee~~|66<br>~~eC~~<br><br>~~ee~~|V<br>~~eC~~<br>|
|Output voltage UVP<br>~~aes~~<br>~~a~~|VOUT_UVP<br>~~es~~<br>~~ee ee~~|Latch mode,IOUT= 0A<br>~~es~~<br>~~ee~~|~~es~~<br>~~ee~~|3.0<br>~~es~~<br>~~ee~~|~~es~~<br>~~ee~~|V<br>~~es~~|
|Output voltage OVP<br>~~es~~<br>~~a~~|VOUT_OVP<br>~~es~~<br>~~ee ee~~|Latch mode,IOUT= 0A<br>~~es~~<br>~~ee~~|~~es~~<br>~~ee~~|7.2<br>~~es~~<br>~~ee~~|~~es~~<br>~~ee~~|V<br>~~es~~|
|Output current over-current<br>protection(OCP) (3)<br>~~es~~<br>~~a~~|IOUT_OC<br>~~es~~<br>~~ee ee~~|Latch mode<br>~~es~~<br>~~ee~~|~~es~~<br>~~ee~~|~~es~~<br>~~ee~~|140<br>~~es~~<br>~~ee~~|A<br>~~es~~|
|Over-temperature (OT)<br>shutdown threshold(3)<br>~~a~~<br>~~a~~|TOTP<br>~~ee ee~~|~~ee ~~|~~ee ~~|130<br> ~~ee~~|~~ee~~|°C|
|OT recoveryhysteresis(3)<br>~~a~~<br>~~Ge~~|TOTP_HYS<br>~~Ge ~~|~~GGG~~|~~GGG~~|30<br>~~GGG~~||°C|
|Protection recovery delay<br>time(3)<br>~~a~~|tPRO_DELAY||||12.7|ms|



**4** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **ELECTRICAL CHARACTERISTICS** _**(continued)**_ 

|**Parameter**<br>~~es~~|**Symbol**<br>~~es~~|**Condition**<br>~~es~~|**Min**<br>~~es~~|**Typ**<br>~~es~~|**Max**<br>~~es~~|**Units**<br>~~es~~|
|---|---|---|---|---|---|---|
|**EN**<br>~~Ce~~|||||||
|Low-voltage input<br>~~Ce~~|VIL(EN)<br>||||0.4<br>|V<br>|
|High-voltage input<br>~~eG~~<br>~~pe~~|VIH(EN)<br>~~eG~~<br>|~~eG~~<br>|0.8<br>~~eG~~<br>|~~eG~~<br>|~~eG~~<br>|V<br>~~eG~~<br>|
|Enable high leakage<br>~~pe~~|IIH(EN)<br>|||3<br>|8<br>|µA<br>|
|Enable delay(3)<br>~~pe~~|tA<br>|EN high to soft start begins,<br>VOUT= 10%<br>||0.8<br>|1<br>|ms<br>|
|**PSYS**<br>~~Cn~~|||||||
|PSYS output voltage(3)<br>~~en~~|VPSYS<br>~~en~~|VIN = 54V, IOUT = 47A, RSYS = 20kΩ<br>~~en~~|~~en~~|0.634<br>~~en~~|~~en~~|V<br>~~en~~|
|**PG Output**<br>~~|~~|||||||
|PG low voltage||IPG= 20mA||0.1||V|
|PG high leakage current<br>~~er~~|ILPG<br>~~er~~|VPG= 3.3V<br>~~er~~|-3<br>~~er~~|~~er~~|+3<br>~~er~~|µA<br>~~er~~|
|**PMBus/I2C DC Characteristics**<br>~~er~~<br>~~a~~|||||||
|High-voltage input(3)<br>~~a~~|VIH<br>|SCL, SDA<br>|1.35<br>|||V<br>|
|Low-voltage input(3)<br>~~aeG~~<br>~~pe~~|VIL<br>~~eG~~<br>|SCL,SDA<br>~~eG~~<br>|~~eG~~<br>|~~eG~~<br>|0.8<br>~~eG~~<br>|V<br>~~eG~~<br>|
|Input leakage current<br>~~pe~~||SCL,SDA,ALT#<br>|-10<br>||+10<br>|µA<br>|
|Pin capacitance(3)<br>~~pe~~|CPIN<br>||||10<br>|pF<br>|
|**PMBus/I2C Timing Characteristics**(3) (4)<br>~~Ce~~<br>~~a~~|||||||
|Operating frequency range<br>~~a~~|fPMB<br>||10||1000|kHz|
|Bus free time<br>~~aeG~~|tBUF<br>~~eG~~|Between stopand start condition<br>~~Ge~~|0.5<br>~~Ge~~|~~Ge~~||µs|
|Holdingtime<br>~~Ge~~|tHD_STA<br>~~Ge~~<br>~~ee~~|~~Ge~~<br>~~ee~~|0.26<br>~~Ge~~<br>~~ee~~|~~Ge~~<br>~~ee~~|~~Ge~~|µs<br>~~Ge~~|
|Repeated start condition set-<br>uptime<br>~~ee~~|tSU_STA<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|0.26<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~|µs<br>~~ee~~|
|Stop condition set-up time<br>~~Ps~~|tSU_STO<br>~~ee~~<br>~~Ps~~<br>~~ee~~|~~ee~~<br>~~Ps~~|0.26<br>~~ee ~~<br>~~Ps~~|~~ee~~<br>~~Ps~~|~~Ps~~|µs<br>~~Ps~~|
|Data hold time<br>~~eG~~|tHD_DAT<br>~~ee~~<br>~~eG~~<br>~~Ge~~|~~eG~~<br>~~Qe~~|10<br>~~eG~~<br>~~Qe~~|~~eG~~|~~eG~~|ns<br>~~eG~~|
|Data set-uptime<br>~~ee~~|tSU_DAT<br>~~ee~~<br>~~Ge~~<br>~~Ge~~|~~ee~~<br>~~Qe~~<br>~~Qe~~|50<br>~~ee~~<br>~~Qe~~<br>~~Qe~~|~~ee~~|~~ee~~|ns<br>~~ee~~|
|Clock low timeout<br>~~ee~~|tTIMEOUT<br>~~Ge~~<br>~~ee~~<br>~~Ge~~|~~Qe~~<br>~~ee~~<br>~~Qe~~|25<br>~~Qe~~<br>~~ee~~<br>~~Qe~~|~~ee~~|35<br>~~ee~~|ms<br>~~ee~~|
|Clock lowperiod<br>~~eG~~|tLOW<br>~~Ge~~<br>~~eG ~~<br>~~Ge~~|~~Qe~~<br> ~~Oe~~<br>~~GG~~|0.5<br>~~Qe~~<br>~~Oe~~<br>~~GG~~|~~GG~~||µs|
|Clock highperiod<br>~~Re~~|tHIGH<br>~~Re~~<br>~~Ge~~<br>~~Ge~~|~~Re~~<br>~~GG~~<br>~~GG~~|0.26<br>~~Re~~<br>~~GG~~<br>~~GG~~|~~Re~~<br>~~GG~~<br>~~GG~~|50<br>~~Re~~|µs<br>~~Re~~|
|Clock/data fallingtime<br>~~Re~~|tF<br>~~Ge ~~<br>~~Re~~<br>~~Ge~~|~~GG~~<br>~~Re~~<br>~~GG~~|~~GG~~<br>~~Re~~<br>~~GG~~|~~GG~~<br>~~Re~~<br>~~GG~~|120<br>~~Re~~|ns<br>~~Re~~|
|Clock/data risingtime<br>~~en~~|tR<br>~~Ge ~~<br>~~en~~|~~GG~~<br>~~en~~|~~GG~~<br>~~en~~|~~GG~~<br>~~en~~|120<br>~~en~~|ns<br>~~en~~|



## **Notes:** 

- 3) Guaranteed by design or characterization data. Not tested in production. 

4) The device supports 100kHz, 400kHz, and 1MHz bus speeds. The PMBus/I[2] C timing parameters in this table are for operation at 400kHz and 1MHz. If the PMBus/I[2] C operating frequency is 100kHz, refer to SMBus specifications for the timing parameters 

**5** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** MPS ee 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ **TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.** 

## **Efficiency vs. Output Current** 

**==> picture [458 x 389] intentionally omitted <==**

**----- Start of picture text -----**<br>
Efficiency vs. Output Current Power Loss vs. Output Current<br>0.98<br>18<br>16<br>0.97 [et | 14 e Vin=40V e<br>12 Vin=48V<br>0.96 7 4aNSN 10 Vin=54V —f<br>8 Vin=60V<br>0.95 Vin=40V<br>f SY 6 y<br>Vin=48V<br>4<br>0.94 Vin=54V<br>f= oN 2 o w<br>Vin=60V<br>0<br>0.93<br>0 10 20 30 40 50 60<br>0 10 20 30 40 50 60<br>IOUT (A)<br>IOUT (A)<br>Output Voltage vs. Output<br>Current<br>7<br>6 CTTTTI<br>5<br>——<br>4 a<br>Vin=40V<br>—<br>3<br>Vin=48V<br>2 Vin=54V<br>Vin=60V<br>=<br>1 | |<br>0 10 20 30 40 50 60<br>IOUT (A)<br>EFFICIENCY (%)<br> (V)<br>OUT<br>V<br>POWER LOSS (W)<br>**----- End of picture text -----**<br>


**6** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com 

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **TYPICAL PERFORMANCE CHARACTERISTICS** _**(continued)**_ 

## **TA = 25°C, unless otherwise noted.** 

## **Start-Up through VIN** 

VIN = 54V, IOUT = 0A 

## **Start-Up through VIN** 

VIN = 54V, IOUT = 60A, full load 

**==> picture [35 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
CH2: VOUT<br>**----- End of picture text -----**<br>


**==> picture [30 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
CH2: VIN<br>**----- End of picture text -----**<br>


**==> picture [34 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
CH2: VOUT<br>**----- End of picture text -----**<br>


**==> picture [29 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
CH2: VIN<br>**----- End of picture text -----**<br>


## **Remote On** 

VIN = 54V, IOUT = 0A, EN on 

## **Remote On** 

VIN = 54V, IOUT = 60A, EN on 

**CH4: VOUT CH4: VOUT** 

**==> picture [279 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
CH2: EN CH2: EN<br>**----- End of picture text -----**<br>


## **Transient Response** 

VIN = 54V, 1A/µs step change in load from 100% to 75% of IO_MAX 

## **Transient Response** 

VIN = 54V, 1A/µs step change in load from 75% to 100% of IO_MAX 

**==> picture [283 x 33] intentionally omitted <==**

**----- Start of picture text -----**<br>
CH4:  CH4:<br>VOUT/AC VOUT/AC<br>CH3: IOUT CH3: IOUT<br>**----- End of picture text -----**<br>


**7** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com 

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** MPS 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **FUNCTIONAL BLOCK DIAGRAM** 

**==> picture [471 x 367] intentionally omitted <==**

**----- Start of picture text -----**<br>
Single Integrated  MP8500 x 2<br>Magnetic Core<br>SR<br>VOUT = 4V to 6V<br>VIN = 40V to 60V<br>VIN<br>VCC5V<br>SR<br>CR<br>MP8500 x2<br>SR<br>LR<br>VIN<br>GND<br>SR<br>PWMS2<br>_ OSS<br>VCC33V<br>Temp<br>PWMS1<br>PWMP1 CS2<br>PWM  SR<br>Control Control<br>CS1<br>PWMP2<br>MP2981<br>SCL SDA<br>Driver<br>Driver<br>**----- End of picture text -----**<br>


**Figure 1: Functional Block Diagram** 

**8** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## MPS 

## **OPERATION** 

The MPC1100A-54-0000 is a full-bridge LLCDCX power converter module with a 10:1 transformer turns ratio. The device incorporates the MP2981, a digital LLC controller that provides two PWM channels for primary-side control as well as two PWM channels for secondary-side control. 

The LLC circuit is most efficient when working at the resonant frequency (see Figure 2). LR and CR have tolerances and temperature shifts that may cause the operating frequency to shift away from the resonant frequency. 

The resonant frequency (fR) can be calculated with Equation (1): 

**==> picture [178 x 34] intentionally omitted <==**

With MPS’s MP8500 (a smart synchronous rectifier), the MPC1100A-54-0000 can be optimized to work at the resonant frequency, which improves the module’s efficiency. 

The MPC1100A-54-0000 incorporates four MP8500 devices. The MP8500 supports accurate current-sense (CS) functionality. Its CS pin sources a current that is proportional to the output current (5µA/A), and generates a voltage by connecting a resistor to GND. The MP2981 can use this signal to monitor and report the output current (IOUT), as well as protect the MPC1100A-54-0000 power card module. 

The MP8500 can also send a zero-current detection (ZCD) signal to the MP2981 once a 0A current is detected. Then the MP2981 aligns the PWM off time and ZCD signal by fine-tuning the PWM on time (tON) to let the MPC1100A-54-0000 operate at the resonant frequency. 

During the dead time, the transformer’s magnetizing inductor current discharges the FET’s output capacitor to zero before the FET turns on. This helps the FET achieve zerovoltage switching (ZVS) on its primary side. The MP8500 turns off after ZCD, and then zerocurrent switching (ZCS) is implemented. 

**==> picture [272 x 288] intentionally omitted <==**

**----- Start of picture text -----**<br>
PWM1 PWM2 PWM1 PWM2<br>IR IR<br>I M IM<br>ARIE:<br>a<br>V DS1<br>tDEAD<br>ID1 ID2<br>IREC<br>Let e:<br>VC<br>t0 | t1 t2 INNZIN,  t3 t4 t5 t6<br>Figure 2: LLC Waveform<br>**----- End of picture text -----**<br>


**9** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com 

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **Power-On Sequence** 

## _**Multiple-Time Programmable (MTP) Memory Operation**_ 

The MP2981 uses the multiple-time programmable (MTP) memory to store the configuration parameters, including the switching frequency (fSW), soft-start time (tSS), and protection parameters. Default values are preconfigured during manufacturing. Data can be reconfigured using the STORE_USER_ALL command (17h) or STORE_ALL command (15h) via the PMBus/I[2] C interface. 

The configurations are restored by the MTP during the power-on sequence, or by receiving a RESTORE_USER_ALL (18h) command or RESTORE_ALL (16h) command from the PMBus/I[2] C. Figure 3 shows the device’s system state machine. ENABLE_CMD means that the MSB of 01H is 1. MEMORY_OK means that the MTP has no signature error or CRC error, or that an MTP fault state has been cleared after copying the MTP. 

**==> picture [165 x 350] intentionally omitted <==**

**----- Start of picture text -----**<br>
Rest<br>C)<br>POR<br>Data Invalid  NVM<br>Copy NVM Faults<br>Waiting<br>Fault Clear<br>System<br>Initialization<br>MEMORY_OK<br>Wait B<br>Start Wait Retry<br>Delay<br>ENABL E_ CMD<br>TON_DELAY<br>v<br>Power Out<br>~ENABL E_ CMD and<br>TOF F_ DELAY Protection<br>CRC Error<br>Wait A Wait C Wait B<br>~ENABLE<br>_CMD<br>~ENABLE<br>_CMD<br>**----- End of picture text -----**<br>


**Figure 3: System State Machine** 

MTP operation can be easily accomplished with MPS’s GUI software, downloaded from the MPS website. The MTP can be subjected to more than 100,000 erase and write cycles. 

## _**Start-Up Sequence**_ 

After VDD33 is ready, the internal reset of the MP2981 is released and the clock starts ticking (see Figure 4). The MP2981 begins to copy data regardless of the EN pin’s state. Then the MPC1100A-54-0000 can be powered on by turning on EN, pulling VIN high, or by receiving an ON command. 

**==> picture [196 x 181] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD3V3<br>VDD1V8<br>VDD3V3_UVLO<br>VDD1V8_UVLO<br>VDD3V3_OK<br>VDD1V8_OK<br>Pll_200M<br>NRST<br>EN Pin<br>MTP Copy Start Delay<br>VOUT<br>**----- End of picture text -----**<br>


**Figure 4: MP2981 Start-Up Sequence** 

## _**Soft Start**_ 

The MP2981 adopts pulse-width modulation (PWM) mode for the first PWM cycle during soft start. During the first tON increasing stage, PWM runs at the maximum frequency. The PWM on time begins at TON_MIN_LIM (1Fh), bits[13:8] and increases to TON_MIN (1Ch). 

The first dead time value is (TON_MIN + DEAD_TIME (1Bh) - TON_MIN_LIM). Then it drops to DEAD_TIME (1Bh), which is the normal working value. The frequency remains the same. 

During the second tON increasing stage, the PWM frequency is reduced from its maximum value to the resonant frequency. tON increases from TON_MIN (1Ch) to TON_NORMAL (1Eh), and the dead time is fixed. This helps reduce the inrush current during the first PWM cycles during soft start compared to traditional soft start methodology. 

**10** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** ss meS _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **Primary ZCD Loop** 

The MP2981 detects the ZCD signal from the synchronous rectifier (SR), and adjusts the PWM frequency to its resonant value according to ZCD. ZCD going high (or low, selected by SEL_ZCD_NEG (0Fh), bit[14]), means that the SR current goes negative. Both phases have their own ZCD, which can be enabled together or separately (0Fh, bits[6:5]). 

The valid area for detecting ZCD is set by register 0Bh. For more details, see the ZCD_TIME_SET (0Bh) section on page 24. If the ZCD edge is within the valid setting area, tON falls by WEIGHTN_ZCD (29h), bits[15:8]. If not, tON increases by WEIGHTP_ZCD (29h), bits[6:0]. The adjusting speed is determined by register 29h. After 256 continuous valid ZCD pulses (including phase 1 and phase 2), tON drops by 5ns. If no valid ZCD occurs within 256 continuous PWM pulses (including phase 1 and phase 2), then tON increases by 5ns. 

This function can be limited by the sampled SR current. The TDC current must be within the light-load and heavy-load limitations defined by register 0Ch if the load limit is enabled (0Ch, bits[4]). 

If LOADLOW_ZCDLOOP_EN (0Ch), bit[15] is not enabled, the ZCD adjusting frequency can be held. The frequency can be held if any of the following conditions are met: 

- The CS1 pin current is below CMP_CS1_ENTERFREQ (1Ah), bit[8], and 1Ah, bits[3:0] is in the corresponding valid area 

- The TDC current is below or equal to the level set by MFR_IOUT_LEVEL_L (49h), bits[7:0] 

Under these conditions, the ZCD adjusting frequency is held since the SR’s ZCD is not accurate under light-load conditions. 

If the tON difference between neighboring PWM periods is within ZCDLOOP_HYS (0Bh), bits[10:8] for 256 PWM periods, the frequency is stable unless the load changes. tON can be locked if ZCDLOOP_LATCHTON_EN (0Ch), bit[5] is high. The synchronized ZCD in the MP2981 is delayed from SR current ZCD timing. The final tON can be fixed by 

TON_ZCDLOOP_DEC (0Fh), bits[11:8] if ZCDLOOP_LATCHTON_EN (0Ch), bit[5] is enabled. 

## **Fault Monitoring and Protections** 

The MPC1100A-54-0000 monitors the input voltage (VIN), output voltage (VOUT), output current (IOUT), MP8550 temperature, and MP2981 die temperature. 

The MPC1100A-54-0000 also supports various fault monitoring and protections, including VIN under-voltage lockout (UVLO), VIN over-voltage protection (OVP), over-current protection (OCP) spike, OCP thermal design current (TDC), output OVP, under-voltage protection (UVP), overtemperature protection (OTP), and DrMOS fault protection. 

## _**VIN Under-Voltage Lockout (UVLO) and OverVoltage Protection (OVP)**_ 

VIN is sensed and monitored by the analog-todigital converter (ADC). The ADC-sensed input voltage is converted to an unsigned binary format (READ_VIN (0.125V/LSB, 88h)) using the value set by VIN_CAL_GAIN (3Ah), which is proportional to the input voltage divider. 

The READ_VIN value is compared with the VIN_ON (35h) and VIN_OFF (36h) values to control the VIN UVLO threshold. If VIN is below or equal to VIN_ON when the device is off (PWM is not generated during this time) or VIN drops below VIN_OFF at any time, then VIN UVLO occurs (see Figure 5). The only exception is when the MTP is copying at start-up. 

**==> picture [222 x 104] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN_ON<br>VIN_OFF<br>VIN<br>Start Start<br>Copy MTP Delay Delay<br>VIN_UVLO<br>Fr<br>PWM  ...<br>**----- End of picture text -----**<br>


**Figure 5: VIN UVLO** 

VIN UVLO is also enabled when both DISABLE_ALL_PRO (68h), bit[0] and RST_VIN_PRO (68h), bit[4] are low. VIN UVLO resets all shutdown protections. 

**11** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

If VIN ramps up, EN turns on, and there is no off command, then the MPC100A-54-0000 restarts and resumes normal operation. 

the low-pass filter, and are then outputted on the IMON pin after a three-time buffer. 

The ADC samples the IMON voltage (see Figure 7). Then the digital part calculates IOUT_CAL_GAIN (38h) and IOUT_CAL_OFFSET (39h), as well as READ_IOUT (8Ch) from the ADC result (9Bh), which is compared to the output current limit (register 6Ah) to determine whether an overcurrent (OC) condition has occurred. 

If VIN exceeds VIN_OV_FLT_LIM (40h), then VIN OVP occurs and the chip shuts down. OVP does not occur when the MTP is being restored during start-up. It is controlled by registers 68h, bits[5:4] and 68h, bit[0]. 

## _**VOUT Under-Voltage Protection (UVP) and Over-Voltage Protection (OVP)**_ 

If the thermal design current (TDC) remains high for longer than the set time (6Ah), this protection shuts down the module. 

Output OVP and UVP are designed to protect the output fault statuses. If VOUT exceeds the VOUT_MAX value, the chip shuts down immediately. Based on the mode set by the VOUT_OVP_MAX_LATCH bit, the part responds by going into latch-off or hiccup mode. It can also take no action if OVP is disabled. 

**==> picture [188 x 80] intentionally omitted <==**

**----- Start of picture text -----**<br>
ADC<br>CS1 1MΩ<br>x3 IMON<br>RCS1<br>CS2 1MΩ<br>RCS2<br>**----- End of picture text -----**<br>


The OVP_MAX threshold (OVP1) has eight options ranging between 1V and 1.7V, with 0.1V/step. The over-voltage threshold (OVP2) has four tracking options: 110%, 120%, 130%, and 140% of the reference voltage (VREF). 

**Figure 7: IMON Pin** 

If VOUT drops quickly and falls below the UVP_MIN threshold, the device shuts down after a short delay time (6Dh, bits[5:0]) (see Figure 6). The under-voltage threshold has four tracking options: 90%, 80%, 70%, and 60% of the reference voltage (VREF). Level 2 UVP (UVP2), also called VOUT low protection, has four thresholds: 0.3V, 0.4V, 0.5V, and 0.6V. 

## _**Over-Current Protection (OCP) Spike**_ 

OCP is designed to limit the output current when the load consumes more current than the circuit can handle. The MP8500’s CS pin sources a current that is proportional to IOUT (5µA/A), and generates a voltage by connecting a resistor to GND. The CS pins (CS1 and CS2) of both phases are compared to the peak CS levels (OCSPK_H and OCSPK_L) (see Figure 8). 

**==> picture [468 x 226] intentionally omitted <==**

**----- Start of picture text -----**<br>
VOSEN<br>OV1 OC_SPIKE_H<br>3 OV1_LIMIT<br>DAC CS1<br>i OCSPK_H_1<br>6Ch,<br>VOSEN OV2 bits[15:8]<br>VREF | 2 OV2_LIMIT DAC<br>OCSPK_H_2<br>VREF 2 UV_LIMIT UV<br>VOSEN<br>OC_SPIKE_L<br>CS2<br>Figure 6: OVP1, OVP2, and UVP Protection  OCSPK_L_1<br>6Ch,<br>Circuits<br>bits[7:0]<br>——— E :<br>Over-Current Protection (OCP) and Thermal  DAC<br>Design Current (TDC)   OCSPK_L_2<br>All parallel SR DrMOS currents of the same<br>phase flow together into their own CS resistor<br>(RCS). Two-phase CS voltages are added after  Figure 8: OC Spike Comparators<br>**----- End of picture text -----**<br>


**12** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

If the current drops to the lower level, the tON accumulator decreases by the value of WEIGHT_OCSPK_L (32h) (see Figure 9). After dropping to a sufficient value, tON decreases by 5ns. The minimum tON value is TON_MIN (1Ch). In each PWM cycle, the tON values for both phases are the same. 

**==> picture [188 x 108] intentionally omitted <==**

**----- Start of picture text -----**<br>
OCSPK_L<br>tON<br>WEIGHT_ WEIGHT_<br>OCSPK_L OCSPK_L_INC<br>Figure 9: OCSPK_L<br>**----- End of picture text -----**<br>


The two OC spikes cannot shut off the chip directly. 

When the OC conditions are removed, tON gradually increases to the original value of WEIGHT_OCSPK_H or WEIGHT_OCSPK_L. The greater OC value has the higher priority. 

The SR_PWM pins (PWM pins for the MP8500) are designed to turn off later than the PWMP pins (PWM signal for the primary edge) on the MP2981 during an OC spike to reduce the SR current flowing through the diodes. This is set by register 08h, bits[15:12], and bits[6:4]. See the CTRL_OC (08h) section on page 23 for more details. 

## _**Over-Temperature Protection (OTP)**_ 

The SR temperature and controller die temperature are both sensed by the ADC. These values trigger different responses that are independent from one another. However, the device enters latch-off or hiccup mode if either condition is triggered. 

The MP8500 sends the temperature-sense signal for the MP2981’s TEMP pin. If the MP8500 triggers a CS fault and enters a protection mode, it pulls the TEMP pin to 3.3V. The MP2981 must have a half-divider on the TEMP pin so that the MP2981 can send the signal to the comparator and the ADC. 

## _**MTP Fault**_ 

system enters the MTP fault state and waits for the error to be cleared. 

## _**Communication Failure**_ 

A data transmission fault occurs when information is not properly transferred between the devices. There are several data transmission faults: 

- Sending too little data 

- Reading too little data 

- Host sending too many bytes 

- Reading too many bytes 

- Improperly set read bit in the address byte 

- Unsupported command codes 

## **PMBus/I[2] C Communication** 

The MPC1100A-54-0000 supports real-time monitoring for the VR operation parameters and status with PMBus/I[2] C.interface. Table 1 lists the monitored parameters. 

**Table 1: PMBus/I[2] C Monitored Parameters** 

|**Parameter**|**PMBus/I2C **|
|---|---|
|VOUT|62.5mV/LSB|
|IOUT|0.25A/LSB|
|Temperature|1°C|
|VIN|0.125V/LSB|
|Die temperature|1°C|
|OVP|✓|
|UVP|✓|
|OCP|✓|
|OTP|✓|
|VINUVLO|✓|
|VINOV|✓|
|CML|✓|



## **PMBus/I[2] C Interface** 

To support multiple VR devices using the same PMBus/I[2] C interface, the MFR_ADDR_PMBus register or the ADDR pin can configure the PMBus/I[2] C address. 

The address is a 7-bit code. The 3MSB are set by the register. The 4LSB bit address can either be set by the register or by the ADDR voltage. The 00h address is reserved as an all call address, which can be set for a single chip. 

The ADDR voltage is set by the voltage divider from the VDD18 voltage. 

If the data in the MTP is determined to be invalid by the cyclic redundancy check (CRC), then the 

**13** 

MPC1100A-54-0000 Rev. 1.0 MonolithicPower.com 3/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** MPS _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

Table 2 shows the resistor values for different PMBus/I[2] C addresses when the 3MSB are set to 3’b010. 

|||~~ee~~||
|---|---|---|---|
|**PMBus/I2C **<br>**Address**<br>~~ee~~|**Setting**<br>**Point(V)**<br>~~ee~~|**RTOP**<br>**(kΩ) 1%**<br>~~ee~~<br>~~ee~~|**RBOTTOM**<br>**(kΩ) 1%**<br>~~ee~~|
|20h<br>~~ee~~<br>~~ee~~|0<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|0<br>~~ee~~|
|21h<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.031<br>~~ee~~|33.2<br>~~ee~~|0.576<br>~~ee~~|
|22h<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.055|33.2|1.05|
|23h<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.084|33.2|1.62|
|24h<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.115|33.2|2.26|
|25h<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.156|33.2|3.16|
|26h<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.203|33.2|4.22|
|27h<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.266|33.2|5.76|
|28h<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.338|33.2|7.68|
|29h<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.432|33.2|10.5|
|2Ah<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.542|33.2|14.3|
|2Bh<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.677|33.2|20.0|
|2Ch<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.845|33.2|29.4|
|2Dh<br>~~ee~~<br>~~ee~~<br>~~ee~~|1.049|33.2|46.4|
|2Eh<br>~~ee~~<br>~~ee~~|1.301|33.2|86.6|
|2Fh<br>~~ee~~|1.549|33.2|20.5|



There are a total of five transmission structures, listed below: 

1. Send command only 

2. Write byte 

3. Write word 

4. Read byte 

5. Read word 

To read or write to the MPC1100A-54-0000 registers, the PMBus/I[2] C or I[2] C command must be compliant with the corresponding register and byte number. 

The PMBus/I[2] C communication frequency can support 1MHz. 

Figure 10 shows the supported PMBus/I[2] C transmission structure without packet error checking (PEC). 

Figure 11 shows the supported PMBus/I[2] C transmission structure with PEC. 

The PMBus/I[2] C or I[2] C commands and register map of the MPC1100A-54-0000 is the same as the MP2981. Refer to the MP2981 datasheet for additional details. 

- 1) S Slave Address Wr A Command Code A P ~~ee~~ ee eee 

- 2) S Slave Address Wr A Command Code A Data Byte A P ee ~~ee~~ ee 

- 3) S Slave Address Wr A Command Code A Data Byte Low A Data Byte High A P a ~~ee~~ 

- 4) S Slave Address Wr A Command Code A S Slave Address Rd A Data Byte NA P a a Bs 

- 5) S Slave Address Wr A Command Code A S Slave Address Rd A Data Byte Low **A** Data Byte High NA P a ~~Be~~ a Be ee **S = Start** LI **Master to Slave P = Stop** L **Slave to Master A = Acknowledge (ACK) Wr = Write (Bit Value = 0) NA = Not Acknowledge (NACK) Rd = Read (Bit Value = 1)** 

**Figure 10: Supported PMBus/I[2] C Transmission Structure without PEC** 

**14** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** MPS 

- _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

- 1) S Slave Address Wr A Command Code A PEC Byte A P ~~ee~~ 

- 2) S Slave Address Wr A Command Code A Data Byte A PEC Byte A P [| ~~TC~~ TT 

- 3) S Slave Address Wr A Command Code A Data Byte Low A Data Byte High A PEC Byte A P [fT TT 

- 4) S Slave Address Wr A Command Code A S Slave Address Rd A Data Byte A PEC Byte NA P aeOe dD 

- 5) S Slave Address Wr A Command Code A S Slave Address Rd A Data Byte Low A Data Byte High A ~~[jE~~ PEC Byte NA P 

- ee 

> **S = Start** O **Master to Slave** 

> **P = Stop** Oo **Slave to Master A = Acknowledge (ACK) Wr = Write (Bit Value = 0) NA = Not Acknowledge (NACK) Rd = Read (Bit Value = 1)** 

## **Figure 11: Supported PMBus/I[2] C Transmission Structure with PEC** 

**15** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** MPS _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ **PMBUS/I[2] C MEMORY PAGE 0 COMMANDS/REGISTERS** 

|**Command Code**<br>~~a~~|**Command Name**|**Type **|**Bytes**|
|---|---|---|---|
|0x00<br>~~ee~~|PAGE|R/W|1|
|0x01<br>~~ee~~<br>~~Ge~~|OPERATION<br>~~Ge~~|R/W<br>~~Ge~~|1<br>~~Ge~~|
|0x03<br>~~Ge~~|CLEAR_FAULTS<br>~~Ge~~|Send<br>~~Ge~~|0<br>~~Ge~~|
|0x04<br>~~ee~~|CTRL_PWM<br>~~ee~~|R/W<br>~~ee~~|2<br>~~ee~~|
|0x05<br>~~ee~~<br>~~a~~|MFR_ADC_HOLD_TIME<br>~~ee~~|R/W<br>~~ee~~|1<br>~~ee~~|
|0x06<br>~~GG~~|CTRL_VR<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|
|0x07<br>~~Ge~~|CTRL_MTP<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x08<br>~~Ge~~<br>~~a~~|CTRL_OC<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x09<br>~~GG~~|LOW_POWER_SET_BIT<br>~~GG~~|R/W<br>~~GG~~|1<br>~~GG~~|
|0x0b<br>~~Ge~~|ZCD_TIME_SET<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x0c<br>~~Ge~~<br>~~a~~|ZCD_LOOP_SET<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x0e<br>~~GG~~|SKIP_SR_PWM_SET<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|
|0x0f<br>~~Ge~~|CTRL_PWM_BK<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x15<br>~~Ge~~<br>~~a~~|STORE_ALL<br>~~Ge~~|Send<br>~~Ge~~|0<br>~~Ge~~|
|0x16<br>~~GG~~|RESTORE_ALL<br>~~GG~~|Send<br>~~GG~~|0<br>~~GG~~|
|0x17<br>~~Ge~~|STORE_USER_ALL<br>~~Ge~~|Send<br>~~Ge~~|0<br>~~Ge~~|
|0x18<br>~~Ge~~<br>~~a~~|RESTORE_USER_ALL<br>~~Ge~~|Send<br>~~Ge~~|0<br>~~Ge~~|
|0x19<br>~~GG~~|MFR_VOUT_SEL<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|
|0x1A<br>~~Ge~~|MFR_IOUT_SEL<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x1B<br>~~Ge~~<br>~~a~~|DEAD_TIME<br>~~Ge~~|R/W<br>~~Ge~~|1<br>~~Ge~~|
|0x1C<br>~~GG~~|TON_MIN<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|
|0x1D<br>~~Ge~~|TON_MAX<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x1E<br>~~Ge~~<br>~~Ge~~|TON_NORMAL<br>~~Ge~~<br>~~Ge~~|R/W<br>~~Ge~~<br>~~Ge~~|2<br>~~Ge~~<br>~~Ge~~|
|0x1F<br>~~GG~~|TON_MIN_LIM<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|
|0x21<br>~~eG~~|MFR_REF_CONFIG<br>~~eG~~|R/W<br>~~eG~~|2<br>~~eG~~|
|0x22<br>~~eG~~<br>~~Ge~~|VOUT_TRIM<br>~~eG~~<br>~~Ge~~|R/W<br>~~eG~~<br>~~Ge~~|1<br>~~eG~~<br>~~Ge~~|
|0x25<br>~~GG~~|TRANSFORMER_RATIO<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|
|0x29<br>~~Ge~~|WEIGHT_ZCD<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x2A<br>~~Ge~~<br>~~a~~|SR_PWM_SETA_PRIDRV<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x2B<br>~~GG~~|SS_SRNEG_SET<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|
|0x2C<br>~~Ge~~|SR_PWM_SETB<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x2D<br>~~Ge~~<br>~~a~~|MFR_SLOPE_SR<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x2E<br>~~GG~~|MFR_SLOPE_BLK<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|
|0x2F<br>~~Ge~~|PRISETBLK_WEIGHT_SS<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x30<br>~~Ge~~<br>~~a~~|WEIGHT_2_1<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x31<br>~~GG~~|WEIGHT_4_3<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|
|0x32<br>~~Ge~~|WEIGHT_OCSPK_L_N<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x33<br>~~Ge~~<br>~~a~~|WEIGHT_OCSPK_INC<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x34<br>~~GG~~|MFR_VIN_DROP_SET<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|
|0x35<br>~~Ge~~|VIN_ON<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x36<br>~~Ge~~<br>~~a~~|VIN_OFF<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x38<br>~~GG~~|IOUT_CAL_GAIN<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|
|0x39<br>~~GG~~|IOUT_CAL_OFFSET<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|



**16** 

MPC1100A-54-0000 Rev. 1.0 MonolithicPower.com 3/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** MPS _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ **PMBUS/I[2] C MEMORY PAGE 0 COMMANDS/REGISTERS** _**(continued)**_ 

|**Command Code**<br>~~a~~|**Command Name**<br>~~G~~|**Type**|**Bytes**|
|---|---|---|---|
|0x3A<br>~~GG~~|VIN_CAL_GAIN<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|
|0x3B<br>~~a~~|VOUT_CAL_GAIN|R/W|2|
|0x40<br>~~a~~<br>~~GG~~|VIN_OV_FLT_LIM<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|
|0x42<br>~~GG~~|TEMP_GAIN_OFFSET<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|
|0x43<br>~~ee~~|DIETEMP_GAIN_OFFSET<br>~~ee~~|R/W<br>~~ee~~|2<br>~~ee~~|
|0x44<br>~~ee~~<br>~~GG~~|MFR_USER_PWD<br>~~ee~~<br>~~GG~~|W<br>~~ee~~<br>~~GG~~|2<br>~~ee~~<br>~~GG~~|
|0x45<br>~~GG~~|MFR_MTP_WP<br>~~GG~~|R/W<br>~~GG~~|1<br>~~GG~~|
|0x46<br>~~ee~~|SKIPDRMOS_SR_ERARLI<br>~~ee~~|R/W<br>~~ee~~|2<br>~~ee~~|
|0x49<br>~~ee~~<br>~~GG~~|MFR_IOUT_LEVEL<br>~~ee~~<br>~~GG~~|R/W<br>~~ee~~<br>~~GG~~|2<br>~~ee~~<br>~~GG~~|
|0x4B<br>~~GG~~|MFR_VCAL_I_MAX<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|
|0x4C<br>~~ee~~|DC_TRIM<br>~~ee~~|R/W<br>~~ee~~|1<br>~~ee~~|
|0x50<br>~~ee~~<br>~~GG~~|MPS_CODE<br>~~ee~~<br>~~GG~~|R/W<br>~~ee~~<br>~~GG~~|2<br>~~ee~~<br>~~GG~~|
|0x51<br>~~GG~~|PRODUCT_CODE<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|
|0x52<br>~~ee~~|CONFIG_ID<br>~~ee~~|R/W<br>~~ee~~|2<br>~~ee~~|
|0x53<br>~~ee~~<br>~~GG~~|CONFIG_REV<br>~~ee~~<br>~~GG~~|R/W<br>~~ee~~<br>~~GG~~|2<br>~~ee~~<br>~~GG~~|
|0x5A<br>~~GG~~|CALVO_LOW_TON_SS_L<br>~~GG~~|R/W<br>~~GG~~|2<br>~~GG~~|
|0x5B<br>~~ee~~|TON_SS_H<br>~~ee~~|R/W<br>~~ee~~|2<br>~~ee~~|
|0x5E<br>~~ee~~<br>~~a~~|POWER_GOOD_ON<br>~~ee~~|R/W<br>~~ee~~|2<br>~~ee~~|
|0x5F<br>~~Ge~~|POWER_GOOD_OFF<br>~~Ge~~|R/W<br>~~Ge~~|2<br>~~Ge~~|
|0x60<br>~~ee~~|PROTECT_DELAY<br>~~ee~~|R/W<br>~~ee~~|1<br>~~ee~~|
|0x62<br>~~ee~~<br>~~a~~|PWRGD_DELAY<br>~~ee~~|R/W<br>~~ee~~|1<br>~~ee~~|
|0x63<br>~~eG~~|START_DELAY<br>~~eG~~|R/W<br>~~eG~~|2<br>~~eG~~|
|0x64<br>~~eG~~<br>~~OG~~|OFF_DELAY<br>~~eG~~<br>~~OG~~|R/W<br>~~eG~~<br>~~OG~~|2<br>~~eG~~<br>~~OG~~|
|0x65<br>~~OG~~<br>~~Ge~~|MFR_OTP_SET<br>~~OG~~<br>~~Ge~~|R/W<br>~~OG~~<br>~~Ge~~|2<br>~~OG~~<br>~~Ge~~|
|0x66<br>~~eG~~|MFR_DIE_OTP_SET<br>~~eG~~|R/W<br>~~eG~~|2<br>~~eG~~|
|0x67<br>~~eG~~<br>~~a~~|PMBUS/I2C_ADDR_SET<br>~~eG~~|R/W<br>~~eG~~|1<br>~~eG~~|
|0x68<br>~~a~~<br>~~OG~~|MFR_PROTECT_CFG<br>~~OG~~|R/W<br>~~OG~~|2<br>~~OG~~|
|0x69<br>~~OG~~<br>~~GG~~|OVP_UVP_VID_SET<br>~~OG~~<br>~~GG~~|R/W<br>~~OG~~<br>~~GG~~|2<br>~~OG~~<br>~~GG~~|
|0x6A<br>~~OG~~|OCP_TDC_SET<br>~~OG~~|R/W<br>~~OG~~|2<br>~~OG~~|
|0x6B<br>~~ee~~|OCP_SPIKE_TIMES_SET<br>~~ee~~|R/W<br>~~ee~~|2<br>~~ee~~|
|0x6C<br>~~ee~~<br>~~GG~~|OCP_SPIKE_LEVEL<br>~~ee~~<br>~~GG~~|R/W<br>~~ee~~<br>~~GG~~|2<br>~~ee~~<br>~~GG~~|
|0x6D<br>~~OG~~|UVP_MIN_SET<br>~~OG~~|R/W<br>~~OG~~|1<br>~~OG~~|
|0x79<br>~~ee~~|STATUS_WORD<br>~~ee~~|R<br>~~ee~~|2<br>~~ee~~|
|0x7A<br>~~ee~~<br>~~GG~~|STATUS_VOUT<br>~~ee~~<br>~~GG~~|R<br>~~ee~~<br>~~GG~~|1<br>~~ee~~<br>~~GG~~|
|0x7B<br>~~OG~~|STATUS_IOUT<br>~~OG~~|R<br>~~OG~~|1<br>~~OG~~|
|0x7C<br>~~ee~~|PROTECT_SIG_GRP<br>~~ee~~|R<br>~~ee~~|2<br>~~ee~~|
|0x7D<br>~~ee~~<br>~~GG~~|STATUS_TEMP<br>~~ee~~<br>~~GG~~|R<br>~~ee~~<br>~~GG~~|1<br>~~ee~~<br>~~GG~~|
|0x7E<br>~~OG~~|STATUS_CML<br>~~OG~~|R<br>~~OG~~|1<br>~~OG~~|
|0x80<br>~~ee~~|SYS_STATE_DBG<br>~~ee~~|R<br>~~ee~~|1<br>~~ee~~|
|0x81<br>~~ee~~<br>~~ee~~|FINAL_PMBUS/I2C_ADDR<br>~~ee~~<br>~~ee~~|R<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|
|0x82<br>~~GD~~|REG_LAST_FAULT_MTP<br>~~GD~~|R<br>~~GD~~|2<br>~~GD~~|



**17** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** MPS 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ **PMBUS/I[2] C MEMORY PAGE 0 COMMANDS/REGISTERS** _**(continued)**_ 

|**Command Code**<br>~~ee~~|**Command Name**<br>~~ee~~|**Type**<br>~~ee~~|**Bytes**<br>~~ee~~|
|---|---|---|---|
|0x88<br>~~ee~~|READ_VIN|R|2|
|0x8B<br>~~ee~~<br>~~GG~~|READ_VOUT<br>~~GG~~|R<br>~~GG~~|2<br>~~GG~~|
|0x8C<br>~~GG~~|READ_IOUT<br>~~GG~~|R<br>~~GG~~|2<br>~~GG~~|
|0x8D<br>~~ee~~|READ_TEMP<br>~~ee~~|R<br>~~ee~~|1<br>~~ee~~|
|0x8E<br>~~ee~~<br>~~GG~~|READ_DIE_TEMP<br>~~ee~~<br>~~GG~~|R<br>~~ee~~<br>~~GG~~|1<br>~~ee~~<br>~~GG~~|
|0x90<br>~~GG~~|USER_KEY_INPUT<br>~~GG~~|W<br>~~GG~~|2<br>~~GG~~|
|0x96<br>~~ee~~|READ_POUT<br>~~ee~~|R<br>~~ee~~|2<br>~~ee~~|
|0x99<br>~~ee~~<br>~~a~~|VIN_SENSE<br>~~ee~~|R<br>~~ee~~|2<br>~~ee~~|
|0x9A<br>~~Ge~~|VOUT_SENSE<br>~~Ge~~|R<br>~~Ge~~|2<br>~~Ge~~|
|0x9B<br>~~ee~~|IOUT_SENSE<br>~~ee~~|R<br>~~ee~~|2<br>~~ee~~|
|0x9C<br>~~ee~~<br>~~a~~|TEMP_SENSE<br>~~ee~~|R<br>~~ee~~|2<br>~~ee~~|
|0x9D<br>~~Ge~~|DIE_TEMP_SENSE<br>~~Ge~~|R<br>~~Ge~~|2<br>~~Ge~~|
|0x9E<br>~~ee~~|TON_PWMP<br>~~ee~~|R<br>~~ee~~|2<br>~~ee~~|
|0x9F<br>~~ee~~<br>~~a~~|TON_SR_PWM<br>~~ee~~|R<br>~~ee~~|2<br>~~ee~~|
|0xF1<br>~~Ge~~|CLR_LAST_FAULT_WMTP<br>~~Ge~~|Send<br>~~Ge~~|0<br>~~Ge~~|
|0xF2<br>~~ee~~|READ_LAST_FAULT_TRIG<br>~~ee~~|Send<br>~~ee~~|0<br>~~ee~~|
|0xF3<br>~~ee~~<br>~~a~~|CLEAR_STORE_FAULTS<br>~~ee~~|Send<br>~~ee~~|0<br>~~ee~~|
|0xF4<br>~~Ge~~|CLEAR_MTP_FAULTS<br>~~Ge~~|Send<br>~~Ge~~|0<br>~~Ge~~|



**18** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **PAGE 0 REGISTER MAP** 

## **PAGE (00h)** 

The PAGE command configures, controls, and monitors the device through only one physical address to support normal operation, testing mode, and debugging mode. 

|**Command**<br>PAGE<br>**Format**<br>Unsigned binary<br>**Bit**<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>PAGE<br>~~SS~~|**Command**<br>PAGE<br>**Format**<br>Unsigned binary<br>**Bit**<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>PAGE<br>~~SS~~|**Command**<br>PAGE<br>**Format**<br>Unsigned binary<br>**Bit**<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>PAGE<br>~~SS~~|**Command**<br>PAGE<br>**Format**<br>Unsigned binary<br>**Bit**<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>PAGE<br>~~SS~~|**Command**<br>PAGE<br>**Format**<br>Unsigned binary<br>**Bit**<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>PAGE<br>~~SS~~|
|---|---|---|---|---|
|**Bits**|**Bit Name**||**Description**||
|7:2|RESERVED|RESERVED|Reserved. Bits[7:2] must set to 0 when changing bits[1:0].||
||||2’b00: Page 0. Normal and trim registers (read/write registers) can be stored in||
||||the MTP||
||||2’b01: Page 1. Unused||
|1:0|PAGE||2’b10: Page 2. Each PMBus/I2C command (not including (00h)) directly||
||||reads/writes to the MTP cells||
||||2’b11: Page 3. Debugging/testing registers. Not stored in the MTP||
||||Users should only use Page 0 to avoid unintentionally entering test mode.||



## **OPERATION (01h)** 

The OPERATION command turns the output on or off by working with the EN pin. The MPC1100A-540000 remains in the commanded operating mode until another different OPERATION command is sent, or the state of EN changes. 

|**Command**<br>OPERATION<br>**Format**<br>Unsigned binary<br>**Bit**<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>~~SS~~|**Command**<br>OPERATION<br>**Format**<br>Unsigned binary<br>**Bit**<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>~~SS~~|
|---|---|
|**Bits**<br>**Bit Name**<br>**Description**<br>7<br>OPERATION<br>1’b1: Turn on<br>1’b0: Turn off<br>6:0<br>RESERVED<br>Reserved. R/W bits are available, but do not change the device.<br>~~ee~~||
|**CLEAR_FAULTS (03h)**||
|The CLEAR_FAULTS command clears any fault bit in the following status registers: STATUS_WORD||
|(79h), STATUS_VOUT (7Ah), STATUS_IOUT (7Bh), STATUS_TEMP (7Dh), and STATUS_CML (7Eh).|(79h), STATUS_VOUT (7Ah), STATUS_IOUT (7Bh), STATUS_TEMP (7Dh), and STATUS_CML (7Eh).|



This command is write-only. There is no data byte for this command. 

## **CTRL_PWM (04h)** 

The CTRL_PWM command controls PWM operation. The positive and negative edges of the SR_PWM pins (SR_PWMs) can be adjusted using the PWMP pins. The SR_PWMs can be made to turn off earlier or later than the time set by the PWMP pins. 

|**Command**|CTRL_PWM|CTRL_PWM|CTRL_PWM|CTRL_PWM|CTRL_PWM|CTRL_PWM|CTRL_PWM|CTRL_PWM|CTRL_PWM|CTRL_PWM|CTRL_PWM|CTRL_PWM|CTRL_PWM|CTRL_PWM|CTRL_PWM|CTRL_PWM|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|Unsigned binary||||||||||||||||
|**Bit**|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|**Access**|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|**Function**|||||||||||||||||



**19** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com 

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

**==> picture [481 x 646] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||
|---|---|---|
|Bits|Bit Name|Description|
|15|RESERVED|Reserved. R/W bits are available, but do not change the device.|
|Enables setting the MP2981’s SKIP_EN pin high during soft start.|
|14|SKIP_SS_EN|1’b1: Enabled. The SKIP_EN pin is pulled high during soft start|
|1’b0: Disabled. The SKIP_EN pin is pulled low during soft start|
|Enables VOUT skipping. Determines what happens after VOUT ramps above|
|VOUT_SKIP_H (19h), bits[3:2], and before VOUT ramps below VOUT_SKIP_L|
|(19h), bits[1:0].|
|13|VOUT_SKIP_EN|
|1’b1: Shut down both SR_PWM pins during the dead time and after soft start. If|
|04h, bit[10] = 0, the primary PWMs also shut off|
|1’b0: No PWM shuts off|
|Enables the primary closed loop.|
|12|CLOSE_LOOP_EN|1’b1: Enabled|
|1’b0: Disabled|
|Enables the primary zero-current detection (ZCD) loop.|
|11|ZCD_LOOP_EN|1’b1: Enabled|
|1’b0: Disabled|
|Determines how the part responds when VOUT skipping is enabled and VOUT|
|exceeds its limit.|
|10|VOUT_SKIP_PWMP_EN|
|1’b1: PWMP remains on when VOUT exceeds its limit during skip mode|
|1’b0: PWMP turns off when VOUT exceeds its limit during skip mode|
|Shuts off SR_PWM if the chip detects that VIN is dropping quickly, or VOSEN|
|exceeds the VIN ADC value.|
|9|SKIPSR_VIN_DROP_EN|
|1’b1: Enabled|
|1’b0: Disabled|
|8:7|RESERVED|Reserved. R/W bits are available, but do not change the device.|
|Adjusts whether the SR_PWMs turn on/off before or after the PWMP pins.|
|1’b1: Enabled. If 0Fh, bit[15] and 04h, bits[4:1] are set to 1’b1, then this bit should|
|6|SR_ADJ_NORMAL_EN|be set to 1’b1|
|1’b0: Disabled. If 0Fh, bit[15] and 04h, bits[4:1] are set to 1’b0, then this bit should|
|be set to 1’b0|
|Shuts off SR_PWM after or before PWMP during soft start, according to tON. This|
|bit is related to registers 5Ah, 5Bh, and 2Bh.|
|5|SR_NEG_ADJ_SS_EN|
|1’b1: Enabled|
|1’b0: Disabled|
|Shuts off SR_PWM a fixed time before PWMP. Related to register 2Ah.|
|4|SR_FIXED_DEC_EN|1’b1: Enabled|
|1’b0: Disabled|
|Shuts off SR_PWM a fixed time after PWMP. Related to register 2Ah.|
|3|SR_FIXED_EXT_EN|1’b1: Enabled|
|1’b0: Disabled|
|Shuts off SR_PWM a fixed time before the next PWMP. Related to register 2Ch.|
|2|SR_NEG_ADJ_EN|1’b1: Enabled|
|1’b0: Disabled|
|Turns on SR_PWM after PWMP. Related to register 2Ch.|
|1|SR_POS_DEC_EN|1’b1: Enabled|
|1’b0: Disabled|

**----- End of picture text -----**<br>


**20** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** MPS 

0 SR_EN 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ Makes SR_PWM equal to PWMP if no other adjusting function is enabled. Only enabled when the part is not in soft start, and 04h, bit[6] = 0. 1’b1: SR_PWM = PWMP 1’b0: SR_PWM = 0 

## **MFR_ADC_HOLD_TIME (05h)** 

The MFR_ADC_HOLD_TIME command sets the waiting time between finishing one channel sampling and starting the next channel sampling. **Command** MFR_ADC_HOLD_TIME **Format** Unsigned binary **Bit** 7 6 5 4 3 2 1 0 **Access** R R/W R/W R/W R/W R/W R/W R/W ~~==~~ **Function** X MFR_ADC_HOLD_TIME **Bits Bit Name Description** 7 RESERVED Not defined. Read-only. The time after one channel finishes, and before the next channel starts. 6:0 MFR_ADC_HOLD_TIME 100ns/LSB. ~~a~~ 

**CTRL_VR (06h)** The CTRL_VR command configures certain chip functions, excluding pulse-width modulation (PWM). 

**==> picture [496 x 360] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Command|CTRL_VR|
|Format|Unsigned binary|
|Bit|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|Access|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|Function|
|Bits|Bit Name|Description|
|15|RESERVED|Reserved. R/W bits are available, but do not change the device.|
|Controls the analog output to enable bandgap (BG) chop.|
|14|CHOP_BG|1’b1: Enabled|
|1’b0: Disabled|
|Selects the PSYS current rate by sending different READ_POUT (96h) data.|
|13|PSYS_SEL_2W|1’b1: 2 with LSB, send READ_POUT (96h), bits[10:1] to the 10-bit PSYS digital-|
|to-analog converter (DAC)|
|1’b0: 1 with LSB, send READ_POUT (96h), bits[9:0] to the DAC|
|Enables the DC loop.|
|12|DC_CAL_EN|1’b1: Enabled|
|1’b0: Disabled|
|Selects the die temperature’s voltage vs. temperature (V-T) rate.|
|11|DIE_TEMP_RATE_NEG|
|1’b1: Negative|
|1’b0: Positive|
|10:9|RESERVED|Reserved. R/W bits are available, but do not change the device.|
|1’b1: The ADC constantly samples the ADDRP pin|
|PMBUS/I|[2]|C_ADDR_|
|8|1’b0: The ADC samples ADDRP only seven times after the MTP address reaches|
|KEEP_SAMP|
|8’h20|
|7:4|PMBUS/I|[2]|C_FILTER_SET|PMBus/I|[2]|C filter on the digital side. 10ns/LSB.|

**----- End of picture text -----**<br>


**21** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

|3|WAIT_VIN_START|1’b1: Wait until VINis ready (READ_VIN > VIN_ON) before ramping VREFand<br>generating PWMs<br>1’b0: Do not wait until VINis ready (READ_VIN > VIN_ON) before ramping VREF<br>and generating PWMs|
|---|---|---|
|2|SEL_PWRGD_1REF_<br>0TON|Selects VREFramping or tONincreasing to act as the PG reference.<br>1’b1: VREF<br>1’b0: tON|
|1|MFR_ONOFFDLY_CLK_<br>1L0S|Selects the counting clock for START_DELAY and OFF_DELAY during start-up<br>and shutdown.<br>1’b1: 20kHz<br>1’b0: 50kHz|
|0|KEEP_TON_MIN_LMT_SS|Determines the VOUTthreshold before increasing tONduring soft start.<br>1’b1: tONstays at the TON_MIN_LIM (1Fh) value and does not increase until VOUT<br>exceeds VOUT UVP_MIN (19h)<br>1’b0: tONdoes not stay at the TON_MIN_LIM (1Fh) value, and begins increasing<br>before VOUTexceeds VOUT UVP_MIN (19h)|



## **CTRL_MTP (07h)** 

The CTRL_MTP command sets the MTP parameters. It is recommended to use the vendor’s preset configurations. 

|**Bits**|**Bit Name**|**Description**|
|---|---|---|
|15|CRC_FAULT_USER_EN|Enables cyclic redundancy check (CRC) for the MTP user.<br>1’b1: Enabled<br>1’b0: Disabled|
|14|CRC_FAULT_TRIM_EN|Enables CRC for the MTP trim.<br>1’b1: Enabled<br>1’b0: Disabled|
|13|CRC_FAULT_TOT_EN|Enables CRC for the total MTP. Do not set this bit to 1 when using 17h<br>(STORE_USER_ALL) to write to the MTP.<br>1’b1: Enabled<br>1’b0: Disabled|
|12|MTP_FAULT_BLOCK_<br>EN|Determines whether an MTP fault prevents start-up, including the signature fault<br>and CRC fault.<br>1’b1: Enabled. If an MTP fault occurs, the chip enters the MTP fault state, and a<br>CLEAR_MTP_FAULTS (F4h) command must be sent to exit the state<br>1’b0: Disabled. The chip starts up if an MTP fault occurs|
|11|LAST_FAULT_BLOCK_<br>EN|Prevents start-up if the data read from the MTP LAST_FAULT_ADDR is not 0.<br>1’b1: Enabled. If the last fault exists, the chip must receive a<br>CLEAR_STORE_FAULTS (F3h) command to start up<br>1’b0: Disabled. The chip starts up, even if the last fault exists|
|10:6|RESERVED|Reserved. R/W bits are available, but do not change the device.|



**22** 

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|**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE**|**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE**|**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE**|
|---|---|---|
|**_NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002_**|||
|5<br>CAL_FAULT_CRC_DIS<br>1’b1: Do not include MTP_FAULT_RECORD_ADDR (the 2 bytes in the MTP that<br>store protection faults, such as OVP) when calculating CRC_TOT<br>1’b0: Include MTP_FAULT_RECORD_ADDR when calculating CRC_TOT<br>4<br>NO_FAULT_STORE<br>1’b1: Store 00h data to MTP_FAULT_RECORD_ADDR<br>1’b0: Store the value of MEMORY_ADDR (7Ah) to<br>MTP_FAULT_RECORD_ADDR when storing is not triggered by a fault<br>3<br>FAULT_SINGLE_EN<br>1’b1: Only store the 2-byte MTP_FAULT_RECORD_ADDR<br>1’b0: Store the whole third section of the MTP when storing FAULT_RECORD<br>2<br>RESERVED<br>Reserved. R/W bits are available, but do not change the device.<br>1<br>PROTECT_FAULT_<br>RECORD_EN<br>Enables FAULT_RECORD.<br>1’b1: Enabled<br>1’b0: Disabled<br>0<br>MFR_MTP_COPY_EN<br>Reads the MTP (16h or 18h or F6h) when the device outputs power; ineffective<br>for the READ_LAST_FAULT command (F2h) or the reading MTP commands (16h<br>or 18h or F6h) on Page 2.<br>1’b1: Enabled<br>1’b0: Disabled<br>~~—~~|||
|**CTRL_OC (08h)**|||
|The CTRL_OC command configures the over-current (OC) spike function. The PWM tONis reduced when|||
|an OC spike occurs, and recovers after the OC spike condition is removed (see Figure 12). This|||
|protection cannot directly shut down the chip.|||
|PWMP1|||
|TON_MIN_<br>Valid Area|||
|OCSPK_H|||
|PWMP2|||



**==> picture [102 x 17] intentionally omitted <==**

**----- Start of picture text -----**<br>
TON_MIN_ Valid Area<br>OCSPK_H<br>**----- End of picture text -----**<br>


## **Figure 12: OCSPK_H** 

|**Bits**|**Bit Name**|**Description**|
|---|---|---|
|15:12|SR_DLY_OCSPK|Sets the time lengths of the SR_PWM pins’ wait period before turning off after the<br>PWMP pins when an over-current (OC) spike occurs. If any bit between bits[6:4]<br>of this command is high, there must be a <1Bh (dead time setting). 5ns/LSB.|
|11:8|TON_MIN_OCSPK_H|If an OC spike occurs on CS1 (OCSPK_H), the minimum tONcan be calculated<br>with the equation below:<br>(TON_MIN_OCSPK_H + 1) x 5ns|
|7|RESERVED|Reserved. R/W bits are available, but do not change the device.|
|6|SR_DLY_OCSPK_H_<br>SS_EN|Turns off the SR_PWM pins after the PWMP pins if an OC spike occurs on CS1<br>(OCSPK_H) during soft start.<br>1’b1: Enabled<br>1’b0: Disabled|



**23** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

**==> picture [475 x 304] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||
|---|---|---|
|Turns off the SR_PWM pins after the PWMP pins if an OC spike occurs on CS1|
|(OCSPK_H) during a time that is not soft start.|
|5|SR_DLY_OCSPK_H_EN|
|1’b1: Enabled|
|1’b0: Disabled|
|Turns off the SR_PWM pins after the PWMP pins if an OC spike occurs on CS1|
|(OCSPK_H) during normal operation.|
|4|SR_DLY_OCSPK_L_EN|
|1’b1: Enabled. Bit[5] must be set to 1’b1|
|1’b0: Disabled|
|Turns on the SR_PWM pins immediately if they are not on when an OC spike|
|occurs on CS1 or CS2 (OCSPK_H or OCSPK_L, respectively) while PWMP is on.|
|3|OC_TRIG_SR_EN|
|1’b1: Enabled|
|1’b0: Disabled|
|Adjusts tON if an OC spike occurs on CS1 (OCSPK_H) during soft start.|
|OCSPK_H_TON_SS_|
|2|EN|1’b1: Enabled|
|1’b0: Disabled|
|Adjusts tON if an OC spike occurs on CS1 (OCSPK_H) during a time that is not soft|
|start.|
|1|OCSPK_H_TON_EN|
|1’b1: Enabled|
|1’b0: Disabled|
|Adjusts tON if an OC spike occurs on CS2 (OCSPK_L). This cannot be adjusted|
|during soft start.|
|0|OCSPK_L_TON_EN|
|1’b1: Enabled|
|1’b0: Disabled|

**----- End of picture text -----**<br>


## **LOW_POWER_SET_BIT (09h)** 

The LOW_POWER_SET_BIT command controls low-power mode. 

**==> picture [504 x 147] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||||||
|---|---|---|---|---|---|---|---|---|
|Command|LOW_POWER_SET_BIT|
|Format|Unsigned binary|
|Bit|7|6|5|4|3|2|1|0|
|Access|R|R|R|R|R|R|R/W|R/W|
|Function|X|X|X|X|X|X|
|SSS|
|Bits|Bit Name|Description|
|7:2|RESERVED|Not defined. Read-only.|
|1|RESERVED|Reserved. R/W bits are available, but do not change the device.|
|1’b1: The chip remains in low-power mode when the EN pin is low|
|0|LOW_POWER_SET_BIT|
|1’b0: The chip operates normally when the EN pin is low|

**----- End of picture text -----**<br>


## **ZCD_TIME_SET (0Bh)** 

The ZCD_TIME_SET command configures frequency adjusting via the zero-current detection (ZCD) function (primary ZCD loop). Figure 13 on page 25 shows the valid ZCD1 area for this function. The valid ZCD2 area is determined by SR_PWM2. When ZCD occurs within the valid area, tON decreases by WEIGHTN_ZCD (29h), bits[15:8]. When a ZCD event occurs outside the valid area, tON increases by WEIGHTP_ZCD (29h), bits[6:0]. 

Frequency adjusting completes if the following conditions are met: 

- The difference between neighboring tON values is within ZCDLOOP_HYS (0Bh), bits[10:8] for more than 256 periods. 

- There is no load change, or another conditional change. 

**24** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

**==> picture [360 x 64] intentionally omitted <==**

**----- Start of picture text -----**<br>
SR_PWM1<br>((0Bh, bits[3:0]) x 2 + 1) x 5ns<br>Valid ZCD1  (ZCD_BLK_TIME x 2 + 1) x 5ns<br>Area<br>(0Bh, bits[6:4]) x 5ns<br>ZCD_VALID_DLY x 5ns<br>**----- End of picture text -----**<br>


## **Figure 13: Valid ZCD1 Area for ZCD Loop Function** 

|**Bits**|**Bit Name**|**Description**|
|---|---|---|
|15:11|RESERVED|Not defined. Read-only.|
|10:8|ZCDLOOP_HYS|When tONstays between TON_LAST_PERIOD ± ZCDLOOP_HYS for about 256<br>periods, the loop is stable. 5ns/LSB.|
|7|RESERVED|Reserved. R/W bits are available, but do not change the device.|
|6:4|ZCD_VALID_DLY|The ZCD valid area after the delayed SR_PWM. 5ns/LSB.|
|3:0|ZCD_BLK_TIME|The beginning area of SR_PWM is invalid for ZCD. 10ns/LSB. The ZCD blanking<br>time can be calculated with the following equation:<br>ZCD blanking time = (ZCD_BLK_TIME x 2 + 1) x 5ns|



## **ZCD_LOOP_SET (0Ch)** 

The ZCD_LOOP_SET command configures the adjusting frequency via the zero-current detection (ZCD) function (primary ZCD loop). If ZCDLOOP_LATCHTON_EN (0Ch), bit[5] is enabled and the frequency adjustment finishes (tON stays within the hysteresis threshold for more than 256 periods), then tON is fixed to TON_ZCDLOOP_DEC (0Fh), bits[11:8] (the 256th tON). If ZCDLOOP_LATCHTON_EN (0Ch), bit[5] is not enabled, then the adjustment continues calculating. If ZCDLOOP_LOADLMT_EN (0Ch), bit[4] = 1, then the ZCD loop is only enabled when the TDC current is within the load limitation. 

|**Bits**|**Bit Name**|**Description**|
|---|---|---|
|15|LOADLOW_ZCDLOOP_EN|Enables the ZCD loop when the voltage of the CS1 pin drops below the skip<br>SR_PWMs level (1Ah, bit[8] and 1Ah, bits[3:0]) or (READ_IOUT (8Ch) / 2) is<br>below or equal to MFR_IOUT_LEVEL_L (49h), bits[7:0]).<br>1’b1: Enables the ZCD loop function<br>1’b0: Disables the ZCD loop function|
|14:8|ZCDLOOP_LOADLMT_H|The load’s high limit to enable the ZCD loop compared to READ_IOUT / 8 (from<br>ADC sampling and then calculation). 2A/LSB.|
|7:6|RESERVED|Reserved. R/W bits are available, but do not change the device.|
|5|ZCDLOOP_LATCHTON_EN|Latches tONafter tONstays in hysteresis for 256 periods.<br>1’b1: Enabled<br>1’b0: Disabled|



**25** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

|4|ZCDLOOP_LOADLMT_EN|Enables the load limitation for the ZCD loop.<br>1’b1: Enabled<br>1’b0: Disabled|
|---|---|---|
|3:0|ZCDLOOP_LOADLMT_L|The load’s low limit to enable the ZCD loop compared to READ_IOUT / 4 (from<br>ADC sampling and then calculation). 1A/LSB.|



## **SKIP_SR_PWM_SET (0Eh)** 

The SKIP_SR_PWM_SET command configures the function that allows the SR_PWMs to be skipped under light-load conditions. Figure 14 shows the valid skip areas. When the CS1 pin is below CMP_CS1_ENTERFREQ (1Ah), the signal from CMP_CS1_ENTERFREQ goes high. The valid area to detect this comparator output to enter skip mode is defined below by bits[10:0]. This command is only valid for phase 1. 

|PWM1<br>PWM1_DLYED|PWM1<br>PWM1_DLYED|PWM1<br>PWM1_DLYED||(2Ah, bits[3:0]+1) x 5ns|(2Ah, bits[3:0]+1) x 5ns|(2Ah, bits[3:0]+1) x 5ns|(2Ah, bits[3:0]+1) x 5ns||(2Ah,|(2Ah,|(2Ah,||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||||||bits[3:0]+1) x||||||||||
|||||||||||5ns|||||||||
||Valid||||||||||||||||||
||Area||||||||||||||||||
||||BLKP x 10ns + 5ns||||BLKP x 10ns + 5ns||SEL = 1<br>BLKN x 10ns||||||||||
|||||||||||||SEL = 0|SEL = 0||||||
||Valid<br>Area|(2Ah, bits[3:0] + 2 - BLKN) x<br>5ns<br>0 < BLKN   2Ah, bits[3:0]<br>Valid<br>~~ph~~|||||||||||||||||
||Valid<br>Area|Valid|||||||5ns<br>SEL = 1, BLKN = 0|||||(2Ah, bits[3:0] + 2) x|||||
|||||||||||||||5ns|||||
||Valid|||||||||||5ns|||||||
||Area||||||||SEL = 0, BLKN > 2Ah, bits[3:0]||||||||||
||||||||**Figure 14: Valid Skip Area**||||||||||||
|**Command**|||||||||SKIP_SR_PWM_SET||||||||||
|**Format**|||||||||Unsigned binary||||||||||
|**Bit**|15|14|13||12||11<br>10||9<br>8<br>7<br>6||5|4||3||2|1|0|
|**Access**|R/W<br>R/W||R/W||R/W||R/W<br>R/W|R/W<br>R/W<br>R/W<br>R/W||R/W|R/W<br>R/W|||R/W|R/W||R/W|R/W|
|**Function**|||||||SEL||SKIP_SR_PWM_BLKN_SEL|||||SKIP_SR_PWM_BLKN|||||
||||||||||||||||||||
|**Bits**|**Bit Name**||||||**Description**|**tion**|||||||||||
||||||||Turns off SR_PWM when CS is low.||||||||||||
|15|SKIP_SR_PWM_EN||||||1’b1: Enabled||||||||||||
||||||||1’b0: Disabled||||||||||||
|14:12|SKIP_SR_PWM_NUM||||||Sets the off time for the SR_PWM periods. After the skip delay, the<br>SKIP_SR_PWM_NUM and SR_PWM periods (phase 1 and 2) are skipped.||||||||||||
|11|RESERVED||RESERVED||||Reserved. R/W bits are available, but do not change the device.||Reserved. R/W bits are available, but do not change the device.||Reserved. R/W bits are available, but do not change the device.|||||Reserved. R/W bits are available, but do not change the device.|||



**26** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

|10|SKIP_SR_PWM_BLKN_<br>SEL|Selects the valid area of SKIP_SR_PWM before or after the PWM1 pull-down<br>pulse.<br>1’b1: The valid area is before the PWM1 pull-down pulse<br>1’b0: The valid area is after the PWM1 pull-down pulse|
|---|---|---|
|9:4|SKIP_SR_PWM_BLKP|Sets the blanking time of the valid area after a PWM1 pull-up pulse. The blanking<br>time can be estimated with the equation below:<br>Skip blank time = (SKIP_SR_PWM_BLKP x 10ns + 5ns)|
|3:0|SKIP_SR_PWM_BLKN|Sets the blanking time for the valid area border to the PWM1 pull-down pulse. If<br>SKIP_SR_PWM_BLKN_SEL = 1, the valid area border ahead of the PWM1 pull-<br>down pulse is SKIP_SR_PWM_BLKN x 10ns. If SKIP_SR_PWM_BLKN_SEL = 0,<br>the valid area border after the PWM1 pull-down pulse changes is based on the<br>following scenarios:<br>•SKIP_SR_PWM_BLKN = 0: 5ns<br>•0 < SKIP_SR_PWM_BLKN < 2Ah, bits[3:0]: (2Ah, bits[3:0] + 2 x<br>SKIP_SR_PWM_BLKN) x 5ns<br>•SKIP_SR_PWM_BLKN > 2Ah, bits[3:0]: (2Ah, bits[3:0] + 2) x 5ns|



## **CTRL_PWM_BK (0Fh)** 

The CTRL_PWM_BK command sets the PWM working options. 

|**Command**|CTRL_PWM_BK|CTRL_PWM_BK|CTRL_PWM_BK|CTRL_PWM_BK|CTRL_PWM_BK|CTRL_PWM_BK|CTRL_PWM_BK|CTRL_PWM_BK|CTRL_PWM_BK|CTRL_PWM_BK|CTRL_PWM_BK|CTRL_PWM_BK|CTRL_PWM_BK|CTRL_PWM_BK|CTRL_PWM_BK|CTRL_PWM_BK|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|Unsigned binary||||||||||||||||
|**Bit**|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|**Access**|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|**Function**|||||TON_ZCDLOOP_DEC||||||||||||



|**Bits**|**Bit Name**|**Description**|
|---|---|---|
|15|SR_POS_EARLIERER<br>_EN|Turns on SR_PWM before PWMP. Related to 46h.<br>1’b1: Enabled<br>1’b0: Disabled|
|14|SEL_ZCD_NEG|1’b1: ZCD negative edge effective<br>1’b0: ZCD positive edge effective|
|13|CALVOUT_LOW_LMT_<br>TONL|1’b1: Disable the function that makes the SR_PWMs turn off after the PWMP pins<br>when READ_VOUT, bits[8:1] exceeds CALVOUT_LOW_LVL, bits[5:0]<br>1’b0: Enable the SR_PWMs to always turn off after the PWMPs|
|12|RM_VOUTLOW_SS_<br>TONLOW|1’b1: Disable the turn off later function during the VOUTlow stage. The VOUTlow area<br>(VOSEN < level, tONkeeps TON_MIN_LIM) during soft start is not included in TONLL<br>or TONL<br>1’b0: Enable the SR_PWM pins to turn off after the PWMP pins|
|11:8|TON_ZCDLOOP_DEC|If ZCDLOOP_LATCHTON_EN is enabled, tONis fixed to the tONvalue at the 256th<br>cycle. 5ns/LSB. tONcan be calculated with the following equation:<br>tON- TON_ZCDLOOP_DEC x 5ns|
|7|RESERVED|Reserved. R/W bits are available, but do not change the device.|
|6|ZCD1_EN|Enables ZCD1.<br>1’b1: Enabled<br>1’b0: Disabled|
|5|ZCD2_EN|Enables ZCD2.<br>1’b1: Enabled<br>1’b0: Disabled|



**27** 

MPC1100A-54-0000 Rev. 1.0 MonolithicPower.com 3/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** MPS _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 1’b1: ZCD2 = ZCD2 pin 4 SR_ZCD_SEPARATE 1’b0: ZCD2 = ZCD1 pin 3:0 RESERVED Reserved. R/W bits are available, but do not change the device. ~~pp~~ 

**STORE_ALL (15h)** The STORE_ALL command instructs the PMBus/I[2] C slave device to copy the R/W contents from the Page 0 registers of the operating memory to the matching locations in the MTP when the command is sent for Page 0, Page 1, or Page 3 (not for Page 2). 

This command can be used while the device is outputting power. 

This command is write-only. There is no data byte for this command. Other unused MTP addresses are written to 0. 

## **RESTORE_ALL (16h)** 

The RESTORE_ALL command instructs the PMBus/I[2] C slave device to copy the contents of the MTP to the matching locations in the operating memory. The values in the operating memory are overwritten by the value retrieved from the MTP. Any items that do not have matching locations in the operating memory are ignored. 

This command cannot be used while the device is outputting power, unless MFR_MTP_COPY_EN (register 07h, bit[0] on Page 0) is set to 1. 

This command is write-only. There is no data byte for this command. 

## **STORE_USER_ALL (17h)** 

The STORE_USER_ALL command instructs the PMBus/I[2] C slave device to copy the read and write Page 0 registers of the operating memory (except the trim registers) to the matching locations in the MTP (inside MTP address 8’h00 to 8’hDF) when the command is sent for Page 0, Page 1, or Page 3 (not for Page 2). 

This command can be used while the device is outputting power. 

This command is write-only. There is no data byte for this command. Other unused MTP addresses inside the MTP addresses 8’h00 to 8’hDF are written to 0. 

## **RESTORE_USER_ALL (18h)** 

The RESTORE_USER_ALL command instructs the PMBus/I[2] C slave device to copy the R/W contents of the MTP addresses 8’h00 to 8’hDF to the matching locations in the operating memory. The values in the operating memory are overwritten by the value retrieved from the MTP. Any items that do not have matching locations in the operating memory are ignored. 

This command cannot be used while the device is outputting power, unless MFR_MTP_COPY_EN (register 07h, bit[0] on Page 0) is set to 1. 

This command is write-only. There is no data byte for this command. 

## **MFR_VOUT_SEL (19h)** 

The MFR_VOUT_SEL command configures VOUT_OVP_MAX, OVP_VID, UVP_VID, UVP_MIN, and VOUT_SKIP, then compares these values to the VOSEN pin. 

|**Command**|MFR_VOUT_SEL|MFR_VOUT_SEL|MFR_VOUT_SEL|MFR_VOUT_SEL|MFR_VOUT_SEL|MFR_VOUT_SEL|MFR_VOUT_SEL|MFR_VOUT_SEL|MFR_VOUT_SEL|MFR_VOUT_SEL|MFR_VOUT_SEL|MFR_VOUT_SEL|MFR_VOUT_SEL|MFR_VOUT_SEL|MFR_VOUT_SEL|MFR_VOUT_SEL|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|Unsigned binary||||||||||||||||
|**Bit**|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|**Access**|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|**Function**||||OVP_MAX|||OVP_VID||UVP_VID||UVP_MIN||SKIP_H||SKIP_L||



**28** 

MPC1100A-54-0000 Rev. 1.0 MonolithicPower.com 3/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

|**Bits**|**Bit Name**|**Description**|
|---|---|---|
|15:13|RESERVED|Reserved. R/W bits are available, but do not change the device.|
|12:10|OVP_MAX_LVL_SEL|See the tables below for more information.<br>The VREFlevel in OVP_VID, UVP_VID, and VOUT_SKIP is the VOUTreference<br>DAC output (e.g. 21h, bits[7:0] x 6.25mV).|
|9:8|OVP_VID_LVL_SEL||
|7:6|UVP_VID_LVL_SEL||
|5:4|UVP_MIN_LVL_SEL||
|3:2|VOUT_SKIP_H_SEL||
|1:0|VOUT_SKIP_L_SEL||



**OVP_MAX_LVL_SEL** 0 1 2 3 4 5 6 7 **OVP_MAX Level (V)** 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 **Level Select 0 1 2 3** OVP_VID_LVL_SEL, OVP_VID level (V) 140% of VREF 130% of VREF 120% of VREF 110% of VREF UVP_VID_LVL_SEL, UVP_VID level (V) 90% of VREF 80% of VREF 70% of VREF 60% of VREF UVP_MIN_LVL_SEL, 0.3 0.4 0.5 0.6 UVP_MIN level (V) VOUT_SKIP_H_SEL, VOUT_SKIP_H level (V) VREF + 50mV VREF + 40mV VREF + 30mV VREF + 20mV VOUT_SKIP_L_SEL, ~~===55=~~ VOUT_SKIP_L level (V) VREF + 40mV VREF + 30mV VREF + 20mV VREF + 10mV **MFR_IOUT_SEL (1Ah)** The MFR_IOUT_SEL command configures the light-load levels (CMP_CS1_EXITSKIP and CMP_CS1_ENTERFREQ), which are compared to the CS1 pin. After CS1 exceeds CMP_CS1_EXITSKIP, the DrMOS stops skipping (SKIP_DRMOS_EN). When CS1 drops below CMP_CS1_ENTERFREQ, the SR_PWMs skip after a delay (SKIP_SR_PWM_EN) for a configurable number of PWM periods. 

|**Bits**|**Bit Name**|**Description**|
|---|---|---|
|15:11|RESERVED|Reserved. R/W bits are available, but do not change the device.|
|10:9|CMP_CS1_EXITSKIP_<br>GAIN|Selects the current level’s analog buffer gain when exiting skip mode.<br>2’b0x: Gain = 1<br>2’b10: Gain = 2<br>2’b11: Gain = 4|
|8|CMP_CS1_ENTERFREQ<br>_GAIN|Selects the current level’s analog buffer gain when entering skip mode.<br>1’b1: Gain = 2<br>1’b0: Gain = 1|
|7:4|CMP_CS1_EXITSKIP_<br>SEL|The final level is determined by bits[7:4], multiplied by the buffer gain.|
|3:0|CMP_CS1_ENTERFREQ<br>_SEL|The final level is determined by bits[3:0], multiplied by the buffer gain.|



**29** 

MPC1100A-54-0000 Rev. 1.0 MonolithicPower.com 3/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

Table 3 lists the values for CMP_CS1_EXITSKIP. Table 4 lists the values for CMP_CS1_ENTER. 

||**Table 3: CMP_CS1_EXITSKIP Values                                Table 4: CMP_CS1_ENTER Values**|**Table 3: CMP_CS1_EXITSKIP Values                                Table 4: CMP_CS1_ENTER Values**|**Table 3: CMP_CS1_EXITSKIP Values                                Table 4: CMP_CS1_ENTER Values**|**Table 3: CMP_CS1_EXITSKIP Values                                Table 4: CMP_CS1_ENTER Values**|**Table 3: CMP_CS1_EXITSKIP Values                                Table 4: CMP_CS1_ENTER Values**|**Table 3: CMP_CS1_EXITSKIP Values                                Table 4: CMP_CS1_ENTER Values**|**Table 3: CMP_CS1_EXITSKIP Values                                Table 4: CMP_CS1_ENTER Values**|**Table 3: CMP_CS1_EXITSKIP Values                                Table 4: CMP_CS1_ENTER Values**|**Table 3: CMP_CS1_EXITSKIP Values                                Table 4: CMP_CS1_ENTER Values**|
|---|---|---|---|---|---|---|---|---|---|
||**CMP_CS1_**<br>**EXITSKIP (V)**|**CMP_CS1_EXITSKIP_**<br>**GAIN, Bits[10:9]**<br>**0 or 1**<br>**2**<br>**3**|||||**CMP_CS1_**<br>**ENTERFREQ (V)**<br>**CMP_CS1_**<br>**ENTERFREQ_GAIN,**<br>**Bit[8]**<br>**0**<br>**1**<br>~~=~~|||
||**CMP_CS1_**<br>**EXITSKIP_SEL,**<br>**Bits[3:0]**<br>**Mul 1**<br>**Mul 2**<br>**Mul 4**<br>0<br>0.08<br>0.160<br>0.320<br>~~li~~||||||**CMP_CS1_**<br>**ENTERFREQ_SEL,**<br>**Bits[3:0]**<br>0|**Mul 1**<br>0.03|**Mul 2**<br>0.06|
||1|0.085||0.170|0.340||1|0.035|0.070|
||2|0.09||0.180|0.360||2|0.04|0.080|
||3|0.095||0.190|0.380||3|0.045|0.090|
||4|0.1||0.200|0.400||4|0.05|0.100|
||5|0.105||0.210|0.420||5|0.055|0.110|
||6|0.11||0.220|0.440||6|0.06|0.120|
||7|0.115||0.230|0.460||7|0.065|0.130|
||8|0.12||0.240|0.480||8|0.07|0.140|
||9|0.125||0.250|0.500||9|0.075|0.150|
||10|0.13||0.260|0.520||10|0.08|0.160|
||11|0.135||0.270|0.540||11|0.085|0.170|
||12|0.14||0.280|0.560||12|0.09|0.180|
||13|0.145||0.290|0.580||13|0.095|0.190|
||14|0.15||0.300|0.600||14|0.1|0.200|
||15|0.155||0.310|0.620||15|0.105|0.21|



## **DEAD_TIME (1Bh)** 

The DEAD_TIME command sets the normal working dead time. During soft start, tON begins at TON_MIN_LIM (1Fh), bits[13:8], and the dead time is (TON_MIN (1Ch) + DEAD_TIME (1Bh) - TON_MIN_LIM). After VOUT reaches UVP_MIN and the KEEP_TON_MIN_LMT_SS bit (06h, bit[0]) is set high, tON starts increasing. At the same time, the dead time decreases but remains at the same frequency (see Figure 15 on page 31). 

If KEEP_TON_MIN_LMT_SS is not enabled, then tON and the dead time start immediately. When tON reaches TON_MIN, the dead time is DEAD_TIME (1Bh). The dead time remains at this value, tON keeps ramping until tON equals TON_NORMAL (1Eh), and soft start completes. For more details on the tON increasing speed, see the PRISETBLK_WEIGHT_SS section on page 36. 

|**Command**<br>DEAD_TIME<br>**Format**<br>Unsigned binary<br>**Bit**<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>X<br>DEAD_TIME<br>~~=~~|
|---|
|**Bits**<br>**Bit Name**<br>**Description**<br>7<br>RESERVED<br>Not defined. Read-only.<br>6:0<br>DEAD_TIME<br>The real normal working dead time = ([6:0] + 1) x 5ns.<br>~~———~~|
|MPC1100A-54-0000 Rev. 1.0<br>MonolithicPower.com<br>**30**|
|3/5/2021<br>MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.|
|© 2022 MPS. All Rights Reserved.|



**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

**==> picture [441 x 274] intentionally omitted <==**

**----- Start of picture text -----**<br>
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002<br>Dead Time<br>TON_MIN + DEAD_TIME (1Bh) -<br>TON_MIN_LIM<br>DEAD_TIME (1Bh)<br>SN<br>Time<br>tON<br>TON_NORMAL<br>Frequency<br>Fixed Frequency Decreasing<br>TON_MIN<br>TON_MIN_LIM<br>VOUT Reaches  Time<br>UVP_MINl<br>**----- End of picture text -----**<br>


**Figure 15: Soft Start tON and Dead Time** 

## **TON_MIN (1Ch)** 

The TON_MIN command sets the minimum tON in the zero-current detection (ZCD) loop and primary closed loop. It is also the end of soft start’s first stage. For more details, see the DEAD_TIME (1Bh) section on page 30. 

|**Command**|||||||||TON_MIN|TON_MIN|||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**||||||||Unsigned binary|||||||||||
|**Bit**|15|14||13|12|11|10|9|8|7||6|5|4|3|2|1|0|
|**Access**|R|R||R|R|R|R|R/W|R/W|R/W||R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|**Function**|X|X||X|X|X|X||||||TON_MIN||||||
||||||||||||||||||||
|**Bits**|**Bit Name**|||||**Description**||**tion**|||||||||||
|15:10|RESERVED|||||Not defined. Read-only.||Not defined. Read-only.|||||||||||
|9:0|TON_MIN|||||5ns/LSB.|||||||||||||



## **TON_MAX (1Dh)** 

The TON_MAX command sets the maximum tON. In the zero-current detection (ZCD) loop and primary closed loop, tON is adjusted according to ZCD and the set signals. The adjusting process is limited between TON_MIN (1Ch) and TON_MAX (1Dh). **Command** TON_MAX **Format** Unsigned binary **Bit** 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 **Access** R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W **Function** X X X X X X TON_MAX **Bits Bit Name Description** 15:10 RESERVED Not defined. Read-only. 9:0 TON_MAX 5ns/LSB. ~~—~~ MPC1100A-54-0000 Rev. 1.0 MonolithicPower.com **31** 3/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **TON_NORMAL (1Eh)** 

The TON_NORMAL command sets the normal working tON. It is also the final tON for soft start, and the tON for open-loop operation. **Command** TON_NORMAL **Format** Unsigned binary **Bit** 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 **Access** R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W **Function** X X X X X X TON_NORMAL **Bits Bit Name Description** 15:10 RESERVED Not defined. Read-only. 9:0 TON_NORMAL The real tON is (TON_NORMAL + 1) x 5ns. **TON_MIN_LIM (1Fh)** The TON_MIN_LIM command sets the starting tON for PWM during soft start. ~~a~~ **Command** TON_MIN_LIM **Format** Unsigned binary **Bit** 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 **Access** R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W **Function** TON_MIN_LIM **Bits Bit Name Description** 15:14 RESERVED Reserved. R/W bits are available, but do not change the device. The beginning of the soft-start pulse width. Only used during soft start. The pulse 13:8 TON_MIN_LIM width can be calculated with the following equation: Pulse width = (TON_MIN_LIM + 1) x 5ns 7:0 RESERVED Reserved. R/W bits are available, but do not change the device. 

## **MFR_REF_SR_CTRL (21h)** 

The MFR_REF_SR_CTRL command configures the VOUT DAC input (also called VID or VREF) and controls its slew rate. VREF works as a reference in primary closed-loop operation, and is the base reference for OVP_VID and UVP_VID. **Command** MFR_REF_SR_CTRL **Format** Unsigned binary **Bit** 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 **Access** R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W **Function** VID_COUNTING_STEP MFR_REF_SET **Bits Bit Name Description** ~~=SEES SEEEEEEE~~ Selects the clock counting rate. 15 CLK_COUNTING_SEL 1’b1: 1µs 1’b0: 0.1µs Every VID_COUNTING_STEP x (1µs or 0.1µs) time period, VID increases or 14:8 VID_COUNTING_STEP decreases by 6.25mV. 7:0 MFR_REF_SET VID (V) = MFR_REF_SET x 6.25mV. 6.25mv/LSB. ~~——~~ MPC1100A-54-0000 Rev. 1.0 MonolithicPower.com **32** 3/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **VOUT_TRIM (22h)** 

The VOUT_TRIM command sets the value to compensate the system error between VREF and VOSEN. The error used for the DC loop is (21h, bits[7:0] x 4 + VOUT_TRIM - VOUT_SENSE). VOUT_SENSE is the 10-bit ADC sampling result of VOSEN. 

|**Command**|||VOUT_TRIM||||
|---|---|---|---|---|---|---|
|**Format**|||Unsigned binary||||
|**Bit**|7<br>6||5<br>4<br>3|2<br>1|0||
|**Access**|R<br>R||R<br>R<br>R/W|R/W<br>R/W|R/W||
|**Function**|X<br>X||X<br>X|VOUT_TRIM|||
|**Bits**<br>**Bit Name**<br>**Description**<br>7:4<br>RESERVED<br>Not defined. Read-only.<br>3:0<br>VOUT_TRIM<br>1.5625mV/LSB.<br>~~—~~|||||||
|**TRANSFORMER_RATIO (25h)**|||||||
|The TRANSFORMER_RATIO command records the transformer ratio of the specific application.|||||||
|**Command**|||TRANSFORMER_RATIO||||
|**Format**<br>Unsigned binary<br>**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>**Bits**<br>**Bit Name**<br>**Description**<br>~~=---__~~<br>~~=== —=~~|||||||
|15:4|RESERVED||Reserved. R/W bits are available, but do not change the device.||||
|3:0|TRANSFORMER_RATIO||Records the transformer ratio.||||



Table 5 lists the values for 25h, bits[3:0], as well as their respective transformer ratios. 

**Table 5: Transformer Ratios** 

|**25h, Bits[3:0]**<br>~~ee~~|0|1|2|3|4|5|6|7|8|9|10|11|12|13|14|15|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Transformer**<br>**Ratio**<br>~~ee~~|-|1|1/2 1/3|1/2 1/3|1/2 1/3<br>1/4 1/5|1/4 1/5|1/6 1/7|1/6 1/7|1/8 1/9|1/8 1/9|1/10|1/11|1/12|1/13|1/14|1/15|



## **WEIGHT_ZCD (29h)** 

The WEIGHT_ZCD command defines the positive and negative weights used when adjusting the frequency set by zero-current detection (ZCD) functionality. Assume tON changes from INITIAL_TON (ns) to FINAL_TON (ns), and the dead time remains the same (DEAD_TIME (ns)). The adjusting time can be calculated with Equation (2): 

**==> picture [426 x 27] intentionally omitted <==**

Where all variables are unitless. The variables are defined below: 

- TON_INIT_D = INITIAL_TON (ns) / 5ns - 1 

- TON_FIN_D = FINAL_TON (ns) / 5ns - 1 

- n = TON_FIN_D - TON_INIT_D + 1 

- DT = DEAD_TIME (ns) / 5ns - 1 

- WEIGHT_ABS is the absolute value of WEIGHTN_ZCD or WEIGHTP_ZCD 

The time above does not include the 256 PWM periods during which tON stays within the tON hysteresis (0Bh, bits[10:8]) for tON latch (0Ch, bit[5]). 

**33** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** meso 

||||**_NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002_**|**_NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002_**|**_NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002_**|**_NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002_**|**_NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002_**|**_NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002_**|**_NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002_**|
|---|---|---|---|---|---|---|---|---|---|
|**Command**|||||WEIGHT_ZCD|||||
|**Format**|||||Direct|||||
|**Bit**|15|14|13|12|11<br>10<br>9<br>8<br>7|6<br>5|4<br>3<br>2|1|0|
|**Access**|R/W|R/W|R/W|R/W|R/W<br>R/W<br>R/W<br>R/W<br>R/W|R/W<br>R/W|R/W<br>R/W<br>R/W<br>R/W|R/W|R/W|
|**Function**|||WEIGHTN_ZCD||||WEIGHTP_ZCD|||
|||||||||||
|**Bits**|**Bit Name**||||**Description**|||||
|15:8|WEIGHTN_ZCD||||When zero-current detection (ZCD) occurs in a valid ZCD time (0Bh), tON<br>decreases by this value. Cannot be set to 0 or 0xFF.|||||
|7|RESERVED||||Reserved. R/W bits are available, but do not change the device.|||||
|6:0|WEIGHTP_ZCD||||When ZCD does not occur in a valid ZCD time (0Bh), tONincreases by this value.<br>Cannot be set to 0 or 0x01.|||||



## **SR_PWM_SETA_PRIDRV (2Ah)** 

The SR_PWM_SETA_PRIDRV command controls the SR_PWM setting and sets the simulated primary driver chip delay. For more information, see the CTRL_PWM section on page 19. 

|**Bits**|**Bit Name**|**Description**|
|---|---|---|
|15:12|PWM_NEG_FIXED|If SR_FIXED_DEC_EN = 1 and SR_FIXED_EXT_EN = 0, SR_PWM shuts off<br>before the PWMP pin of its own phase, and the change is (PWM_NEG_FIXED) x<br>5ns. If SR_FIXED_EXT_EN = 1 and SR_FIXED_DEC_EN = 0 or 1, SR_PWM<br>shuts off after PWMP, and the change is (PWM_NEG_FIXED + 1) x 5ns.|
|11:6|RESERVED|Reserved. R/W bits are available, but do not change the device.|
|5|RM_PWMDEC_<br>REDUND|Digital internal use.|
|4|PWM_EXT_DN_CFG|Digital internal use.|
|3:0|PRI_DRV_DLY_SIM|Delays the internal PWMPs from the output PWMPs. The time length simulates the<br>primary-drive chip delay. The delay time can be calculated with the following<br>equation:<br>Delay time = (bits[3:0] + 1) x 5ns|



## **SS_SRNEG_SET (2Bh)** 

The SS_SRNEG_SET command sets the time length that determines when the SR_PWM pin turns off (before or after PWMP during soft start). This register works with 5Ah and 5Bh. For more information, see the CTRL_PWM section on page 19. 

|**Command**<br>SS_SRNEG_SET<br>**Format**<br>Unsigned binary<br>**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>**Bits**<br>**Bit Name**<br>**Description**<br>15:12<br>SRNEG_SS_TONHH_<br>DEC<br>If tON≥ TON_LVL_SS_HH during soft start, then turn off SR_PWM before PWMP<br>by SRNEG_SS_TONHH_DEC x 5ns.<br>~~= SEE SESEEEEEEEES~~<br>~~————~~|
|---|
|MPC1100A-54-0000 Rev. 1.0<br>MonolithicPower.com<br>**34**|
|3/5/2021<br>MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.|
|© 2022 MPS. All Rights Reserved.|



**34** 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** meso 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

|11:8|SRNEG_SS_TONH_<br>DEC|If TON_LVL_SS_HH > tON≥ TON_LVL_SS_H, then turn off SR_PWM before<br>PWMP by SRNEG_SS_TONH_DEC x 5ns.|
|---|---|---|
|7:4|SRNEG_SS_TONL_<br>DLY|If TON_LVL_SS_L > tON≥ TON_LVL_SS_LL during soft start, then turn off<br>SR_PWM after PWMP by (SRNEG_SS_TONL_DLY + 1) x 5ns.|
|3:0|SRNEG_SS_TONLL_<br>DLY|If tON< TON_LVL_SS_LL, then turn off SR_PWM after PWMP by<br>(SR_NEG_SS_TONLL_DLY + 1) x 5ns.|



## **SR_PWM_SETB (2Ch)** 

The SR_PWM_SETB command controls the SR_PWM pins’ settings. For more information, see the CTRL_PWM section on page 19. 

|**Bits**<br>~~=~~|**Bit Name**<br>|**Description**<br>|
|---|---|---|
|15:13<br>~~=~~|RESERVED<br>|Reserved. R/W bits are available, but do not change the device<br>|
|12:8|SR_PWM_NEG_ADJ|SR_PWM shuts off before or after PWMP. The time length between SR_PWM’s<br>negative<br>edge<br>and<br>the<br>other<br>phase’s<br>PWMP<br>positive<br>edge<br>is<br>(SR_PWM_NEG_ADJ  + 1) x 5ns.|
|7:4|SR_PWM_POS_DECH|When SR_POS_DEC_EN = 1 under conditions other than light load, SR_PWM<br>turns on after PWMP by (SR_PWM_POS_DECH  + 1) x 5ns (the MP2981’s<br>SKIP_EN pin is low).|
|3:0|SR_PWM_POS_DECL|When SR_POS_DEC_EN = 1 under light-load conditions, SR_PWM turns on after<br>PWMP by (SR_PWM_POS_DECL  + 1) x 5ns (the the MP2981’s SKIP_EN pin is<br>high).|



## **MFR_SLOPE_SR (2Dh)** 

The MFR_SLOPE_SR command defines the capacitor’s slope charge number and current. 

|**Command**||||||||MFR_SLOPE_SR|MFR_SLOPE_SR|MFR_SLOPE_SR||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**||||||||Unsigned binary||||||||||
|**Bit**|15|14|13||12||12<br>11<br>10|9<br>8|7|6|5|4|3|2|1||0|
|**Access**|R|R|R||R||R<br>R|R<br>R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|**Function**|X|X|X||X||X<br>X|X||||SLOPE_CURRENT||||||
|||||||||||||||||||
|**Bits**|**Bit Name**||||||**Description**|||||||||||
|15:9|RESERVED||||||Not defined. Read-only.|||||||||||
|8:6|SLOPE_CAP_SET|||SLOPE_CAP_SET|||The parallel capacitor number is (8 - SLOPE_CAP_SET), and each capacitor is 3.7pF.||The parallel capacitor number is (8 - SLOPE_CAP_SET), and each capacitor is 3.7pF.|||||||The parallel capacitor number is (8 - SLOPE_CAP_SET), and each capacitor is 3.7pF.||
|5:0|SLOPE_CURRENT||||||Slope charge current. 250nA/LSB.|||||||||||



## **MFR_SLOPE_BLK (2Eh)** 

The MFR_SLOPE_BLK command defines the slope discharge time. 

|**Command**|MFR_SLOPE_BLK|MFR_SLOPE_BLK|MFR_SLOPE_BLK|MFR_SLOPE_BLK|MFR_SLOPE_BLK|MFR_SLOPE_BLK|MFR_SLOPE_BLK|MFR_SLOPE_BLK|MFR_SLOPE_BLK|MFR_SLOPE_BLK|MFR_SLOPE_BLK|MFR_SLOPE_BLK|MFR_SLOPE_BLK|MFR_SLOPE_BLK|MFR_SLOPE_BLK|MFR_SLOPE_BLK|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|Unsigned binary||||||||||||||||
|**Bit**|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|**Access**|R|R|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|**Function**|X|X|MFR_SLOPE_BLK||||||||||||||



**35** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com 

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

**==> picture [484 x 70] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||
|---|---|---|
|Bits|Bit Name|Description|
|15:14|RESERVED|Not defined. Read-only.|
|Discharge slope during dead time, excluding the first 5ns of dead time and the first|
|13:8|MFR_SLOPE_BLK|
|(MFR_SLOPE_BLK + 1) x 5ns of the PWMP pulses.|
|7:0|RESERVED|Reserved. R/W bits are available, but do not change the device.|

**----- End of picture text -----**<br>


## **PRISETBLK_WEIGHT_SS (2Fh)** 

The PRISETBLK_WEIGHT_SS command sets the blanking time of the primary set loop (primary closed loop). It is a time length at the beginning of the PWMP period. During this time, tON does not adjust based on the set loop. This command also configures how quickly tON increases during soft start. There are two tON increasing stages: fixed frequency and decreasing frequency. The first-stage cost time (tSS1) can be calculated with Equation (3): 

**==> picture [464 x 28] intentionally omitted <==**

Where DEAD_TIME = 1Bh, bits[6:0]; TON_MIN_LIM = 1Fh, bits[13:8]; and WEIGHT_SS = 2Fh, bits[6:0]. The second-stage cost time (tSS2) can be estimated with Equation (4): 

**==> picture [399 x 37] intentionally omitted <==**

Where u = TON_MIN = 1Ch, bits[9:0]; n = TON_NORMAL - TON_MIN; and TON_NORMAL = 1Eh, bits[9:0]. 

**==> picture [509 x 380] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Command|PRISETBLK_WEIGHT_SS|
|Format|Unsigned binary|
|Bit|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|Access|R|R|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|Function|X|X|BLK_TIME|
|Bits|Bit Name|Description|
|15:14|RESERVED|Not defined. Read-only.|
|Adjusts the blank PWMP tON (only primary closed loop) at the beginning of the|
|13:8|BLK_TIME|
|PWMP period. 5ns/LSB.|
|7|RESERVED|Reserved. R/W bits are available, but do not change the device.|
|6:0|WEIGHT_SS|Accumulation step during soft start.|
|WEIGHT_2_1 (30h)|
|The WEIGHT_2_1 command configures the value at which tON increases in the primary closed loop when|
|the set signal is received during the last two quarters of the remaining PWMP pulse, and BLK_TIME (2Fh)|
|is disabled.|
|Command|WEIGHT_2_1|
|Format|Unsigned binary|
|Bit|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|Access|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|Function|WEIGHT_2|WEIGHT_1|
|a|
|MPC1100A-54-0000 Rev. 1.0|MonolithicPower.com|36|
|3/5/2021|MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.|
|© 2022 MPS. All Rights Reserved.|

**----- End of picture text -----**<br>


|**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE**|**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE**|
|---|---|
|**_NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002_**||
|**Bits**<br>**Bit Name**<br>**Description**<br>15<br>RESERVED<br>Reserved. R/W bits are available, but do not change the device.<br>14:8<br>WEIGHT_2<br>Value at which the primary closed loop tONincreases when the set signal occurs<br>during the third quarter of the remaining PWMP period (PWMP with BLK_TIME is<br>disabled).<br>7<br>RESERVED<br>Reserved. R/W bits are available, but do not change the device.<br>6:0<br>WEIGHT_1<br>Value at which the primary closed loop tONincreases when the set signal is<br>received during the final quarter (not including the last 5ns) of the remaining PWMP<br>period (PWMP with BLK_TIME is disabled).<br>~~=———~~||
|**WEIGHT_4_3 (31h)**||
|The WEIGHT_4_3 command configures the value at which tONincreases in the primary closed loop when||
|the set signal is received on the first two quarters of the remaining PWMP pulse, not including BLK_TIME||
|(2Fh).||
|**Command**<br>WEIGHT_4_3<br>**Format**<br>Unsigned binary<br>**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>WEIGHT_4<br>WEIGHT_3<br>~~posses~~||
|**Bits**<br>**Bit Name**<br>**Description**<br>15<br>RESERVED<br>Reserved. R/W bits are available, but do not change the device.<br>14:8<br>WEIGHT_4<br>Value at which the primary closed loop tONincreases when the set signal is<br>received during the first quarter of the remaining PWMP period (PWMP with<br>BLK_TIME is disabled).<br>7<br>RESERVED<br>Reserved. R/W bits are available, but do not change the device.<br>6:0<br>WEIGHT_3<br>Value at which the primary closed loop tONincreases when the set signal is<br>received during the second quarter of the remaining PWMP period (PWMP with<br>BLK_TIME is disabled).<br>~~=———~~||
|**WEIGHT_OCSPK_L_N (32h)**||
|The WEIGHT_OCSPK_L_N command defines the tONdecreasing weight of the primary closed loop and||
|OCSPK_L.||
|**Command**<br>WEIGHT_OCSPK_L_N<br>**Format**<br>Direct<br>**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>WEIGHT_OCSPK_L<br>WEIGHT_N<br>~~[eases~~||
|**Bits**<br>**Bit Name**<br>**Description**<br>15:8<br>WEIGHT_OCSPK_L<br>Value at which tONdecreases when an over-current (OC) spike occurs on CS2<br>(OCSPK_L).<br>7:0<br>WEIGHT_N<br>Value at which the primary closed-loop tONdecreases when no set pulses appear<br>during the PWMP period while BLK_TIME is disabled.<br>~~————~~||



**37** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com 

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

## PIS 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **WEIGHT_OCSPK_INC (33h)** 

The WEIGHT_OCSPK_INC command sets the tON recovering (increasing) value after an over-current (OC) spike on CS1 or CS2 (OCSPK_H or OCSPK_L, respectively) goes low. 

|(OC) spike on CS1 or CS2 (OCSPK_H or OCSPK_L, respectively) goes low.||
|---|---|
|**Command**<br>WEIGHT_OCSPK_INC||
|**Format**<br>Unsigned binary||
|**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0||
|**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W||
|**Function**<br>WEIGHT_OCSPK_H_INC<br>WEIGHT_OCSPK_L_INC||
|**Bits**<br>**Bit Name**<br>**Description**<br>15<br>RESERVED<br>Reserved. R/W bits are available, but do not change the device.<br>14:8<br>WEIGHT_OCSPK_H_INC<br>Value at which tONrecovers (increases) after an over-current (OC) spike on CS1<br>(OCSPK_H) goes low.<br>7<br>RESERVED<br>Reserved. R/W bits are available, but do not change the device.<br>6:0<br>WEIGHT_OCSPK_L_INC<br>Value at which tONrecovers (increases) after an OC spike on CS2 (OCSPK_L)<br>goes low.<br>**MFR_VIN_DROP_SET (34h)**<br>The MFR_VIN_DROP_SET command configures the two functions when VINdrops.<br>**Command**<br>MFR_VIN_DROP_SET<br>**Format**<br>Unsigned binary<br>**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R<br>R<br>R<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>X<br>X<br>X<br>RESERVED<br>VINL_VOUTH_DELTA<br>VODROP_DAC<br>~~ce=~~||
|**Bits**<br>**Bit Name**<br>**Description**<br>15:13<br>RESERVED<br>Not defined. Read-only.<br>12:8<br>RESERVED<br>Reserved. R/W bits are available, but do not change the device.<br>7:4<br>VINL_VOUTH_DELTA<br>When the MP2981’s VINSEN drops below VOSEN - VINL_VOUTH_DELTA, the<br>SR_PWM pins start skipping.<br>3:0<br>VODROP_DAC<br>When the MP2981’s VINSEN exceeds VOSEN + VODROP_DAC, the SR_PWM<br>pins start generating.<br>**VIN_ON (35h)**<br>The VIN_ON command defines the levels for VINto start working. After VINramps up to VIN_ON, the<br>MP2981 starts to count START_DELAY (PROTECT_DELAY must finish counting before<br>START_DELAY) and then to generate PWMs. This level should be greater than VIN_OFF.<br>**Command**<br>VIN_ON<br>**Format**<br>Unsigned binary<br>**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>X<br>X<br>X<br>X<br>X<br>X<br>X<br>VIN_ON<br>**Bits**<br>**Bit Name**<br>**Description**<br>15:9<br>RESERVED<br>Not defined. Read-only.<br>8:0<br>VIN_ON<br>If READ_VIN ≤ VIN_ON and the power is off or READ_VIN < VIN_OFF at any<br>moment, VINunder-voltage lockout (UVLO) occurs. 0.25V/LSB.<br>~~ce—~~||
|MPC1100A-54-0000 Rev. 1.0<br>MonolithicPower.com<br>**38**||
|3/5/2021<br>MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.||
|© 2022 MPS. All Rights Reserved.||



**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **VIN_OFF (36h)** 

The VIN_OFF command defines the VIN level when the device is on and VIN starts working. This level should be below VIN_ON. 

|**Command**|||||VIN_OFF|||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|||||Unsigned binary|||||||
|**Bit**|15|14|13|12|11<br>10<br>9<br>8<br>7|6|5<br>4|3|2|1|0|
|**Access**<br>**Function**<br>~~— ~~|R<br>R<br>R<br>R<br>X<br>X<br>X<br>X<br> ~~EE~~||||R<br>R<br>R<br>R/W<br>R/W<br>X<br>X<br>X|R/W|R/W<br>R/W<br>R/W<br>VIN_OFF||R/W|R/W|R/W|
|**Bits**|**Bit Name**||||**Description**|||||||
|15:9|RESERVED||||Not defined. Read-only.|||||||
|8:0|VIN_OFF||||If READ_VIN ≤ VIN_ON and the power is off or READ_VIN < VIN_OFF at any<br>time, VINunder-voltage lockout (UVLO) occurs. 0.25V/LSB.||||If READ_VIN ≤ VIN_ON and the power is off or READ_VIN < VIN_OFF at any|||



## **IOUT_CAL_GAIN (38h)** 

The IOUT_CAL_GAIN command helps calculate READ_IOUT (8Ch), bits[9:0] (0.25A/LSB). IOUT_CAL_GAIN can be calculated with Equation (5): 

**==> picture [358 x 27] intentionally omitted <==**

Where kCS is the DrMOS current-sense (CS) gain (e.g. if the CS gain is 5µA/A, kCS = 5e - 6) (in A/A), and RCS is the resistor connected from CS1/CS2 to GND (in Ω). 

|**Command**|||||||IOUT_CAL_GAIN|||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|||||||Unsigned binary|||||||
|**Bit**|15|14|13|12|11<br>10||9<br>8<br>7<br>6|5|4|3|2|1|0|
|**Access**<br>R<br>R<br>R<br>R<br>R<br>R<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>X<br>X<br>X<br>X<br>X<br>X<br>IOUT_CAL_GAIN<br>~~ER~~||||||||||||||
|**Bits**|**Bit Name**||||**Description**||**tion**|||||||
|15:10|RESERVED||||Not defined. Read-only.|Not defined. Read-only.|Not defined. Read-only.|||||||
|9:0|IOUT_CAL_GAIN||||These bits help calculate READ_IOUT.|||||||||



## **IOUT_CAL_OFFSET (39h)** 

The IOUT_CAL_OFFSET command calculates READ_IOUT (8Ch), bits[9:0] (0.25A/LSB). It is in signed binary format and uses complements. READ_IOUT can be estimated with Equation (6): 

**==> picture [410 x 29] intentionally omitted <==**

Where IOUT_SENSE is the 10-bit ADC sampling result on the IMON pin. 

|**Command**|IOUT_CAL_OFFSET|IOUT_CAL_OFFSET|IOUT_CAL_OFFSET|IOUT_CAL_OFFSET|IOUT_CAL_OFFSET|IOUT_CAL_OFFSET|IOUT_CAL_OFFSET|IOUT_CAL_OFFSET|IOUT_CAL_OFFSET|IOUT_CAL_OFFSET|IOUT_CAL_OFFSET|IOUT_CAL_OFFSET|IOUT_CAL_OFFSET|IOUT_CAL_OFFSET|IOUT_CAL_OFFSET|IOUT_CAL_OFFSET|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|Signed binary<br>~~S~~||||||||||||||||
|**Bit**<br>~~BERR~~|15<br>~~BERR~~|14<br>~~BERR~~|13<br>~~BERR~~|12<br>~~BERR~~|11<br>~~BERR~~|10<br>~~BERR~~|9<br>~~BERR~~|8<br>~~BERR~~|7<br>~~BERR~~|6<br>~~BERR~~<br>~~S~~|5<br>~~BERR~~<br>~~S~~|4<br>~~BERR~~|3<br>~~BERR~~|2<br>~~BERR~~|1<br>~~BERR~~|0<br>~~BERR~~|
|**Access**<br>~~BERR~~|R<br>~~BERR~~|R<br>~~BERR~~|R<br>~~BERR~~|R<br>~~BERR~~|R<br>~~BERR~~|R<br>~~BERR~~|R<br>~~BERR~~|R<br>~~BERR~~|R<br>~~BERR~~|R<br>~~BERR~~<br>~~S~~|R/W<br>~~BERR~~<br>~~S~~|R/W<br>~~BERR~~|R/W<br>~~BERR~~|R/W<br>~~BERR~~|R/W<br>~~BERR~~|R/W<br>~~BERR~~|
|**Function**<br>~~BERR~~|X<br>~~BERR~~|X<br>~~BERR~~|X<br>~~BERR~~|X<br>~~BERR~~|X<br>~~BERR~~|X<br>~~BERR~~|X<br>~~BERR~~|X<br>~~BERR~~|X<br>~~BERR~~|X<br>~~BERR~~<br>~~S~~|IOUT_CAL_OFFSET<br>~~BERR~~<br>~~S~~||||||



**39** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com 

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

5:0 IOUT_CAL_OFFSET Calculates READ_IOUT. 

## **VIN_CAL_GAIN (3Ah)** 

The VIN_CAL_GAIN command calculates READ_VIN (88h), bits[9:0] (0.125V/LSB). VIN_CAL_GAIN can be calculated with Equation (7): 

**==> picture [335 x 13] intentionally omitted <==**

Where GAIN is the VIN divider ratio (e.g. if a 48V VIN results in 1V on the MP2981’s VINSEN pin with the resistor divider, then GAIN = 1/48). READ_VIN can be estimated with Equation (8): 

**==> picture [345 x 28] intentionally omitted <==**

Where VIN_SENSE is the 10-bit ADC sampling result on the VINSEN pin. 

**==> picture [499 x 121] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Command|VIN_CAL_GAIN|
|Format|Unsigned binary|
|Bit|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|Access|R|R|R|R|R|R|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|RRRESS|Function|X|X|X|X|X|X|VIN_CAL_GAIN|
|Bits|Bit Name|Description|
|15:10|RESERVED|Not defined. Read-only.|
|9:0|VIN_CAL_GAIN|Calculates READ_VIN.|

**----- End of picture text -----**<br>


## **VOUT_CAL_GAIN (3Bh)** 

The VOUT_CAL_GAIN command helps calculate READ_VOUT (8Bh), bits[8:0] (62.5mV/LSB). VOUT_CAL_GAIN can be calculated with Equation (9): 

**==> picture [335 x 14] intentionally omitted <==**

Where GAIN is the VOUT divider ratio (e.g. if 6V VOUT results in 1V on the VOSEN pin with the resistor divider, then GAIN = 1/6). 

READ_VOUT can then be calculated with Equation (10): 

**==> picture [361 x 29] intentionally omitted <==**

Where VOUT_SENSE is the 10-bit ADC sampling result of the VOSEN pin. 

**==> picture [504 x 122] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Command|VOUT_CAL_GAIN|
|Format|Unsigned binary|
|Bit|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|Access|R|R|R|R|R|R|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|RRR|Function|X|X|X|X|X|X|VOUT_CAL_GAIN|
|Bits|Bit Name|Description|
|15:10|RESERVED|Not defined. Read-only.|
|9:0|VOUT_CAL_GAIN|Helps calculated READ_VOUT.|

**----- End of picture text -----**<br>


**40** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **VIN_OV_FLT_LIM (40h)** 

The VIN_OV_FLT_LIM command sets the VIN over-voltage protection (OVP) fault limit. Compared to READ_VIN (88h), bits[9:1]. 

|**Command**|||||||VIN_OV_FLT_LIM|VIN_OV_FLT_LIM|VIN_OV_FLT_LIM|VIN_OV_FLT_LIM||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|||||||Unsigned binary|||||||||||
|**Bit**|15|14|13|12|11|10|9|8|7|6||5|4|3|2|1|0|
|**Access**<br>**Function**<br>~~— ~~|R<br>R<br>R<br>R<br>X<br>X<br>X<br>X<br> ~~EE~~||||R<br>X|R<br>X|R<br>X|R/W|R/W|R/W|R/W|R/W<br>R/W<br>R/W<br>VIN_OV_FLT_LIM|||R/W|R/W|R/W|
|**Bits**|**Bit Name**||||**Description**||**tion**|||||||||||
|15:9|RESERVED||||Not defined. Read-only.||Not defined. Read-only.|||||||||||
|8:0|VIN_OV_FLT_LIM||||VINover-voltage protection (OVP) limit. 0.25V/LSB.||||over-voltage protection (OVP) limit. 0.25V/LSB.|over-voltage protection (OVP) limit. 0.25V/LSB.|over-voltage protection (OVP) limit. 0.25V/LSB.|||||||



## **TEMP_GAIN_OFFSET (42h)** 

The TEMP_GAIN_OFFSET command calculates READ_TEMP (8Dh), bits[7:0] (1°C/LSB). MFR_TEMP_GAIN is an unsigned binary, while MFR_TEMP_OFFSET is a signed binary that uses complement format. READ_TEMP is calculated from the TEMP pin, and reflects the DrMOS temperature (T (°C)). Assuming the TEMP pin voltage (V) = _k_ x (T(°C) - _a_ ), READ_TEMP can be estimated with Equation (11): 

**==> picture [495 x 27] intentionally omitted <==**

Where TEMP_PIN_SENSE is the 10-bit ADC sampling result on the TEMP pin, and MFR_TEMP_GAIN and MFR_TEMP_OFFSET can be calculated with Equation (12) and Equation (13), respectively: 

**==> picture [321 x 26] intentionally omitted <==**

**==> picture [508 x 13] intentionally omitted <==**

|||MFR _TEMP_OFFSET|MFR _TEMP_OFFSET<br>a<br>=<br>(13)|(13)|(13)|
|---|---|---|---|---|---|
|**Command**|||TEMP_GAIN_OFFSET|||
|**Format**||Unsigned binary, signed binary||||
|**Bit**|15<br>14<br>13<br>12|11<br>10|9<br>8<br>7<br>6<br>5<br>4<br>3<br>2|1|0|
|**Access**|R/W<br>R/W<br>R/W<br>R/W|R/W<br>R/W|R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W|R/W|R/W|
|**Function**|MFR_TEMP_GAIN||MFR_TEMP_OFFSET|||
|**Bits**<br>**Bit Name**<br>**Description**<br>15:8<br>MFR_TEMP_GAIN<br>Proportional to the voltage vs. temperature (V-T) line gain. Unsigned binary.<br>7:0<br>MFR_TEMP_OFFSET<br>Proportional to the voltage value when T = 0°C. Signed binary.<br>~~———<<<<<<==—~~||||||
|**DIETEMP_GAIN_OFFSET (43h)**||||||



The DIETEMP_GAIN_OFFSET command calculates READ_DIE_TEMP (8Eh), bits[7:0] (1°C/LSB). MFR_DIE_TEMP_GAIN is an unsigned binary, while MFR_DIE_TEMP_OFFSET is a signed binary that uses complement format. The MP2981 senses its die temperature on the chip (not the TEMP pin). READ_DIE_TEMP can be calculated with the sensed ADC results using Equation (14): 

**==> picture [428 x 27] intentionally omitted <==**

**41** 

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MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

MFR_DIE_TEMP_GAIN and MFR_DIE_TEMP can be estimated with Equation (15) and Equation (16), respectively: 

**==> picture [345 x 27] intentionally omitted <==**

**==> picture [508 x 13] intentionally omitted <==**

Assume the voltage (V) input to ADC = _k_ x (T(°C) - _a_ ) during positive mode (06h, bit[11] = 0), which is the default mode. Positive mode is the default V-T wave mode. The second mode is negative mode (06h, bit[11] = 1). In negative mode, READ_DIE_TEMP can be calculated with Equation (17): 

**==> picture [468 x 27] intentionally omitted <==**

Where DIE_TEMP_SENSE is the 10-bit ADC sampling result of the chip’s sensed temperature, GAIN is short for MFR_DIE_TEMP_GAIN, and OFFSET is short for MFR_DIE_TEMP_OFFSET. 

In VBE mode, MFR_DIE_TEMP_GAIN and MFR_DIE_TEMP_OFFSET can be estimated with Equation (18) and Equation (19), respectively: 

**==> picture [361 x 27] intentionally omitted <==**

MFR _DIE_TEMP_OFFSET = a − 350 (19) 

||MFR _DIE_TEMP_OFFSET|MFR _DIE_TEMP_OFFSET<br>a<br>350<br>=<br>−<br>(19)|(19)|(19)|(19)|(19)|(19)|
|---|---|---|---|---|---|---|---|
|**Command**||DIETEMP_GAIN_OFFSET||||||
|**Format**||Unsigned binary, signed binary||||||
|**Bit**|15<br>14<br>13<br>12|11<br>10<br>9<br>8<br>7<br>6<br>5|4|3|2|1|0|
|**Access**|R/W<br>R/W<br>R/W<br>R/W|R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W|R/W|R/W|R/W|R/W|R/W|
|**Function**|MFR_DIE_TEMP_GAIN<br>MFR_DIE_TEMP_OFFSET|||||OFFSET||
|**Bits**<br>**Bit Name**<br>**Description**<br>15:8<br>DIE_TEMP_GAIN<br>Helps calculate READ_DIE_TEMP. Unsigned binary.<br>7:0<br>DIE_TEMP_OFFSET<br>Helps calculate READ_DIE_TEMP. Signed binary.<br>~~——<—<—<<<<=——~~||||||||



## **MFR_USER_PWD (44h)** 

The MFR_USER_PWD command is the configured user password for PMBus/I[2] C communication. Writeonly. All reads are 0. 

|**Command**||||MFR_USER_PWD||||
|---|---|---|---|---|---|---|---|
|**Format**||||Unsigned binary||||
|**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>W<br>W<br>W<br>W<br>W<br>W<br>W<br>W<br>W<br>W<br>W<br>W<br>W<br>W<br>W<br>W<br>**Function**<br>**Bits**<br>**Bit Name**<br>**Description**<br>~~feeee~~||||||||
|15:0|MFR_USER_PWD|MFR_USER_PWD|Configures the user password for PMBus/I2C communication.||C communication.|||



**42** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** meso _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **MFR_MTP_WP (45h)** 

The MFR_MTP_WP command provides MTP write protection. The MTP store command cannot be executed if this byte is not 8’h63. 

|**Command**|||||MFR_MTP_WP|MFR_MTP_WP||||
|---|---|---|---|---|---|---|---|---|---|
|**Format**|||||Direct|||||
|**Bit**|7||6|5|4|3|2|1|0|
|**Access**|R/W||R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|**Function**|||||MFR_MTP_WP|||||
|||||||||||
|**Bits**|**Bit Name**|||**Description**|**tion**|||||
|7:0|MFR_MTP_WP|||MTP write protection.||||||



## **SKIPDRMOS_SR_EARLI (46h)** 

The SKIPDRMOS_SR_EARLI command allows the device to skip the DrMOS function under light-load conditions. It is related to registers 1Ah and 49h. This register also sets the time length at which SR_PWM turns on before PWMP. 

|**Bits**|**Bit Name**|**Description**|
|---|---|---|
|15:13|RESERVED|Reserved. R/W bits are available, but do not change the device.|
|12:8|SR_POS_EARLIER|Determines how early SR_PWM turns on before PWMP. 5ns/LSB.|
|7|RESERVED|Reserved. R/W bits are available, but do not change the device.|
|6|SKIP_DRMOS_EN|Enables bypassing the DrMOS function (the SKIP_EN pin).<br>1’b1: Enabled<br>1’b0: Disabled|
|5:0|SKIPSR_DELAY_TIME|If SR_PWM is triggered by SKIP_PWM_EN or SKIP_DRMOS_EN before skipping<br>under light-load conditions, the current must stay low for this set time. One whole<br>ADC sample round/LSB, which is about 18µs/LSB if MFR_ADC_HOLD_TIME<br>(05H) is set to 2µs.|



## **MFR_IOUT_LEVEL (49h)** 

The MFR_IOUT_LEVEL command configures the TDC IOUT values to skip the DrMOS function under light-load conditions (the MP2981’s SKIP_EN pin, 46h, and 1Ah). If the load increases and READ_IOUT (8Ch) / 2 exceeds MFR_IOUT_LEVEL_H, then the SKIP_EN pin goes low and the DrMOS MOSFET starts working. 

The other way to exit skip mode is for the CS1 pin to exceed CMP_CS1_EXITSKIP (1Ah). The only condition to enter DrMOS skip mode is that READ_IOUT (8Ch) / 2 ≤ MFR_IOUT_LEVEL_L for a configured time (46h). 

|MPC1100A-54-0000 Rev. 1.0<br>MonolithicPower.com<br>**43**<br>**Command**<br>MFR_IOUT_LEVEL<br>**Format**<br>Unsigned binary<br>**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>MFR_IOUT_LEVEL_H<br>MFR_IOUT_LEVEL_L<br>~~== EEEEEE EEEEEES~~|MPC1100A-54-0000 Rev. 1.0<br>MonolithicPower.com<br>**43**<br>**Command**<br>MFR_IOUT_LEVEL<br>**Format**<br>Unsigned binary<br>**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>MFR_IOUT_LEVEL_H<br>MFR_IOUT_LEVEL_L<br>~~== EEEEEE EEEEEES~~|MPC1100A-54-0000 Rev. 1.0<br>MonolithicPower.com<br>**43**<br>**Command**<br>MFR_IOUT_LEVEL<br>**Format**<br>Unsigned binary<br>**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>MFR_IOUT_LEVEL_H<br>MFR_IOUT_LEVEL_L<br>~~== EEEEEE EEEEEES~~|MPC1100A-54-0000 Rev. 1.0<br>MonolithicPower.com<br>**43**<br>**Command**<br>MFR_IOUT_LEVEL<br>**Format**<br>Unsigned binary<br>**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>MFR_IOUT_LEVEL_H<br>MFR_IOUT_LEVEL_L<br>~~== EEEEEE EEEEEES~~|MPC1100A-54-0000 Rev. 1.0<br>MonolithicPower.com<br>**43**<br>**Command**<br>MFR_IOUT_LEVEL<br>**Format**<br>Unsigned binary<br>**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>MFR_IOUT_LEVEL_H<br>MFR_IOUT_LEVEL_L<br>~~== EEEEEE EEEEEES~~|
|---|---|---|---|---|
|3/5/2021||MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.|||
|||© 2022 MPS. All Rights Reserved.|||



**43** 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

|**Bits**|**Bit Name**|**Description**|
|---|---|---|
|15:8|MFR_IOUT_LEVEL_H|Sets the TDC IOUTvalue to exit DrMOS skip mode.|
|7:0|MFR_IOUT_LEVEL_L|Sets the TDC IOUTvalue to enter DrMOS skip mode.|



## **MFR_VCAL_I_MAX (4Bh)** 

The MFR_VCAL_I_MAX command defines the integration factor and the maximum DC loop limit. 

|**Command**||MFR_VCAL_I_MAX|||||
|---|---|---|---|---|---|---|
|**Format**||Unsigned binary|||||
|**Bit**<br>15<br>14<br>13|12|11<br>10<br>9<br>8<br>7<br>6|5<br>4<br>3|2|1|0|
|**Access**<br>R/W<br>R/W<br>R/W|R/W|R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W|R/W<br>R/W<br>R/W|R/W|R/W|R/W|
|**Function**|MFR_VCAL_I||MFR_VO_CMPS_MAX||||
||||||||
|**Bits**<br>**Bit Name**<br>**Description**<br>15:8<br>MFR_VCAL_I<br>The integration factor of the DC loop.<br>7:0<br>MFR_VO_CMPS_MAX<br>The maximum limit of the value input into the VO_COMP DAC.<br>~~————~~|||||||
|**DC_TRIM (4Ch)**|||||||



The DC_TRIM command sets the initial value of the VO_COMP DAC. The initial VO_COMP is DC_TRIM x 8. When the DC loop is enabled, VO_COMP = DC_TRIM x 8 - (DC loop result). If the DC loop is disabled, the data input to the VO_COMP DAC keeps the value before disabling. The DAC output is divided by 2, then added to VOSEN. The sum signal is one input of the primary closed-loop comparator. **Command** DC_TRIM **Format** Direct **Bit** 7 6 5 4 3 2 1 0 **Access** R/W R/W R/W R/W R/W R/W R/W R/W ~~===~~ **Function** DC_TRIM **Bits Bit Name Description** 7:5 RESERVED Reserved. R/W bits are available, but do not change the device. 4:0 DC_TRIM DC_TRIM x 8 is the initial value input into the VO_COMP DAC. ~~———~~ 

## **MPS_CODE (50h)** 

The MPS_CODE command is written with a code that represents MPS. 

|**Command**|MPS_CODE|MPS_CODE|MPS_CODE|MPS_CODE|MPS_CODE|MPS_CODE|MPS_CODE|MPS_CODE|MPS_CODE|MPS_CODE|MPS_CODE|MPS_CODE|MPS_CODE|MPS_CODE|MPS_CODE|MPS_CODE|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**<br>~~=~~|Direct<br>~~EEEEE EEEEEEEE~~||||||||||||||||
|**Bit**<br>~~=~~|15<br>~~EEE~~|14<br>~~EEE~~|13<br>~~EEE~~|12<br>~~EEE~~|11<br>|10<br>~~EE~~|9<br>~~EE EEE~~|8<br>~~EEE~~|7<br>~~EEE~~|6<br>~~EEE~~|5<br>~~EEE~~|4<br>~~EEEEE~~|3<br>~~EEEEE~~|2<br>~~EEEEE~~|1<br>~~EEEEE~~|0<br>~~EEEEE~~|
|**Access**<br>~~=~~|R/W<br>~~EEE~~|R/W<br>~~EEE~~|R/W<br>~~EEE~~|R/W<br>~~EEE~~|R/W<br>|R/W<br>~~EE~~|R/W<br>~~EE EEE~~|R/W<br>~~EEE~~|R/W<br>~~EEE~~|R/W<br>~~EEE~~|R/W<br>~~EEE~~|R/W<br>~~EEEEE~~|R/W<br>~~EEEEE~~|R/W<br>~~EEEEE~~|R/W<br>~~EEEEE~~|R/W<br>~~EEEEE~~|
|**Function**<br>~~=~~|~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~||~~EE~~|~~EE EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|~~EEEEE~~|~~EEEEE~~|~~EEEEE~~|~~EEEEE~~|~~EEEEE~~|



**44** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ **PRODUCT_CODE (51h)** 

The PRODUCT_CODE command is written with “2981” (hex code), and represents the MP2981 chip. 

|**Command**|||||PRODUCT_CODE|PRODUCT_CODE|PRODUCT_CODE|PRODUCT_CODE|||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**||||||Direct|||||||||
|**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>~~aes~~|||||||||||||||
||||||||||||||||
|**Bits**|**Bit Name**|||**Description**|**tion**||||||||||
|15:0|PRODUCT_CODE||PRODUCT_CODE|This code represents the MP2981 chip. It is 2981 (hex radix).|||||||This code represents the MP2981 chip. It is 2981 (hex radix).|This code represents the MP2981 chip. It is 2981 (hex radix).|||
|**CONFIG_ID (52h)**|**CONFIG_ID (52h)**||||||||||||||
|The CONFIG_ID command should be written with the specific application programming code.|||||||||||||||
|**Command**||||||CONFIG_ID|||||||||
|**Format**||||||Direct|||||||||
|**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>~~eee~~|||||||||||||||
||||||||||||||||
|**Bits**|**Bit Name**|||**Description**|**tion**||||||||||
|15:0|CONFIG_ID|CONFIG_ID||Write with a specific application programming code.|||||||||||



## **CONFIG_ID (52h)** 

The CONFIG_ID command should be written with the specific application programming code. 

## **CONFIG_REV (53h)** 

The CONFIG_REV command should be written with a version of the specific application programming code or complement programming code. 

|**Command**||||CONFIG_REV|CONFIG_REV|CONFIG_REV|CONFIG_REV|||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|||||Direct|||||||||||
|**Bit**|15<br>14|13|12|11<br>10<br>9|8|7|6|5||4|3||2|1|0|
|**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>~~tt~~||||||||||||||||
|||||||||||||||||
|**Bits**|**Bit Name**|||**Description**||||||||||||
|15:0|CONFIG_REV|||Write with a version of a specific application programming code or complement<br>programming code.|||||Write with a version of a specific application programming code or complement|||Write with a version of a specific application programming code or complement||Write with a version of a specific application programming code or complement||



## **CALVO_LOW_TON_SS_L (5Ah)** 

The CALVO_LOW_TON_SS_L command defines the upper limit of VOUT to enable the two stages (TONLL and TONL) of the SR_PWM pins turning off after the PWMPs during soft start. If VOUT > CALVOUT_LOW_LVL x 0.125V, TONLL and TONL are invalid. It also sets the two tON boundaries of these two stages. TON_LVL_SS_L must be greater than or equal to TON_LVL_SS_LL. 

|**Command**|CALVO_LOW_TON_SS_L|CALVO_LOW_TON_SS_L|CALVO_LOW_TON_SS_L|CALVO_LOW_TON_SS_L|CALVO_LOW_TON_SS_L|CALVO_LOW_TON_SS_L|CALVO_LOW_TON_SS_L|CALVO_LOW_TON_SS_L|CALVO_LOW_TON_SS_L|CALVO_LOW_TON_SS_L|CALVO_LOW_TON_SS_L|CALVO_LOW_TON_SS_L|CALVO_LOW_TON_SS_L|CALVO_LOW_TON_SS_L|CALVO_LOW_TON_SS_L|CALVO_LOW_TON_SS_L|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|Unsigned binary||||||||||||||||
|**Bit**|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|**Access**|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|**Function**|CALVOUT_LOW_LVL||||||TON_LVL_SS_L||||||TON_LVL_SS_LL||||



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MonolithicPower.com 

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

**==> picture [484 x 111] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||
|---|---|---|
|Bits|Bit Name|Description|
|If READ_VOUT / 2 (8Bh) > CALVOUT_LOW_LVL, then the TONLL and TONL|
|15:10|CALVOUT_LOW_LVL|stages during soft start can be disabled by setting CALVOUT_LOW_LMT_TONL|
|(in 0Fh) high. 125mv/LSB.|
|If TON_LVL_SS_L > tON ≥ TON_LVL_SS_LL during soft start, the SR_PWM pins|
|9:4|TON_LVL_SS_L|turn off after the PWMP pins by (SRNEG_SS_TONL_DLY + 1) x 5ns. Related to|
|2Bh. 5ns/LSB.|
|If tON < TON_LVL_SS_LL during soft start, the SR_PWM pins turn off after the|
|3:0|TON_LVL_SS_LL|
|PWMP pins by (SRNEG_SS_TONLL_DLY + 1) x 5ns. Related to 2Bh. 5ns/LSB.|

**----- End of picture text -----**<br>


## **TON_SS_H (5Bh)** 

The TON_SS_H command sets the two tON boundaries that turn the SR_PWM pins off before the PWMP pins during soft start. TON_LVL_SS_HH must be greater than or equal to TON_LVL_SS_H. 

**==> picture [509 x 236] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Command|TON_SS_H|
|Format|Unsigned binary|
|Bit|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|Access|R|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|ae|Function|X|TON_LVL_SS_H|TON_LVL_SS_HH|
|Bits|Bit Name|Description|
|15|RESERVED|Not defined. Read-only.|
|If TON_LVL_SS_HH > tON ≥ TON_LVL_SS_H during soft start, then the SR_PWM|
|14:8|TON_LVL_SS_H|pins turn off before the PWMP pins by (SRNEG_SS_TONH_DEC x 5ns). Related|
|to 2Bh. 5ns/LSB.|
|If tON ≥ TON_LVL_SS_HH during soft start, the SR_PWM pins turn off before the|
|7:0|TON_LVL_SS_HH|
|PWMP pins by (SRNEG_SS_TONHH_DEC x 5ns). Related to 2Bh. 5ns/LSB.|
|———|
|POWER_GOOD_ON (5Eh)|
|The POWER_GOOD_ON command defines a VID level close to the VID target (21h, bits[7:0]). This|
|means that VID ramping up is almost completed, and the PG on delay starts to use VID (instead of tON)|
|as the PG reference (06h, bit[2]).|

**----- End of picture text -----**<br>


**==> picture [495 x 132] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Command|POWER_GOOD_ON|
|Format|Direct|
|Bit|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|Access|R|R|R|R|R|R|R|R|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|Function|X|X|X|X|X|X|X|X|POWER_GOOD_ON|
|Bits|Bit Name|Description|
|15:8|RESERVED|Not defined. Read-only.|
|VID level that means VID ramping up is almost done. Must be set below or equal|
|7:0|POWER_GOOD_ON|
|to the VID target (21h, bits[7:0]). 6.25mV/LSB.|

**----- End of picture text -----**<br>


**46** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **POWER_GOOD_OFF (5Fh)** 

If VID is below or equal to this register and VID is selected as the PG reference (06h, bit[2]), then PG goes low. 

|goes low.|||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Command**|POWER_GOOD_OFF||||||||||||||||
|**Format**|Direct||||||||||||||||
|**Bit**|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|**Access**|R|R|R|R|R|R|R|R|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|**Function**|X|X|X|X|X|X|X|X|POWER_GOOD_OFF||||||||
|**Bits**|**Bit Name**||||**Description**||||||||||||
|15:8|RESERVED||||Not defined. Read-only.||||||||||||
|7:0|POWER_GOOD_OFF||||Determines the VID level of PG off if VID is selected as the PG reference. Must be<br>set below POWER_GOOD_ON (5Eh), bits[7:0]. 6.25mV/LSB.||||||||||||



## **PROTECT_DELAY (60h)** 

The PROTECT_DELAY sets the delay time after a shutdown occurs. After a shutdown protection that does not include an over-current (OC) spike (e.g. Phase OC, OCSPK_H, and OCSPK_L) occurs, the device starts counting PROTECT_DELAY. After this delay, the chip starts to count START_DELAY (63h), and then generates PWMs and ramps VID up again. 

|**PROTECT_DELAY (60h)**<br>The PROTECT_DELAY sets the delay time after a shutdown occurs. After a shutdown protection that<br>does not include an over-current (OC) spike (e.g. Phase OC, OCSPK_H, and OCSPK_L) occurs, the<br>device starts counting PROTECT_DELAY. After this delay, the chip starts to count START_DELAY (63h),<br>and then generates PWMs and ramps VID up again.|**PROTECT_DELAY (60h)**<br>The PROTECT_DELAY sets the delay time after a shutdown occurs. After a shutdown protection that<br>does not include an over-current (OC) spike (e.g. Phase OC, OCSPK_H, and OCSPK_L) occurs, the<br>device starts counting PROTECT_DELAY. After this delay, the chip starts to count START_DELAY (63h),<br>and then generates PWMs and ramps VID up again.|
|---|---|
|If the device has been configured to hiccup or retry mode, then the restart times are not completed||
|(VOUT_OVP_MAX, OVP_VID, UVP_VID, UVP_MIN, OCP_TDC, or OCP_SPIKE), and are reset by||
|VIN_UVLO.||
|**Bits**<br>**Bit Name**<br>**Description**<br>7<br>RESERVED<br>Not defined. Read-only.<br>6:0<br>PROTECT_DELAY<br>Sets the delay between a protection shutdown and when the device restarts.<br>100µs/LSB.<br>**Command**<br>PROTECT_DELAY<br>**Format**<br>Direct<br>**Bit**<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>X<br>PROTECT_DELAY<br>~~=a~~||
|**PWRGD_DELAY (62h)**||
|The PWRGD_DELAY command sets the delay period between the end of PG reference (tONincreasing||
|to TON_NORMAL (1Eh) or VID ramping up to POWER_GOOD_ON (5Eh)) ramping to when the PG pin|to TON_NORMAL (1Eh) or VID ramping up to POWER_GOOD_ON (5Eh)) ramping to when the PG pin|
|turns on.||



|turns on.||||||||
|---|---|---|---|---|---|---|---|
|**Command**||||PWRGD_DELAY||||
|**Format**||||Unsigned binary||||
|**Bit**|7|6|5|4<br>3|2|1|0|
|**Access**|R/W|R/W|R/W|R/W<br>R/W|R/W|R/W|R/W|
|**Function**||||PWRGD_DELAY||||
|||||||||
|**Bits**<br>**Bit Name**<br>**Description**<br>7<br>PWRGD_DELAY_SEL<br>1’b1: 20kHz<br>1’b0: 50kHz<br>~~a~~||||||||



**47** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com 

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

|6:0|PWRGD_DELAY|After VID reaches POWER_GOOD_ON (5Eh) or tONreaches TON_NORMAL<br>(1Eh), this delay time starts counting. After this delay finishes, PG goes high.<br>If 62h[7] = 1, the PWRGD_DELAY time = [6:0] x 50µs<br>If 62h[7] = 0, the PWRGD_DELAY time = [6:0] x 20µs|
|---|---|---|



## **START_DELAY (63h)** 

The START_DELAY command sets the time length for which the EN pin must stay high during start-up, after the MTP finishes restoring, and before VID starts slewing up and PWM switches. 

|**Command**||||||START_DELAY|||
|---|---|---|---|---|---|---|---|---|
|**Format**||||||Unsigned binary|||
|**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>**Bits**<br>**Bit Name**<br>**Description**<br>~~eet~~<br>~~ttt~~|||||||||
|||||Determines if the device requires a continuously high EN pin during start-up. The||Determines if the device requires a continuously high EN pin during start-up. The|||
|15:0|START_DELAY|||resolution is determined by MFR_ONOFFDLY_CLK_1L0S (06h, T). The time<br>length can be calculated with the following equation:||resolution is determined by MFR_ONOFFDLY_CLK_1L0S (06h, T). The time<br>length can be calculated with the following equation:|||
|||||Length = 256 x T x START_DELAY[15:8] + T x START_DELAY[7:0]||Length = 256 x T x START_DELAY[15:8] + T x START_DELAY[7:0]|||



## **OFF_DELAY (64h)** 

The OFF_DELAY command sets the delay time after the EN pin turns off or the PMBus/I[2] C sends an OFF command. This is during normal operation, and before shutting down VID, PG, and the PWM pins. 

|**Command**|||||OFF_DELAY|DELAY|||||
|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|||||Unsigned binary||||||
|**Bit**|15|14|13|12|11<br>10<br>9<br>8<br>7|6|5<br>4|3|2<br>1|0|
|**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>~~ttt~~|||||||||||
||||||||||||
|**Bits**|**Bit Name**||||**Description**||||||
||||||Determines the part’s delay before shutting down. The resolution is determined by||||||
|15:0|OFF_DELAY||||MFR_ONOFFDLY_CLK_1L0S (06h, T). The delay can be calculated with the<br>following equation:||||MFR_ONOFFDLY_CLK_1L0S (06h, T). The delay can be calculated with the||
||||||Delay = 256 x T x OFF_DELAY[15:8] + T x OFF_DELAY, bits[7:0]||||||



## **MFR_OTP_SET (65h)** 

The MFR_OTP_SET command controls the TEMP pin’s parameters if over-temperature protection (OTP) occurs. 

|**Command**<br>MFR_OTP_SET<br>**Format**<br>Unsigned binary<br>**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>MFR_OTP_HYS<br>MFR_OTP_LIMIT<br>**Bits**<br>**Bit Name**<br>**Description**<br>15<br>MFR_OTP_LATCH<br>1’b1: Latch-off mode<br>1’b0: Hiccup mode<br>14:8<br>MFR_OTP_HYS<br>The TEMP pin’s over-temperature (OT) hysteresis limit. When READ_TEMP (8Dh)<br>≤ (MFR_OTP_LIMIT - MFR_OTP_HYS), the OT comparator goes low. 1°C/LSB.<br>~~= EEE EEE~~<br>~~———~~|**Command**<br>MFR_OTP_SET<br>**Format**<br>Unsigned binary<br>**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>MFR_OTP_HYS<br>MFR_OTP_LIMIT<br>**Bits**<br>**Bit Name**<br>**Description**<br>15<br>MFR_OTP_LATCH<br>1’b1: Latch-off mode<br>1’b0: Hiccup mode<br>14:8<br>MFR_OTP_HYS<br>The TEMP pin’s over-temperature (OT) hysteresis limit. When READ_TEMP (8Dh)<br>≤ (MFR_OTP_LIMIT - MFR_OTP_HYS), the OT comparator goes low. 1°C/LSB.<br>~~= EEE EEE~~<br>~~———~~|
|---|---|
|MPC1100A-54-0000 Rev. 1.0<br>MonolithicPower.com<br>**48**||
|3/5/2021<br>MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.||
|© 2022 MPS. All Rights Reserved.||



**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

7:0 MFR_OTP_LIMIT TEMP pin over-temperature (OT) limit. 1°C/LSB. 

**MFR_DIE_OTP_SET (66h)** 

The MFR_DIE_OTP_SET command controls the die temperature’s parameters if over-temperature protection (OTP) occurs. **Command** MFR_DIE_OTP_SET **Format** Unsigned binary **Bit** 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 **Access** R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ~~=e~~ **Function** MFR_DIE_OTP_HYS MFR_DIE_OTP_LIMIT **Bits Bit Name Description** 1’b1: Latch-off mode 15 MFR_DIE_OTP_LATCH 1’b0: Hiccup mode Hysteresis of the die temperature’s over-temperature (OT) limit. When 14:8 MFR_DIE_OTP_HYS READ_TEMP (8Dh) ≤ (MFR_DIE_OTP_LIMIT - MFR_DIE_OTP_HYS), the OT comparator goes low. 1°C/LSB. 7:0 MFR_DIE_OTP_LIMIT Die temperature over-temperature (OT) limit. 1°C/LSB. ~~———~~ **PMBUS/I[2] C_ADDR_SET (67h)** The PMBUS/I2C_ADDR_SET command configures the 7-bit PMBus/I[2] C slave address (the chip’s PMBus/I[2] C address). **Command** PMBUS/I[2] C_ADDR_SET **Format** Unsigned binary **Bit** 7 6 5 4 3 2 1 0 **Access** R/W R/W R/W R/W R/W R/W R/W R/W **Function** ~~===~~ **Bits Bit Name Description** Final PMBus/1[2] C address = 67h, bits[6:4]. If bit[7] = 1, then the final PMBus/I[2] C 7:0 PMBUS/I[2] C_ADDR_SET address bits[3:0] comes from sampling the ADDRP pin. If bit[7] = 0, then the final PMBus/I[2] C address [6:0] = 67h, bits[6:0]. ~~————~~ **MFR_PROTECT_CFG (68h)** The MFR_PROTECT_CFG command controls certain device protections. **Command** MFR_PROTECT_CFG **Format** Unsigned binary **Bit** 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 **Access** R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W **Function Bits Bit Name Description** 1’b1: Only store VIN under-voltage lockout (UVLO) conditions that occur 15 UVLO_STARTUP_MTP_EN when power is being delivered to the MTP 1’b0: Store all VIN UVLO occurrences in the MTP 14:12 RESERVED Reserved. R/W bits are available, but do not change the device. Selects the trigger mode for DrMOS over-current protection (OCP). 11 DrMOS_OC_LATCH 1’b1: Latch-off mode 1’b0: Hiccup mode ~~=——~~ MPC1100A-54-0000 Rev. 1.0 MonolithicPower.com **49** 3/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

**==> picture [478 x 529] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||
|---|---|---|
|Enables DrMOS OCP.|
|10|DrMOS_OC_EN|1’b1: Enabled|
|1’b0: Disabled|
|Selects the VOUT_OVP_MAX protection mode.|
|9|VOUT_OVP_MAX_LATCH|1’b1: Latch-off mode|
|1’b0: Hiccup mode|
|Enables VOUT_OVP_MAX protection.|
|8|VOUT_OVP_MAX_EN|1’b1: Enabled|
|1’b0: Disabled|
|Enables DIE_TEMP protection.|
|7|DIE_TEMP_PRO_EN|
|1’b1: Disable DIE_TEMP protection|
|1’b0: Enable DIE_TEMP protection|
|1’b1: Disable over-temperature protection (OTP) from the TEMP pin (not|
|6|TEMP_PRO_EN|including DrMOS OC or DIE_TEMP)|
|1’b0: Enable OTP from the TEMP pin|
|Determines how the device responds when a VIN protection is enabled|
|(RST_VIN_PRO = 0).|
|5|MFR_VIN_OVP_LATCH|
|1’b1: Latch-off mode|
|1’b0: Hiccup mode|
|1’b1: Disable VIN protection, including VIN UVLO and VIN over-voltage|
|4|RST_VIN_PRO|protection (OVP)|
|1’b0: Enable VIN protection, including VIN UVLO and VIN OVP|
|1’b1: Only store VIN UVLO occurrences while power is delivered to|
|UVLO_STARTUP_STATUS|
|3|STATUS_WORD|
|_EN|
|1’b0: Store all VIN UVLO occurrences to STATUS_WORD.|
|Enables resetting STATUS_XX during a restart, after the EN pin is off, and|
|when operation is off.|
|2|RST_STATUS_EN|
|1’b1: Reset STATUS_XX during a restart|
|1’b0: Do not reset STATUS_XX during a restart|
|Select the clock counting the 4-clock delay after tON reaches TON_NORMAL,|
|before OVP_VID, UVP_VID, and UVP_MIN can be enabled.|
|1|SS_EXT_CLK_SEL|
|1’b1: 20kHz|
|1’b0: 50kHz|
|1’b1: Disable all protection features|
|1’b0: Enable all protection features|
|There are two protections that cannot be controlled by this bit:|
|0|DISABLE_ALL_PRO|
|•|PWM tON change during over-current (OC) spikes on the CS1 or CS2|
|pins (OCSPK_H and OCSPK_L, respectively)|
|•|Counting of OC spikes on CS1 (OCSPK_H) before the device shuts|
|down|

**----- End of picture text -----**<br>


## **OVP_UVP_VID_SET (69h)** 

**==> picture [510 x 143] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|The OVP_UVP_VID_SET command controls VOUT_OVP_VID and UVP_VID protection. Their levels are|
|defined in 19h.|
|Command|OVP_UVP_VID_SET|
|Format|Unsigned binary|
|Bit|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|Access|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|
|Function|OVP_VID_DELAYTIME|UVP_VID_DELAYTIME|
|=|MPC1100A-54-0000 Rev. 1.0|EEE|MonolithicPower.com|EEE|50|
|3/5/2021|MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.|
|© 2022 MPS. All Rights Reserved.|

**----- End of picture text -----**<br>


**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

|**Bits**|**Bit Name**|**Description**|
|---|---|---|
|15:14|OVP_VID_MODE|2’b00: No action<br>2’b01: Latch-off mode<br>2’b10: Hiccup mode<br>2’b11: Retry 3 times or 6 times based on OVP_VID_RETRY_TIMES|
|13|OVP_VID_RETRY_TIMES|1’b1: Retry 3 times<br>1’b1: Retry 6 times, when MFR_OVP_SET_MODE is 11b|
|12:8|OVP_VID_DELAYTIME|If VOUTstays high for a set time, VOUTover-voltage protection (OVP) is triggered.<br>200ns/LSB.|
|7:6|UVP_VID_MODE|2’b00: No action<br>2’b01: Latch-off mode<br>2’b10: Hiccup mode<br>2’b11: Retry 6 times|
|5:0|UVP_VID_DELAYTIME|If VOUTstays low for the set time, VOUTunder-voltage protection (UVP) is<br>triggered. 20µs/LSB.|



## **OCP_TDC_SET (6Ah)** 

The OCP_TDC_SET command controls TDC over-current protection (OCP). 

|**OCP_TDC_SET (6Ah)**<br>The OCP_TDC_SET command controls TDC over-current protection (OCP).|||
|---|---|---|
|**Command**<br>OCP_TDC_SET<br>**Format**<br>Unsigned binary<br>**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>OCP_TDC_DELAYTIME<br>OCP_TDC_LEVEL<br>~~jones!~~|||
|**Bits**<br>**Bit Name**<br>**Description**<br>15:14<br>OCP_TDC_MODE<br>2’b00: No action<br>2’b01: Latch-off mode<br>2’b10: Hiccup mode<br>2’b11: Retry 6 times<br>13:8<br>OCP_TDC_DELAYTIME<br>If the TDC current stays high for this set time, over-current protection (OCP) is<br>triggered. 100µs/LSB.<br>7:0<br>OCP_TDC_LEVEL<br>1A/LSB.<br>~~EEE~~|||
|**OCP_SPIKE_TIMES_SET (6Bh)**|||
|The OCP_SPIKE_TIMES_SET command controls the over-current (OC) spike time, which can shut down||The OCP_SPIKE_TIMES_SET command controls the over-current (OC) spike time, which can shut down|
|the chip.|||
|**Command**<br>OCP_SPIKE_TIMES_SET<br>**Format**<br>Unsigned binary<br>**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R<br>R<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>X<br>X<br>OCP_SPIKE_RANGE<br>OCP_SPIKE_TIMES<br>~~enc~~|||
|MPC1100A-54-0000 Rev. 1.0<br>MonolithicPower.com<br>**51**<br>**Bits**<br>**Bit Name**<br>**Description**<br>15:14<br>RESERVED<br>Not defined. Read-only.<br>13<br>DIS_OCP_SPIKE_SS<br>1’b1: Disable the OCP_SPIKE_TIMES protection during soft start<br>1’b0: Enable the OCP_SPIKE_TIMES protection during soft start<br>12:8<br>OCP_SPIKE_RANGE<br>The time length in which to count over-current (OC) spikes on CS1 (OCSPK_H),<br>and the time length before starting one OCSPK_H pulse. 1 PWMP period/LSB.<br>The set time can be calculated with the following equation:<br>Time length = (PWM1 tON+ PWM2 tON+ 2 dead time) x [12:8]<br>~~___——~~|||
|3/5/2021<br>MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.|||
|© 2022 MPS. All Rights Reserved.|||



**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

|**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE**|**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE**|
|---|---|
|**_NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002_**||
|2’b00: No action||
|7:6<br>OCP_SPIKE_MODE<br>2’b01: Latch-off mode<br>2’b10: Hiccup mode||
|2’b11: Retry 6 times||
|If the pulse time of OC spikes on CS1 (OCSPK_H) (both PWM1 and PWM2)||
|exceeds OCP_SPIKE_TIMES during OCP_SPIKE_RANGE, a protection is||
|5:0<br>OCP_SPIKE_TIMES<br>triggered. If the OCSPK_H (both PWM1 and PWM2) pulse time is below<br>OCP_SPIKE_TIMES during OCP_SPIKE_RANGE, then OCSPK_H pulses are||
|recounted from 0. The next OC pulse and the detection time window||
|(OCP_SPIKE_RANGE) also restart.||
|**OCP_SPIKE_LEVEL (6Ch)**||
|The OCP_SPIKE_LEVEL command sets the higher and lower OCP_SPIKE levels. Both levels are||
|compared with the CS1 and CS2 pins.||
|**Command**<br>OCP_SPIKE_LEVEL<br>**Format**<br>Unsigned binary<br>**Bit**<br>15<br>14<br>13<br>12<br>11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>HIGHER_SPIKE_LVL<br>LOWER_SPIKE_LVL<br>**Bits**<br>**Bit Name**<br>**Description**<br>15:8<br>HIGHER_SPIKE_LVL<br>Digital value of the higher OCP_SPIKE DAC. 2V range, 8-bit DAC. The DAC output<br>is HIGHER_SPIKE_LVL x 2V / 256.<br>7:0<br>LOWER_SPIKE_LVL<br>Digital value of the lower OCP_SPIKE DAC. 2V range, 8-bit DAC. The DAC output<br>is LOWER_SPIKE_LVL x 2V / 256.<br>~~SESE~~<br>~~EEEEEEEE~~<br>~~—————~~||
|**UVP_MIN_SET (6Dh)**||
|The UVP_MIN_SET command controls the VOUTUVP_MIN protection.||
|**Command**<br>UVP_MIN_SET<br>**Format**<br>Unsigned binary<br>**Bit**<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>**Function**<br>UVP_MIN_MODE<br>UVP_MIN_DELAY<br>~~===~~||
|**Bits**<br>**Bit Name**<br>**Description**<br>7:6<br>UVP_MIN_MODE<br>2’b00: No action<br>2’b01: Latch-off mode<br>2’b10: Hiccup mode<br>2’b11: Retry 6 times<br>5:0<br>UVP_MIN_DELAY<br>If VOUTstays low for this time length, the protection is triggered. 0.4µs/LSB.<br>**STATUS_WORD (79h)**<br>The STATUS_WORD command records general protections and the real-time on/off state. It is reset by<br>~~2~~||
|an EN or OPERATION restarting if the RST_STATUS_EN bit (68h), bit[2] is high, by sending the||
|CLEAR_FAULTS command (03h in Page 0, Page 1, or Page 3), or by cycling the power on VCC3V3.||



|**Command**|STATUS_WORD|STATUS_WORD|STATUS_WORD|STATUS_WORD|STATUS_WORD|STATUS_WORD|STATUS_WORD|STATUS_WORD|STATUS_WORD|STATUS_WORD|STATUS_WORD|STATUS_WORD|STATUS_WORD|STATUS_WORD|STATUS_WORD|STATUS_WORD|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|Unsigned binary||||||||||||||||
|**Bit**|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|**Access**|R|R|R|R|R|R|R|R|R|R|R|R|R|R|R|R|
|**Function**|||||||||||||||||



**52** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com 

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

**==> picture [481 x 600] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||
|---|---|---|
|Bits|Bit Name|Description|
|VOUT_OVP_MAX, OVP_VID, UVP_VID, and UVP_MIN fault indicator. If output|
|over-voltage protection (OVP) or under-voltage protection (UVP) occurs, this bit is|
|15|VOUT OVP or UVP|set and latched. The specific protection is determined by STATUS_VOUT (7Ah).|
|1’b0: No VOUT over-voltage (OV) or under-voltage (UV) fault has occurred|
|1’b1: A VOUT OV or UV fault has occurred|
|OCP_TDC or OCP_SPIKE_TIMES fault indicator. If either of these IOUT protections|
|occur, or an UV fault occurs at the beginning of OCP_TDC, this bit is set and|
|14|OCP|latched. The specific protection can be viewed by STATUS_IOUT (7Bh).|
|1’b0: No IOUT over-current (OC) fault has occurred|
|1’b1: An IOUT OC fault has occurred|
|VIN under-voltage lockout (UVLO) protection indicator. If READ_VIN ≤ VIN_ON|
|13|VIN_UVLO_FLAG|while the device is off, or READ_VIN < VIN_OFF at any time except during the|
|reset all protection stages, then this bit is pulled high.|
|VIN OVP fault indicator. If input OVP occurs, this bit is set and latched.|
|12|VIN_OVP|1’b0: No VIN OV fault has occurred|
|1’b1: A VIN OV fault has occurred|
|PG pin state indicator. PG is set high after PWRGD_DELAY. When any protection|
|11|PG|
|or fault occurs during normal operation (power out state), PG is pulled down.|
|10|RESERVED|Reserved. Reads are always 0.|
|DrMOS over-current protection (OCP) fault indicator. If the TEMP pin reaches|
|VCC3V3 (which means DrMOS OCP fault has occurred), this bit is set and latched.|
|9|DrMOS_OCP|Specific protections can be viewed by PROTECT_SIG_GRP (7Ch).|
|1’b0: No DrMOS OC fault has occurred|
|1’b1: A DrMOS OC fault has occurred|
|8:7|RESERVED|Reserved. Reads are always 0.|
|Chip working state indicator.|
|6|EN_SS|1’b1: The chip is not outputting PWMs or VREF, and the state is off|
|1’b0: The state is on, and PWMs are switching|
|VOUT OV positive edge fault indicator. If output OVP_MAX or VID positive edge|
|protection occurs, this bit is set and latched. Unlike STATUS_VOUT (7Ah),|this bit|
|OVP_MAX/OVP_VID_|can be cleared by a CLEAR_FAULTS (03h) command when the protection signal|
|5|POS|stays high.|
|1’b0: No VOUT OV positive edge fault has occurred|
|1’b1: A VOUT OV positive edge fault has occurred|
|IOUT OC positive-edge fault indicator. If output OC positive-edge protection occurs,|
|this bit is set and latched. Unlike STATUS_IOUT (7Bh),|this bit can be cleared by|
|4|OCP_TDC_POS|CLEAR_FAULTS (03h) when the protection signal stays high.|
|1’b0: No IOUT OC positive edge fault has occurred|
|1’b1: An IOUT OC positive edge fault has occurred|
|VOUT UV positive edge fault indicator. If output UV VID or MIN positive-edge|
|protection occurs, this bit is set and latched. Unlike STATUS_VOUT (7Ah),|this bit|
|UVP_VID or|can be cleared by a CLEAR_FAULTS (03h) command when the protection signal|
|3|UVP_MIN_POS|stays high.|
|1’b0: No VOUT UV positive edge fault has occurred|
|1’b1: VOUT UV positive edge fault has occurred|

**----- End of picture text -----**<br>


**53** 

MPC1100A-54-0000 Rev. 1.0 3/5/2021 

MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

|2|TEMP_OTP or DIE_OTP|Over-temperature protection (OTP) positive edge fault indicator. If OTP from the<br>TEMP pin sampling or the 2981 internal DIE_TEMP sensor fault occurs, this bit is<br>set and latched. Specific protections can be viewed by STATUS_TEMP (7Dh).<br>1’b0: No over-temperature (OT) fault has occurred<br>1’b1: An OT fault has occurred|
|---|---|---|
|1|STATUS_CML_<br>NONZERO|CML positive edge fault indicator. If a CML fault occurs, this bit is set and latched.<br>Specific protections can be viewed by STATUS_CML (7Ch).<br>1’b0: No CML fault has occurred<br>1’b1: CML fault has occurred|
|0|RESERVED|Reserved. Unused. Reads are always 0.|



## **STATUS_VOUT (7Ah)** 

The STATUS_VOUT command records the VOUT protection status. It can be reset by an EN or OPERATION restart if RST_STATUS_EN bit (68h), bit[2] is high, by sending a CLEAR_FAULTS command (03h in Page 0, Page 1, or Page 3), or by cycling the power on VCC3C3. 

|**Bits**|**Bit Name**|**Description**|
|---|---|---|
|7|OVP_MAX|VOUTOVP_MAX fault indicator. If VOUTexceeds VOUT_MAX, this bit is set and<br>latched.<br>1’b0: No VOUTOVP_MAX fault has occurred<br>1’b1: A VOUTOVP_MAX fault has occurred|
|6|OVP_VID|VOUTOVP_VID fault indicator. If VOUTexceeds OVP_VID for a set time, this bit is<br>set and latched.<br>1’b0: No VOUTOVP_VID fault has occurred<br>1’b1: A VOUTOVP_VID fault has occurred|
|5|UVP_VID|VOUTUVP_VID fault indicator. If VOUTdrops below UVP_VID for a set time, this bit<br>is set and latched.<br>1’b0: No VOUTOVP_MAX fault has occurred<br>1’b1: A VOUTOVP_MAX fault has occurred|
|4|UVP_MIN|VOUTOVP_MAX fault indicator. If VOUTdrops below UVP_MIN, this bit is set and<br>latched.<br>1’b0: No VOUTOVP_MAX fault has occurred<br>1’b1: A VOUTOVP_MAX fault has occurred|
|3:0|RESERVED|Reserved. Reads are always 0.|



## **STATUS_IOUT (7Bh)** 

The STATUS_IOUT command records the IOUT protection status. It can be reset by an EN or OPERATION restart if RST_STATUS_EN (68h), bit[2] is high, by sending a CLEAR_FAULTS command (03h on Page 0, Page 1, or Page 3), or by cycling the power on VCC3V3. 

|**Command**|STATUS_IOUT|STATUS_IOUT|STATUS_IOUT|STATUS_IOUT|STATUS_IOUT|STATUS_IOUT|STATUS_IOUT|STATUS_IOUT|
|---|---|---|---|---|---|---|---|---|
|**Format**|Unsigned binary||||||||
|**Bit**|7|6|5|4|3|2|1|0|
|**Access**|R|R|R|R|R|R|R|R|
|**Function**|||||||||



**54** 

MPC1100A-54-0000 Rev. 1.0 MonolithicPower.com 3/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

|**Bits**|**Bit Name**|**Description**|
|---|---|---|
|7|OCP_TDC|Normal IOUTover-current protection (OCP) TDC fault indicator. If the TDC remains<br>high for longer than the set time (6Ah), this bit is set and latched.<br>1’b0: No OCP TDC fault has occurred<br>1’b1: An OCP TDC fault has occurred|
|6|OCP_TDC_UV|Indicates an under-voltage (UV) fault caused by an IOUTOCP TDC fault. If the UV<br>comparator output is effective when TDC OCP occurs (after the delay), this bit is<br>set and latched.<br>1’b0: No OCP TDC/UV fault has occurred<br>1’b1: An OCP TDC/UV fault has occurred|
|5|OCP_SPIKE_TIMES|Indicates a UV fault caused by an IOUTOCP TDC fault. If the current-sense (CS)<br>peak exceeds the OC SPIKE H level and the counting pulse number exceeds the<br>set number (6Bh, bits[5:0]) in the configured range (6Bh, bits[12:8]), this bit is set<br>and latched.<br>1’b0: No OCP TDC/UV fault has occurred<br>1’b1: An OCP TDC/UV fault has occurred|
|4:0|RESERVED|Reserved. Reads are always 0.|



## **PROTECT_SIG_GRP (7Ch)** 

The PROTECT_SIG_GRP command records all protections that can result during shutdown. This register can be stored in the MTP. 

|**Bits**|**Bit Name**|**Description**|
|---|---|---|
|15:12|RESERVED|Reserved. Reads are always 0.|
|11|DRMOS_OCP|DrMOS over-current protection (OCP) indicator. If the TEMP pin voltage exceeds<br>1.8V, a DrMOS OCP fault occurs. DRMOS_OCP protection is triggered, and this<br>bit is set and latched. When an over-current (OC) condition occurs, DrMOS sets<br>its TEMP pin to VCC.<br>1’b0: No DrMOS OCP has occurred<br>1’b1: DrMOS OCP has occurred|
|10|RESERVED|Reserved. Reads are always 0.|
|9|OCP_TDC|IOUTTDC OCP indicator. If IOUTTDC OCP occurs and triggers TDC OCP protection,<br>this bit is set and latched.<br>1’b0: No TDC OCP has occurred<br>1’b1: TDC OCP has occurred|
|8|OCP_SPIKE_TIMES|OCP_SPIKE_TIMES protection indicator. If an OCP_SPIKE_TIMES fault occurs<br>and triggers a protection, this bit is set and latched.<br>1’b0: No OCP_SPIKE_TIMES protection has not occurred<br>1’b1: A OCP_SPIKE_TIMES protection has occurred|
|7|VIN_OVP|VINover-voltage protection (OVP) indicator. If VINOVP is triggered, this bit is set<br>and latched.<br>1’b0: No VINOVP has occurred<br>1’b1: VINOVP has occurred|



**55** 

MPC1100A-54-0000 Rev. 1.0 MonolithicPower.com 3/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

**==> picture [475 x 380] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||
|---|---|---|
|VIN under-voltage lockout (UVLO) indicator. If VIN UVLO occurs when delivering|
|power or if UVLO_STARTUP_MTP_EN (68h), bit[15] is enabled, then this bit is set|
|6|VIN_UVLO|and latched.|
|1’b0: No VIN UVLO fault has occurred|
|1’b1: A VIN UVLO fault has occurred|
|Over-temperature protection (OTP) from sampling the TEMP pin indicator. If this|
|fault occurs and triggers the protection, this bit is set and latched.|
|5|OTP|
|1’b0: No OTP has occurred|
|1’b1: OTP has occurred|
|Die OTP protection indicator. If the MP2981’s die temperature exceeds its over-|
|temperature (OT) limit and triggers the protection, this bit is set and latched.|
|4|DIE_OTP|
|1’b0: No die OTP has occurred|
|1’b1: Die OTP has occurred|
|VOUT OVP_MAX protection indicator. If a VOUT OVP max fault occurs and triggers|
|the protection, this bit is set and latched.|
|3|OVP_MAX|
|1’b0: No VOUT OVP_MAX protection has occurred|
|1’b1: A VOUT OV_MAX protection has occurred|
|VOUT OVP_VID protection indicator. If VOUT OVP VID fault occurs and triggers the|
|protection, this bit is set and latched.|
|2|OVP_VID|
|1’b0: No VOUT OVP_MAX protection has occurred|
|1’b1: A VOUT OV_MAX protection has occurred|
|VOUT UVP_VID protection indicator. If a VOUT UVP_VID fault occurs and triggers|
|the protection, this bit is set and latched.|
|1|UVP_VID|
|1’b0: No VOUT UVP_VID protection has occurred|
|1’b1: A VOUT UVP_VID protection has occurred|
|VOUT UVP_MIN protection indicator. If a VOUT UVP_MIN fault occurs and triggers|
|the protection, this bit is set and latched.|
|0|UVP_MIN|
|1’b0: No VOUT UVP_MIN protection has occurred|
|1’b1: A VOUT UVP_MIN protection has occurred|

**----- End of picture text -----**<br>


## **STATUS_TEMP (7Dh)** 

The STATUS_TEMP command records the protection statuses related to the TEMP pin. It can be reset by EN or OPERATION restarting if RST_STATUS_EN bit (68h, bit[2]) is high, by sending a CLEAR_FAULTS command (03h on Page 0, Page 1, or Page 3), or by cycling the power on VCC3V3. **Command** STATUS_TEMP **Format** Unsigned binary **Bit** 7 6 5 4 3 2 1 0 **Access** R R R R R R R R **Function** ~~===~~ **Bits Bit Name Description** ~~——~~ Over-temperature protection (OTP) fault indicator. If an over-temperature (OT) fault is sampled on the TEMP pin, this bit is set and latched. 7 OTP 1’b0: No OTP fault has occurred 1’b1: An OTP fault has occurred Die OTP fault indicator. If the MP2981’s die temperature exceeds its OT threshold, this bit is set and latched. 6 DIE_OTP 1’b0: No Die OTP has occurred 1’b1: Die OTP has occurred ~~—~~ MPC1100A-54-0000 Rev. 1.0 MonolithicPower.com **56** 3/5/2021 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** meso 

|5|DRMOS_OCP|DrMOS over-current protection (OCP) fault indicator. If the TEMP pin exceeds<br>1.8V and a DrMOS OCP fault occurs, this bit is set and latched. When an over-<br>current (OC) condition occurs, DrMOS sets its TEMP pin to VCC.<br>1’b0: No DrMOS OCP has occurred<br>1’b1: DrMOS OCP has occurred|
|---|---|---|
|4:0|RESERVED|Reserved. Reads are always 0.|



## **STATUS_CML (7Eh)** 

The STATUS_CML command records the status between PMBus/I[2] C and MTP communication. It can be reset by sending a CLEAR_FAULTS command (03h on Page 0, Page 1, or Page 3). 

|**Bits**<br>~~_—~~|**Bit Name**<br>~~_—~~|**Description**<br>~~_—~~|
|---|---|---|
|7<br>~~_—~~|CML_INVALID_CMD<br>~~_—~~|CML invalid command fault indicator. If the received PMBus/I2C command is not<br>defined, this bit is set and latched.<br>1’b0: No CML invalid command fault has occurred<br>1’b1: A CML invalid command fault has occurred<br>~~_—~~|
|6<br>~~_—~~|INTERNAL_DEBUG<br>~~_—~~|Used for debugging.<br>~~_—~~|
|5<br>~~_—~~|CML_PEC_FAULT<br>~~_—~~|CML peculiar fault indicator. If the received PMBus/I2C command does not match<br>the command sent by the master, this bit is set and latched.<br>1’b0: No CML peculiar fault has occurred<br>1’b1: A CML peculiar fault has occurred<br>~~_—~~|
|4<br>~~_—~~|LATCHED_WRFAIL<br>~~_—~~|WRFAIL is a flag signal from the MTP. It signifies that 1 byte written to the MTP<br>has failed. The MTP_WRFAIL output is reset at the start of writing the next byte.<br>This bit is the latched result of the MTP_WRFAIL signal. Reset this bit by sending<br>a CLEAR_FAULTS command (03h) and the beginning the next MTP write process<br>(not writing the next byte) after the current MTP storing process finishes.<br>~~_—~~|
|3<br>~~_—~~|CRC_FAULT_ENABLED<br>~~_—~~|If at least one of the three cyclic redundancy check (CRC) faults occurs, then the<br>corresponding CRC enable bit (07h, bits[15:13]) is set to 1:<br>1.<br>The CRC of the first two sections of the MTP (8’h00 to 8’hDD MTP addresses,<br>8’hDE and 8’hDF store the CRC calculation result). Valid in STORE_ALL<br>(15h),<br>RESTORE_ALL<br>(16h),<br>STORE_USER_ALL<br>(17h),<br>and<br>RESTORE_USER_ALL (18h). Its enable bit is 07h, bit[15].<br>2.<br>The CRC of the third section of MTP (8’hE0 to 8’hFB MTP addresses, 8’hFC,<br>and 8’hFD are the calculated CRC). Valid in STORE_ALL (15h),<br>RESTORE_ALL (16h), STORE_S3 (F5h), and RESTORE_S3 (F6h). Its<br>enable bit is 07h, bit[14].<br>3.<br>The total MTP CRC (8’h00 to 8’hFD MTP addresses, 8’hFE and 8’hFF store<br>the calculated CRC). Valid in STORE_ALL (15h) and RESTORE_ALL (16h).<br>This CRC cannot be enabled or configured by the user due to the commands<br>STORE_USER_ALL<br>(17h)<br>and<br>RESTORE_USER_ALL<br>(18h).<br>If<br>RESTORE_ALL (16h) is sent after STORE_USER_ALL (17h), this CRC error<br>is a false alarm. Its enable bit is 07h, bit[13].<br>~~_—~~|



MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

|2|STORE_OK|MTP storing state indicator. If MTP storing has finished without errors, this bit is<br>set. The stored MTP commands are: STORE_ALL (15h), STORE_USER_ALL<br>(17h), STORE_S3 (F5h), and DBG_MTP (F7h).<br>1’b0: MTP storing is not complete<br>1’b1: MTP storing has completed without errors|
|---|---|---|
|1|CML_OTHER_FAULT|Other CML fault indicator. If a false start or stop bit shows up during a normal I2C<br>command, this bit is set and latched.<br>1’b0: No other CML fault has occurred<br>1’b1: A different CML fault has occurred|
|0|MTP_SIGNATURE_<br>FAULT|MTP signature fault indicator. If the first 2 bytes of the MTP are not 16’h1234, this<br>bit is set and latched.<br>1’b0: No MTP_SIGNATURE_FAULT has occurred<br>1’b1: MTP_SIGNATURE_FAULT has occurred|



## **SYS_STATE_DBG (80h)** 

The SYS_STATE_DBG command records the state machine working in digital format. It is for debugging use. 

|**Bits**<br>~~—-—~~|**Bit Name**<br>~~—-—~~|**Description**<br>~~—-—~~|
|---|---|---|
|7<br>~~—-—~~|RESERVED<br>~~—-—~~|Reserved. Reads are always 0.<br>~~—-—~~|
|6:4<br>~~—-—~~|CHIP_PWR_ON_STATE<br>~~—-—~~|MTP restoration status after VCC3V3 powers on.<br>0x03: MTP copying is complete without errors. Normal operation resumes<br>0x04: There is an MTP signature or cyclic redundancy check (CRC) error<br>0x06: A protection occurred and was stored into the MTP during the last VCC3V3<br>on time<br>~~—-—~~|
|3<br>~~—-—~~|VR_OFF<br>~~—-—~~|CRC or MTP fault indicator. If CRC_FAULT_TOT_EN is high and an<br>MTP_SIGNATURE_FAULT (the first 2 bytes of MTP are not 1234h) or a CRC fault<br>occurs, this bit is set and latched.<br>~~—-—~~|
|2:0<br>~~—-—~~|SYS_CRTL_STATE<br>~~—-—~~|Indicates the state of the chip.<br>0x03: Waiting for VINto exit under-voltage lockout (UVLO) conditions<br>0x04: Normal operation<br>0x07: Protection<br>~~—-—~~|



|**Command**||||FINAL_I2C_ADDR|FINAL_I2C_ADDR|||||
|---|---|---|---|---|---|---|---|---|---|
|**Format**||||Unsigned binary||||||
|**Bit**|7|6|5|4|3||2|1|0|
|**Access**|R|R|R|R|R||R|R|R|
|**Function**|0|||FINAL_I2C_ADDR||||||
|||||||||||
|**Bits**|**Bit Name**||**Description**|**tion**||||||
|7|RESERVED|RESERVED|Not defined. Read-only.|Not defined. Read-only.||||||
|6:0|FINAL_I2C_ADDR||Final I2C address of this chip.|||||||



**58** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **REG_LAST_FAULT_MTP (82h)** 

The REG_LAST_FAULT_MTP command records protections. If PROTECT_FAULT_RECORD_EN (07h), bit[1] is set high when any one of the eleven protections in PROTECT_SIG_GRP (7Ch) occurs (except VIN UVLO), PROTECT_SIG_GRP (including the VIN_UVLO bit) are stored into the MTP addresses (8’hF4 and 8’hF5, FAULT_RECORD bytes). 

## **REG_LAST_FAULT_MTP (82h)** 

The REG_LAST_FAULT_MTP command records protections. If PROTECT_FAULT_RECORD_EN (07h), bit[1] is set high when any one of the 11 protections in PROTECT_SIG_GRP (7Ch) occurs (except VIN UVLO), then PROTECT_SIG_GRP (including the VIN_UVLO bit) is stored to the MTP addresses (8’hF4 and 8’hF5, FAULT_RECORD bytes). 

During the MTP restoration process, including the two FAULT_RECORD bytes (RESTORE_ALL (16h), RESTORE_S3 (F6h) and Page 2 byte read commands), if the first 2 bytes of the MTP are correct (16’h1234), then REG_LAST_FAULT_MTP (82h) is updated. 

|**Command**||||||REG_LAST_FAULT_MTP|
|---|---|---|---|---|---|---|
|**Format**||||||Unsigned binary|
|**Bit**|15|14|13|12||11<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0|
|**Access**|R|R|R|R||R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R|
|**Function**<br>~~EE~~|||||||
|**Bits**|**Bit Name**|||||**Description**|
|||||||Read result of the recorded PROTECT_SIG_GRP (7Ch) in the MTP. Can be|
|||||||reset by sending a CLR_LAST_FAULT_WMTP command (F1h) on Page 0, Page|
|15:0|REG_LAST_FAULT_MTP||||REG_LAST_FAULT_MTP|1, or Page 3 (not Page 2) when there is no writing or reading to the MTP. It is|
|||||||updated during MTP restoration, which includes the two FAULT_RECORD MTP|
|||||||addresses (8’hf4 and 8’hf5), if the first 2 bytes of the MTP are 16’h1234.|



## **READ_VIN (88h)** 

The READ_VIN command returns the calculated VIN from the ADC sample result on the MP2981’s VINSEN pin. 

|**Command**||||||||READ_VIN|READ_VIN||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|||||||Unsigned binary||||||||||
|**Bit**|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|**Access**<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>**Function**<br>0<br>0<br>0<br>0<br>0<br>0<br>READ_VIN<br>~~==...~~|||||||||||||||||
||||||||||||||||||
|**Bits**|**Bit Name**||||**Description**||**tion**||||||||||
|15:10|RESERVED||||Not defined. Read-only.||Not defined. Read-only.||||||||||
|9:0|READ_VIN||||0.125V/LSB.||||||||||||



## **READ_VOUT (8Bh)** 

The READ_VOUT command returns the calculated VOUT from the ADC sample result on the VOSEN pin. 

|**Command**|READ_VOUT|READ_VOUT|READ_VOUT|READ_VOUT|READ_VOUT|READ_VOUT|READ_VOUT|READ_VOUT|READ_VOUT|READ_VOUT|READ_VOUT|READ_VOUT|READ_VOUT|READ_VOUT|READ_VOUT|READ_VOUT|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|Unsigned binary||||||||||||||||
|**Bit**|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|**Access**|R|R|R|R|R|R|R|R|R|R|R|R|R|R|R|R|
|**Function**|0|0|0|0|0|0|0|READ_VOUT|||||||||



**59** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

|**Bits**<br>~~——<—<—<<<—=——~~|**Bit Name**<br>~~——<—<—<<<—=——~~|**Description**<br>~~——<—<—<<<—=——~~|
|---|---|---|
|15:9<br>~~——<—<—<<<—=——~~|RESERVED<br>~~——<—<—<<<—=——~~|Not defined. Read-only.<br>~~——<—<—<<<—=——~~|
|8:0<br>~~——<—<—<<<—=——~~|READ_VOUT<br>~~——<—<—<<<—=——~~|62.5mV/LSB.<br>~~——<—<—<<<—=——~~|



## **READ_IOUT (8Ch)** 

The READ_IOUT command returns the calculated IOUT from the ADC sample result on the IMON pin. 

|**Command**||||||||READ_IOUT|READ_IOUT|IOUT||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|||||||Unsigned binary|||||||||||
|**Bit**|15<br>14||13|12|11|10|9|8|7||6|5|4|3|2|1|0|
|**Access**<br>R<br>R<br>**Function**<br>0<br>0<br>~~——~~|||R<br>0|R<br>0|R<br>0|R<br>0|R|R|R||R|R<br>R<br>READ_IOUT||R<br>IOUT|R|R|R|
|**Bits**|**Bit Name**||||**Description**||**tion**|||||||||||
|15:10|RESERVED||||Not defined. Read-only.||Not defined. Read-only.|||||||||||
|9:0|READ_IOUT||||0.25A/LSB.|||||||||||||



## **READ_TEMP (8Dh)** 

|**READ_TEMP (8Dh)**|**READ_TEMP (8Dh)**|
|---|---|
|The READ_TEMP command returns the calculated DrMOS temperature from the ADC sample result on||
|the TEMP pin.||
|**Command**<br>READ_TEMP<br>**Format**<br>Unsigned binary<br>**Bit**<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>**Function**<br>~~===~~||
|**Bits**<br>**Bit Name**<br>**Description**<br>7:0<br>READ_TEMP<br>1°C/LSB.<br>~~a~~||
|**READ_DIE_TEMP (8Eh)**||
|The READ_DIE_TEMP command returns the calculated MP2981 die temperature from the ADC sample||
|result of the chip’s die temperature sense.||
|**Command**<br>READ_DIE_TEMP<br>**Format**<br>Unsigned binary<br>**Bit**<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>**Access**<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>**Function**<br>~~==~~||
|**Bits**<br>**Bit Name**<br>**Description**<br>7:0<br>READ_DIE_TEMP<br>1°C/LSB.<br>~~a~~||



**60** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **USER_KEY_INPUT (90h)** 

The USER_KEY_INPUT command sets the PMBus/I[2] C password. After 90h is written with the value of MFR_USER_PWD (44h) and start-up restoration completed, writing Page 0 registers is allowed. MFR_USER_PWD can be all zeros. This command is write-only. It is not stored in the MTP. After MTP start-up restoration, send the PMBus command to switch to Page 0, and then set register 90h to be equal to MFR_USER_PWD. 

|**Command**|USER_KEY_INPUT|USER_KEY_INPUT|USER_KEY_INPUT|USER_KEY_INPUT|USER_KEY_INPUT|USER_KEY_INPUT|USER_KEY_INPUT|USER_KEY_INPUT|USER_KEY_INPUT|USER_KEY_INPUT|USER_KEY_INPUT|USER_KEY_INPUT|USER_KEY_INPUT|USER_KEY_INPUT|USER_KEY_INPUT|USER_KEY_INPUT|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|Unsigned binary<br>~~EEE EEEEE~~||||||||||||||||
|**Bit**<br>~~PERE~~|15<br>~~PERE~~|14<br>~~PERE~~|13<br>~~PERE~~|12<br>~~PERE~~|11<br>~~PERE~~<br>~~EEE~~|10<br>~~PERE~~<br>~~EEE~~|9<br>~~PERE~~<br>~~EEE EEE~~|8<br>~~PERE~~<br>~~EEE~~|7<br>~~PERE~~<br>~~EEE~~|6<br>~~PERE~~<br>~~EEE~~|5<br>~~PERE~~<br>~~EEE~~|4<br>~~PERE~~<br>~~EE~~|3<br>~~PERE~~<br>~~EE~~|2<br>~~PERE~~<br>~~EE~~|1<br>~~PERE~~<br>~~EE~~|0<br>~~PERE~~<br>~~EE~~|
|**Access**<br>~~PERE~~|W<br>~~PERE~~|W<br>~~PERE~~|W<br>~~PERE~~|W<br>~~PERE~~|W<br>~~PERE~~<br>~~EEE~~|W<br>~~PERE~~<br>~~EEE~~|W<br>~~PERE~~<br>~~EEE EEE~~|W<br>~~PERE~~<br>~~EEE~~|W<br>~~PERE~~<br>~~EEE~~|W<br>~~PERE~~<br>~~EEE~~|W<br>~~PERE~~<br>~~EEE~~|W<br>~~PERE~~<br>~~EE~~|W<br>~~PERE~~<br>~~EE~~|W<br>~~PERE~~<br>~~EE~~|W<br>~~PERE~~<br>~~EE~~|W<br>~~PERE~~<br>~~EE~~|
|**Function**<br>~~PERE~~|~~PERE~~|~~PERE~~|~~PERE~~|~~PERE~~|~~PERE~~<br>~~EEE~~|~~PERE~~<br>~~EEE~~|~~PERE~~<br>~~EEE EEE~~|~~PERE~~<br>~~EEE~~|~~PERE~~<br>~~EEE~~|~~PERE~~<br>~~EEE~~|~~PERE~~<br>~~EEE~~|~~PERE~~<br>~~EE~~|~~PERE~~<br>~~EE~~|~~PERE~~<br>~~EE~~|~~PERE~~<br>~~EE~~|~~PERE~~<br>~~EE~~|



## **READ_POUT (96h)** 

The READ_POUT command returns the monitored output power (POUT) calculated from READ_VOUT and READ_IOUT. The PSYS pin value comes from this register. If PSYS_SEL_2W (06h), bit[13] is high, then READ_POUT, bits[10:1] are sent to the internal PSYS DAC. If PSYS_SEL_2W (06h), bit[13] is low, then READ_POUT, bits[9:0] (READ_POUT, bit[10] = 1 means 10’h3ff) are sent to the DAC. The DAC is 10 bits with a 1.28V range. The DAC output voltage is converted to a current flowing out of PSYS with a 1µA/10mV resolution. Calculate the PSYS current with Equation (20): 

**==> picture [370 x 25] intentionally omitted <==**

Where DAC_IN_10BIT is the 10-bit data inputted into the PSYS DAC. 

|**Command**|||||||READ_POUT|READ_POUT|READ_POUT|||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**||||||Unsigned binary||||||||||
|**Bit**|15<br>14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|**Access**|R<br>R|R|R|R|R|R|R|R|R|R|R|R|R|R|R|
|**Function**|0<br>0|0|0|0|||||READ_POUT|||||||
|||||||||||||||||
|**Bits**<br>**Bit Name**<br>**Description**<br>15:11<br>RESERVED<br>Not defined. Read-only.<br>10:0<br>READ_POUT<br>1W/LSB.<br>~~——<—<<<<=—~~||||||||||||||||
|**VIN_SENSE (99h)**||||||||||||||||



The VIN_SENSE command returns the MP2981’s VINSEN pin’s 10-bit ADC sample result. Used for debugging. 

|**Command**|||||VIN_SENSE|SENSE|||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|||||Unsigned binary||||||||
|**Bit**|15|14|13|12|11<br>10<br>9<br>8<br>7|6|5|4|3|2|1|0|
|**Access**<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>**Function**<br>0<br>0<br>0<br>0<br>0<br>0<br>VIN_SENSE<br>~~EEE~~|||||||||||||
||||||||||||||
|**Bits**|**Bit Name**||||**Description**||||||||
|15:10|RESERVED||||Not defined. Read-only.||||||||
|9:0|VIN_SENSE||||VINSEN (V) x 1024 / 1.6 (V).||||||||



**61** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **VOUT_SENSE (9Ah)** 

The VOUT_SENSE command returns the VOSEN pin’s 10-bit ADC sample result. Used for debugging. 

|**Command**|||||VOUT_SENSE|VOUT_SENSE|VOUT_SENSE|VOUT_SENSE|||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|||||Unsigned binary||||||||||
|**Bit**|15|14|13|12|11<br>10<br>9|8|7|6|5|4|3|2|1|0|
|**Access**<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>**Function**<br>0<br>0<br>0<br>0<br>0<br>0<br>VOUT_SENSE<br>~~FREE~~|||||||||||||||
||||||||||||||||
|**Bits**|**Bit Name**||||**Description**||||||||||
|15:10|RESERVED||||Not defined. Read-only.||||||||||
|9:0|VOUT_SENSE||||VOSEN (V) x 1024 / 1.6 (V).|VOSEN (V) x 1024 / 1.6 (V).|||||||||



## **IOUT_SENSE (9Bh)** 

The IOUT_SENSE command returns the IMON pin’s 10-bit ADC sample result. Used for debugging. 

|**Command**||||||IOUT_SENSE|IOUT_SENSE|IOUT_SENSE|||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**||||||Unsigned binary|||||||||
|**Bit**|15|14|13|12|11<br>10<br>9|8|7|6|5|4|3|2|1|0|
|**Access**<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>R<br>**Function**<br>0<br>0<br>0<br>0<br>0<br>0<br>IOUT_SENSE<br>~~EE~~|||||||||||||||
|**Bits**|**Bit Name**||||**Description**||||||||||
|15:10|RESERVED||RESERVED||Not defined. Read-only.||||||||||
|9:0|IOUT_SENSE||||VIMON (V) x 1024 / 1.6 (V).|VIMON (V) x 1024 / 1.6 (V).|||||||||



## **TEMP_SENSE (9Ch)** 

The TEMP_SENSE command returns the TEMP pin’s 10-bit ADC sample result. Used for debugging. 

|**Command**|||||||TEMP_SENSE|TEMP_SENSE|TEMP_SENSE|TEMP_SENSE||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|||||||Unsigned binary|||||||||||||
|**Bit**|15|14|13|12|11<br>10|9||8|7||6||5|4||3|2|1|0|
|**Access**<br>R<br>R<br>**Function**<br>0<br>0<br>~~———~~|||R<br>0|R<br>0|R<br>R<br>0<br>0|R||R|R||R|R<br>R<br>TEMP_SENSE||||R|R|R|R|
|**Bits**|**Bit Name**||||**Description**|||||||||||||||
|15:10|RESERVED||||Not defined. Read-only.|Not defined. Read-only.||||||||||||||
|9:0|TEMP_SENSE||||TEMP (V) x 1024 / 1.6 (V).||TEMP (V) x 1024 / 1.6 (V).|||||||||||||



## **DIE_TEMP_SENSE (9Dh)** 

The DIE_TEMP_SENSE command returns the 10-bit ADC sample result of the chip’s sensed die temperature. Used for debugging. 

|**Command**|DIE_TEMP_SENSE|DIE_TEMP_SENSE|DIE_TEMP_SENSE|DIE_TEMP_SENSE|DIE_TEMP_SENSE|DIE_TEMP_SENSE|DIE_TEMP_SENSE|DIE_TEMP_SENSE|DIE_TEMP_SENSE|DIE_TEMP_SENSE|DIE_TEMP_SENSE|DIE_TEMP_SENSE|DIE_TEMP_SENSE|DIE_TEMP_SENSE|DIE_TEMP_SENSE|DIE_TEMP_SENSE|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|Unsigned binary||||||||||||||||
|**Bit**<br>~~=.~~|15<br>~~=.~~|14<br>~~=.~~|13<br>~~=.~~|12<br>~~=.~~|11<br>~~=.~~|10<br>~~=.~~|9<br>~~=.~~|8<br>~~=.~~|7<br>~~=.~~|6<br>~~=.~~|5<br>~~=.~~|4<br>~~=.~~|3<br>~~=.~~|2<br>~~=.~~|1<br>~~=.~~|0<br>~~=.~~|
|**Access**<br>~~=.~~|R<br>~~=.~~|R<br>~~=.~~|R<br>~~=.~~|R<br>~~=.~~|R<br>~~=.~~|R<br>~~=.~~|R<br>~~=.~~|R<br>~~=.~~|R<br>~~=.~~|R<br>~~=.~~|R<br>~~=.~~|R<br>~~=.~~|R<br>~~=.~~|R<br>~~=.~~|R<br>~~=.~~|R<br>~~=.~~|
|**Function**<br>~~=.~~|0<br>~~=.~~|0<br>~~=.~~|0<br>~~=.~~|0<br>~~=.~~|0<br>~~=.~~|0<br>~~=.~~|DIE_TEMP_SENSE<br>~~=.~~||||||||||



**62** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

|9:0|DIE_TEMP_SENSE|The ADC result of the temperature from the internal temperature sensor, typically<br>by design. DIE_TEMP_SENSE can be calculated with the following equation:<br>DIE_TEMP_SENSE = INTERNAL_VOLTAGE x 1024 / 1.6<br>In default mode, the internal temp voltage (mV) = 9.83T (°C) - 109.8. In VBE mode,<br>voltage (mV) = -1.99T (°C) + 724.0.|
|---|---|---|



## **TON_PWMP (9Eh)** 

The TON_PWMP command monitors the output PWMP tON. Used for debugging. 

**Command** TON_PWMP **Format** Unsigned binary **Bit** 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 **Access** R R R R R R R R R R R R R R R R ~~=~~ **Function** 0 0 0 0 0 0 TON_PWMP **Bits Bit Name Description** 15:10 RESERVED Not defined. Read-only. 9:0 TON_PWMP tON for output PWMPs. 5ns/LSB. 

## **TON_SR_PWM (9Fh)** 

This register monitors the output SR_PWMs tON. Used for debugging. 

|**Command**|||||TON_SR_PWM|TON_SR_PWM||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Format**|||||Unsigned binary|||||||||||
|**Bits**<br>**Bit**<br>**Access**<br>**Function**<br>~~Se~~|**Bit Name**<br>15<br>14<br>R<br>R<br>0<br>0||13<br>R<br>0|12<br>R<br>0|**Description**<br>11<br>10<br>9<br>8<br>7<br>R<br>R<br>R<br>R<br>R<br>0<br>0||6<br>R|5<br>4<br>R<br>R<br>TON_SR_PWM||||3<br>R|2<br>R|1<br>R|0<br>R|
|15:10|RESERVED||RESERVED||Not defined. Read-only.|||||||||||
|9:0|TON_SR_PWM||||tONfor output SR_PWMs. 5ns/LSB.||for output SR_PWMs. 5ns/LSB.|||||||||



## **CLR_LAST_FAULT_WMTP (F1h)** 

The CLR_LAST_FAULT_WMTP command writes the 2 FAULT_RECORD bytes of the MTP to 0000h, and clears the REG_LAST_FAULT_MTP (82h on Page 0) register. It can be sent by Page 0, Page 1, or Page 3 (not Page 2). 

This command is only valid when the MTP is not locked, which means that this command is not a write protection. When FAULT_SINGLE_EN (07h), bit[3] = 0, sending F1h writes all 32 bytes of the third section of the MTP (8’hE0 to 8’hFF MTP addresses), but the 2 FAULT_RECORD bytes are written to 0000h. When FAULT_SINGLE_EN = 1, sending F1h only writes the 2 bytes of the MTP, and not all 32 bytes. 

## **READ_LAST_FAULT_TRIG (F2h)** 

Do not send this command. 

## **CLEAR_STORE_FAULTS (F3h)** 

The CLEAR_STORE_FAULTS command clears faults. If start-up is paused by MTP_LAST_FAULT (the data of the 2 FAULT_RECORD bytes in the MTP are not all zeros, or are not found during the start-up restoration), sending F3h forces the device to continue start-up. The REG_LAST_FAULT_MTP register (82h) and the 2 bytes in the MTP are not reset by this command. It can be sent by Page 0, Page 1, or Page 3 (not Page 2). 

**63** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** MPS _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ **CLEAR_MTP_FAULTS (F4h)** 

The CLEAR_MTP_FAULTS command clears MTP faults. If start-up is paused due to an MTP_SIGNATURE fault (the first 2 bytes of the MTP are not 1234h) or a CRC fault, sending the F4h command forces the device into the next state (checking REG_LAST_FAULT_MTP (82h)), and start-up continues. 

This command clears all cyclic redundancy check (CRC) errors, clears MTP_SIGN_FAULT, and resets the DBG_MTP_OK signal (the result to automatically read the MTP after the DBG_MTP command (F7h) is correct) to 1. It can be sent by Page 0, Page 1, or Page 3 (not Page 2). 

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© 2022 MPS. All Rights Reserved. 

**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** MPS _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **TYPICAL APPLICATION CIRCUIT** 

**==> picture [238 x 196] intentionally omitted <==**

**----- Start of picture text -----**<br>
3.3V<br>5V<br>b VCC33<br>VCC5V<br>PG<br>v PG<br>SDA<br>SDA<br>SCL MPC1100A-<br>SCL<br>GND GND 54-0000<br>EN<br>EN<br>VIN<br>VOUT<br>VIN VOUT<br>GND ADDR PSYS GND<br>**----- End of picture text -----**<br>


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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

_**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **PACKAGE INFORMATION** 

## **Surface-Mount (18mmx27mmx6mm)** 

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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** 

## _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ 

## **CARRIER INFORMATION** 

|ABCD<br>soos|ABCD<br>soos||1|ABCD|ABCD||1|ABCD|ABCD|1<br>ABCD|1<br>ABCD||1|Pin1|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**Feed Direction**|||**Feed Direction**|||||||
|**Part Number**|**Package**<br>**Description**||**Quantity/**<br>**Reel**||**Quantity/**||**Quantity/**<br>**Tube**|||**Reel**<br>**Diameter**||**Carrier**<br>**Tape**<br>**Width**||**Carrier**<br>**Tape Pitch**|
|MPC1100A-54-0000–Z|Surface-mount<br>(18mmx27mmx6mm)||300||||N/A|||13in||44mm||24mm|



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**MPC1100A-54-0000 – NON-ISOLATED, FIXED RATIO, 300W, DIGITAL DC/DC MODULE** MPS _**NOT RECOMMENDED FOR NEW DESIGNS, REFER TO MPC1100C-54-0002**_ **REVISION HISTORY** 

|**Revision #**<br>~~op~~|**Revision Date**<br>~~op~~|**Description**<br>~~op~~|**Pages Updated**<br>~~op~~|
|---|---|---|---|
|1.0<br>~~op~~|3/5/2021<br>~~op~~|Initial Release<br>~~op~~|-<br>~~op~~|



**Notice:** The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. 

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## Links

- [View this product on Novapart](https://novapart.co/products/MPC1100A-54-0000-Z/non-isolated-pol-dc-converter-300-w-4-v-6-60-a)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/en-ES/monolithic-power-systems-mps/mpc1100a-54-0000-z/dc-dc-converter-4v-6v-60a/dp/3818909)
---

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