MMBFJ175

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February 2014<br>**----- End of picture text -----**<br>


# **J175 / J176 / MMBFJ175 / MMBFJ176 / MMBFJ177 P-Channel Switch** 

## **Description** 

This device is designed for low-level analog switching sample-and-hold circuits and chopper-stabilized amplifiers. Sourced from process 88. 

DP **TO-92 DGS** 

**Figure 1. J175 / J176 Device Package** 

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G<br>S<br>SOT-23 Ng D<br>Mark: 6W / 6X / 6Y<br>Note: Source & drain are interchangeable.<br>**----- End of picture text -----**<br>


**Figure 2. MMBFJ175 / 176 / 177 Device Package** 

## **Ordering Information** 

|**Part Number**|**Marking**|**Package**|**Packing Method**|
|---|---|---|---|
|J175_D26Z|J175|TO-92 3L|Tape and Reel|
|J176_D74Z|J176|TO-92 3L|Ammo|
|MMBFJ175|6W|SOT-23 3L|Tape and Reel|
|MMBFJ176|6X|SOT-23 3L|Tape and Reel|
|MMBFJ177|6Y|SOT-23 3L|Tape and Reel|



©1997 Fairchild Semiconductor Corporation J175 / J176 / MMBFJ175 / MMBFJ176 / MMBFJ177 Rev. 1.1.1 

www.fairchildsemi.com 

1 

## **Absolute Maximum Ratings**[(1),(2)] 

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Values are at TA = 25°C unless otherwise noted. 

**Symbol Parameter Value Unit** VDG Drain-Gate Voltage -30 V VGS Gate-Source Voltage 30 V IGF Forward Gate Current 50 mA TJ, TSTG Operating and Storage Junction Temperature Range -55 to + 150 ° C ~~<=:~~ 

## **Notes:** 

1. These ratings are based on a maximum junction temperature of 150 ° C. 

2. These are steady-state limits. Fairchild Semiconductor should be consulted on applications involving pulsed or low-duty cycle operations. 

**Thermal Characteristics**[(3)] Values are at TA = 25°C unless otherwise noted. **Max. Symbol Parameter MMBFJ175 / Unit J175 / J176 MMBFJ176 / MMBFJ177** Total Device Dissipation 350 225 mW PD Derate Above 25 ° C 2.8 1.8 mW/ ° C R θ JC Thermal Resistance, Junction to Case 125 ° C/W R θ JA Thermal Resistance, Junction to Ambient 357 556 ° C/W ~~———~~ **Note:** 3. PCB size: FR-4 76 x 114 x 1.57 mm[3] (3.0 inch x 4.5 inch x 0.062 inch) with minimum land pattern size. 

© 1997 Fairchild Semiconductor Corporation J175 / J176 / MMBFJ175 / MMBFJ176 / MMBFJ177 Rev. 1.1.1 

www.fairchildsemi.com 

2 

## **Electrical Characteristics** 

Values are at TA = 25°C unless otherwise noted. 

|Values are at TA = 25°C unless otherwise noted.|Values are at TA = 25°C unless otherwise noted.A = 25°C unless otherwise noted.= 25°C unless otherwise noted.||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Conditions**||**Min.**|**Max.**|**Unit**|
|**Off Characteristics**|||||||
|V(BR)GSS|Gate-Source Breakdown Voltage|IG= 1.0μA, VDS= 0||30||V|
|IGSS|Gate Reverse Current|VGS= 20 V, VDS= 0|||1.0|nA|
|VGS(off)|Gate-Source Cut-Off Voltage|VDS= -15 V, ID= -10 nA|**J175 /**<br>**MMBFJ175**|3.0|6.0|V|
||||**J176 /**<br>**MMBFJ176**|1.0|4.0||
||||**MMBFJ177**|0.8|2.5||
|**On Characteristics**|||||||
|IDSS|Zero-Gate Voltage Drain Current(4)|VDS= -15 V, IGS= 0|**J175 /**<br>**MMBFJ175**|-7.0|-60.0|mA|
||||**J176 /**<br>**MMBFJ176**|-2.0|-25.0||
||||**MMBFJ177**|-1.5|-20.0||
|rDS(on)|Drain-Source On Resistance|VDS ≤ 0.1 V, VGS= 0|**J175 /**<br>**MMBFJ175**||125|Ω|
||||**J176 /**<br>**MMBFJ176**||250||
||||**MMBFJ177**||300||



## **Note:** 

4. Pulse test: pulse width ≤ 300 μ s, duty cycle ≤ 2.0%. 

© 1997 Fairchild Semiconductor Corporation J175 / J176 / MMBFJ175 / MMBFJ176 / MMBFJ177 Rev. 1.1.1 

www.fairchildsemi.com 

3 

## **Typical Performance Characteristics** 

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-20 100 1,000<br>T    A = 25°C<br>TYP   V            = 4.5 VGS(off) EF 50 SSS =a 500<br>-16 0.5 V I DSS<br>-12 Te V      = 0 VGS 1.0 V pr r DS g fs<br>Ze pow ef<br>Aa 10 i seas 100<br>1.5 V<br>-8<br>a 7e—.e8nm 2.0 V 5 SS Seaee 50<br>I        DSS , g fs @ V     = 15VDS ,<br>-4 2.5 V 3.0 V 3.5 V V     = 0 PULSED r     @ -100 mV, V     = 0DS GS GS<br>Zee ee V           @ V      = - 15V,GS(off) DS<br>I     = - 1.0 D μ A<br>0 ) ae 1 pT I 10<br>0 -1 -2 -3 -4 -5 1 2 5 10<br>V    - DRAIN-SOURCE VOLTAGE (V)DS V             - GATE CUTOFF VOLTAGE (V)GS (OFF)<br>Figure 3. Common Drain-Source Figure 4. Parameter Interactions<br>-32 16<br>V      = - 15 VDS V      = - 15 VDS<br>V            = - 4.5 VGS(off) V            = - 4.5 V GS(off)- 55°C<br>-24 AL - 55°C PT 12 aN 25°C =<br>25°C 125°C<br>-16 SS 125°C V            = 2.5 VGS(off)- 55°C i 8 NSS V            = 2.5 VGS(off) - 55°C<br>25 ° C 25°C<br>125°C<br>125°C<br>-8 4<br>0 0<br>0 1 2 3 4 0 1 2 3 4<br>V    - GATE-SOURCE VOLTAGE (V)GS V    - GATE-SOURCE VOLTAGE (V)GS<br>Figure 5. Transfer Characteristics Figure 6. Transfer Characteristics<br>100 1000<br>50 V             @ 5.0V, 10 GS(off) μ A f = 1.0 kHz<br>-5.0V -5.0V<br>20 r     = DS 1  -   ________V r GSDS oe a 100 el -10V -20V -10V<br>10 — V GS(off) ———_———— V             = - 4.5VGS(off) —— -20V Tf ty<br>5 |} 4 10 ed<br>V             GS(off) = - 2.5V<br>2 pit+T [i een<br>1 0 0.2 0.4 0.6 0.8 1 _ 10.01 _ 0.1 oi _ 1 ooh _ 10<br>V    /V         - NORMALIZED GATE-SOURCE VOLTAGE (V)GS GS(off) I    - DRAIN CURRENT (mA)D<br>Figure 7. Normalized Drain Resistance vs.  Figure 8. Output Conductance vs. Drain Current<br>Bias Voltage<br>DS<br>D<br>I     - DRAIN CURRENT (mA)<br>fs (r      - DRAIN "ON" RESISTANCE<br>g     - TRANSCONDUCTANCE (mmhos) ) Ω<br>D D<br>I     - DRAIN CURRENT (mA) I     - DRAIN CURRENT (mA)<br>(  Ω )<br>μ<br>DS<br>r      - NORMALIZED RESISTANCE<br>os<br>g      - OUTPUT CONDUCTANCE (   mhos)<br>**----- End of picture text -----**<br>


© 1997 Fairchild Semiconductor Corporation J175 / J176 / MMBFJ175 / MMBFJ176 / MMBFJ177 Rev. 1.1.1 

www.fairchildsemi.com 

4 

## **Typical Performance Characteristics** (Continued) 

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100<br>10 es Se ee  ——— f  = 0.1 - 1.0 MHz<br>V             = 2.5V GS(off) =——SSe Senet Se<br>5 25°C<br>||neeCee ORT a<br>V             = 6.0V GS(off)<br>- 55°C<br>1 25°C 10 C      is (V      = -15VDS )<br>PP 224ii\| RAN 125°C SERRE<br>0.5 oon oon 5 SS + C      (V       rs DS = -15V) t-—<br>V      = -15VDG a [TF _<br>f = 1.0 kHz<br>Ico Co FARRER<br>0.1<br>_ 0.1 _ 1 _ 10 _ 100 1<br>0 4 8 12 16 20<br>I    - DRAIN CURRENT (mA)D<br>V      - GATE-SOURCE VOLTAGE (V)GS<br>rs<br>is<br>C     (C      ) - CAPACITANCE (pF)<br>fs<br>g     - TRANSCONDUCTANCE (mmhos)<br>**----- End of picture text -----**<br>


**Figure 9. Transconductance vs. Drain Current** 

**Figure 10. Capacitance vs. Voltage** 

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100<br>50 EE<br>SN x I     = - 0.2 mAD<br>a Z<br>Se Saini lil<br>10 I     = 5.0 mAD AT<br>SSP<br>5 | V       DG = - 15V DE |<br>BW = 6.0 Hz @ f = 10 Hz, 100 Hz<br>       = 0.2f @ f  ≥  1.0 kHz<br>1<br>0.01 0.1 1 10 100<br>f - FREQUENCY (kHz)<br>Figure 11. Noise Voltage vs. Frequency<br>350 Po ING<br>300 ee NS ee ee ee eee<br>TO-92<br>250<br>PEN fb<br>200 aee eeeeee ee<br>150 ee ee ee NG ee ee<br>SOT-23<br>100 |Pf ee IRSe Ne ee<br>oN ee<br>50<br>0<br>0 25 50 75 100 125 150<br>TEMPERATURE  (  C)o<br>D<br>√<br>n<br>e    - NOISE VOLTAGE (nV /   Hz)<br>P   - POWER DISSIPATION (mW)<br>**----- End of picture text -----**<br>


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1000<br>— V      = -100 mVDS<br>500 V             = 2.5V GS(off) V      = 0GS<br>V             = 4.5V GS(off) =<br>V             = 8.0V GS(off) ===<br>SESS<br>100 pp<br>50 a ee a<br>es<br>10<br>-50 0 50 100 150<br>T     - AMBIENT TEMPERATURE (  C)A o<br>)( Ω<br>DS<br>r     - DRAIN "ON" RESISTANCE<br>**----- End of picture text -----**<br>


**Figure 12. Channel Resistance vs. Temperature** 

**Figure 13. Power Dissipation vs. Ambient Temperature** 

© 1997 Fairchild Semiconductor Corporation J175 / J176 / MMBFJ175 / MMBFJ176 / MMBFJ177 Rev. 1.1.1 

www.fairchildsemi.com 

5 

## **Physical Dimensions** 

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TO-92<br>**----- End of picture text -----**<br>


## **Figure 14. 3-LEAD, TO92, MOLDED, 0.200 IN LINE SPACING LEAD FORM (J61Z OPTION) (ACTIVE)** 

_Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products._ 

_Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/ZA/ZA03F.pdf ._ 

_For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:_ 

_http://www.fairchildsemi.com/packing_dwg/PKG-ZA03F_BK.pdf_ . 

© 1997 Fairchild Semiconductor Corporation J175 / J176 / MMBFJ175 / MMBFJ176 / MMBFJ177 Rev. 1.1.1 

www.fairchildsemi.com 

6 

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Physical Dimensions  (Continued)<br>SOT-23<br>0.95<br>a 2.92±0.20 __f l | - -<br>3<br>1.40<br>1.30 [+0.20] 2.20<br>-0.15<br>1 2<br>(0.29) 0.60<br>0.37<br>0.95<br>0.20 A B 1.00<br>1.90 1.90<br>— _ beet<br>LAND PATTERN<br>RECOMMENDATION<br>1.20 MAX SEE DETAIL A \ eM<br>(0.93) 0.10<br>0.00<br>0.10 C<br>C<br>a 2.40±0.30<br>NOTES: UNLESS OTHERWISE SPECIFIED<br>GAGE PLANE<br>   A)  REFERENCE JEDEC REGISTRATION<br>TO-236, VARIATION AB, ISSUE H.<br>0.23    B)  ALL DIMENSIONS ARE IN MILLIMETERS.<br>0.08    C)  DIMENSIONS ARE INCLUSIVE OF BURRS,<br>0.25        MOLD FLASH AND TIE BAR EXTRUSIONS.<br>| aaa oF    D)  DIMENSIONING AND TOLERANCING PER       ASME Y14.5M - 1994.<br>0.20 MIN SEATING    E)  DRAWING FILE NAME: MA03DREV10<br>ai (0.55) s PLANE<br>DETAILA<br>SCALE: 2X<br>**----- End of picture text -----**<br>


## **Figure 15. 3-LEAD, SOT23, JEDEC TO-236, LOW PROFILE (ACTIVE)** 

_Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products._ 

_Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/MA/MA03D.pdf ._ 

_For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/packing_dwg/PKG-MA03D.pdf_ . 

© 1997 Fairchild Semiconductor Corporation J175 / J176 / MMBFJ175 / MMBFJ176 / MMBFJ177 Rev. 1.1.1 

www.fairchildsemi.com 

7 

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## **PRODUCT STATUS DEFINITIONS** 

## **Definition of Terms** 

|**Definition of Terms**|||
|---|---|---|
|**Datasheet Identification**|**Product Status**|**Definition**|
|Advance Information|Formative / In Design|Datasheet contains the design specifications for product development. Specifications may change<br>in anymanner without notice.|
|Preliminary|First Production|Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild<br>Semiconductor reserves the right to make changes at anytime without notice to improve design.|
|No Identification Needed|Full Production|Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make<br>changes at anytime without notice to improve the design.|
|Obsolete|Not In Production|Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor.<br>The datasheet is for reference information only.|



Rev. I66 

© Fairchild Semiconductor Corporation 

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