# Bipolar (BJT) Single Transistor, General Purpose, NPN, 80 V, 8 A, 20 W, TO-252 (DPAK)

![Product image](https://novapart.co/image/farnell:2845308/)

**URL**: https://novapart.co/products/MJD44H11RLG/bipolar-bjt-single-transistor-general-purpose-npn
**SKU**: MJD44H11RLG
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || Transistors || Bipolar Transistors || Single Bipolar Junction Transistors - BJT
**Price**: €0.3700
**Stock**: 200+
**Lead Time**: 2 days (indicative)

## Description

Transistor Polarity:NPN; Collector Emitter Voltage V(br)ceo:80V; Transition Frequency ft:85MHz; Power Dissipation Pd:20W; DC Collector Current:8A; DC Current Gain hFE:40hFE; Transistor C

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | Lead (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 20W |
| Transistor Mounting | Surface Mount |
| Transistor Polarity | NPN |
| Transition Frequency | 85MHz |
| Transistor Case Style | TO-252 (DPAK) |
| Dc Current Gain Hfe Min | 40hFE |
| Operating Temperature Max | 150°C |
| Continuous Collector Current | 8A |
| Collector Emitter Voltage Max | 80V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2845308/)

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## Complementary Power Transistors 

## **DPAK for Surface Mount Applications** 

Designed for general purpose power and switching such as output or driver stages in applications such as switching regulators, converters, and power amplifiers. 

## **Features** 

- Lead Formed for Surface Mount Application in Plastic Sleeves (No Suffix) 

- Straight Lead Version in Plastic Sleeves (“−1” Suffix) 

- Electrically Similar to Popular D44H/D45H Series 

- Low Collector Emitter Saturation Voltage 

- Fast Switching Speeds 

- Complementary Pairs Simplifies Designs 

- Epoxy Meets UL 94 V-0 @ 0.125 in 

- NJV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q101 Qualified and PPAP Capable 

- These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant 

**MAXIMUM RATINGS** (TA = 25 C, common for NPN and PNP, minus sign, “−”, for PNP omitted, unless otherwise noted) 

|“−”, for PNP omitted, unless otherwise noted)|“−”, for PNP omitted, unless otherwise noted)|||
|---|---|---|---|
|**Rating**|**Symbol**|**Max**|**Unit**|
|Collector-Emitter Voltage|VCEO|80|Vdc|
|Emitter-Base Voltage|VEB|5|Vdc|
|Collector Current − Continuous|IC|8|Adc|
|Collector Current − Peak|ICM|16|Adc|
|Total Power Dissipation<br>@ TC= 25°C<br>Derate above 25°C|PD|20<br>0.16|W<br>W/°C|
|Total Power Dissipation (Note 1)<br>@ TA= 25°C<br>Derate above 25°C|PD|1.75<br>0.014|W<br>W/°C|
|Operating and Storage Junction<br>Temperature Range|TJ, Tstg|−55 to +150|°C|
|ESD − Human Body Model|HBM|3B|V|
|ESD − Machine Model|MM|C|V|



## **SILICON POWER TRANSISTORS 8 AMPERES 80 VOLTS, 20 WATTS** 

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**----- Start of picture text -----**<br>
COMPLEMENTARY<br>COLLECTOR COLLECTOR<br>2, 4 2, 4<br>1 1<br>BASE BASE<br>3 3<br>EMITTER EMITTER<br>**----- End of picture text -----**<br>


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4<br>4 4<br>1<br>1 a [2] 3 a’ 1 2 3 2 3<br>DPAK DPAK IPAK<br>CASE 369C CASE 369G CASE 369D<br>STYLE 1 STYLE 1 STYLE 1<br>**----- End of picture text -----**<br>


## **MARKING DIAGRAMS** 

AYWW AYWW J4 J4 xH11G xH11G 

DPAK IPAK A = Assembly Location Y = Year WW = Work Week J4xH11 = Device Code x = 4 or 5 G = Pb-Free Package 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. 

NOTE: Some of the devices on this data sheet have been **DISCONTINUED** . Please refer to the table on page 7. 

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. These ratings are applicable when surface mounted on the minimum pad sizes recommended. 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2016 **December, 2025 − Rev. 22** 

**MJD44H11/D** 

**MJD44H11 (NPN), MJD45H11 (PNP)** 

## **THERMAL CHARACTERISTICS** 

|**THERMAL CHARACTERISTICS**||||
|---|---|---|---|
|**Characteristic**|**Symbol**|**Max**|**Unit**|
|Thermal Resistance, Junction-to-Case|R JC|6.25|°C/W|
|Thermal Resistance, Junction-to-Ambient (Note 2)|R JA|71.4|°C/W|
|Lead Temperature for Soldering|TL|260|°C|



2. These ratings are applicable when surface mounted on the minimum pad sizes recommended. 

## **ELECTRICAL CHARACTERISTICS** 

(TA = 25 C, common for NPN and PNP, minus sign, “−”, for PNP omitted, unless otherwise noted) 

||**Characteristic**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
||**OFF CHARACTERISTICS**||||||
||Collector-Emitter Sustaining Voltage|VCEO(sus)||||Vdc|
||(IC= 30 mA, IB= 0)||80|−|−||
||Collector Cutoff Current<br>(VCE= Rated VCEO, VBE= 0)<br>ICES<br>−<br>−<br>1.0<br>A<br>Emitter Cutoff Current<br>(VEB= 5 Vdc)<br>IEBO<br>−<br>−<br>1.0<br>A<br>~~oo~~||||||
||**ON CHARACTERISTICS**||||||
||Collector-Emitter Saturation Voltage|VCE(sat)||||Vdc|
||(IC= 8 Adc, IB= 0.4 Adc)||−|−|1||
||Base-Emitter Saturation Voltage|VBE(sat)||||Vdc|
||(IC= 8 Adc, IB= 0.8 Adc)||−|−|1.5||
||DC Current Gain|hFE||||−|
||(VCE= 1 Vdc, IC= 2 Adc)||60|−|−||
||(VCE= 1 Vdc, IC= 4 Adc)||40|−|−||
||**DYNAMIC CHARACTERISTICS**||||||
|Collector Capacitance<br>(VCB= 10 Vdc, ftest= 1 Mhz)<br>MJD44H11<br>MJD45H11<br>Ccb<br>−<br>−<br>45<br>130<br>−<br>−<br>pF<br>Gain Bandwidth Product<br>(IC= 0.5 Adc, VCE= 10 Vdc, f = 20 Mhz)<br>MJD44H11<br>MJD45H11<br>fT<br>−<br>−<br>85<br>90<br>−<br>−<br>MHz<br>~~rrr~~|||||||
||**SWITCHING TIMES**||||||
||Delay and Rise Times|td+ tr||||ns|
||(IC= 5 Adc, IB1= 0.5 Adc)||||||
||MJD44H11||−|300|−||
||MJD45H11||−|135|−||
||Storage Time|ts||||ns|
||(IC= 5 Adc, IB1= IB2= 0.5 Adc)||||||
||MJD44H11||−|500|−||
||MJD45H11||−|500|−||
||Fall Time|tf||||ns|
||(IC= 5 Adc, IB1= IB2= 0.5 Adc)||||||
||MJD44H11||−|140|−||
||MJD45H11||−|100|−||



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

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**MJD44H11 (NPN), MJD45H11 (PNP)** 

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**----- Start of picture text -----**<br>
1 PF SSSSSE<br>0.7<br>D = 0.5<br>0.5 Bo)a Saee ee ee ee e e eee eee<br>0.3<br>0.2<br>Er Et HHH<br>0.2 P| 0.1 ee ee | DDE R JC(t) = r(t) R JC a P(pk)<br>0.1 PToo  errrry R JC = 6.25 °C/ ; W MAX iamail<br>0.05 D CURVES APPLY FOR POWER<br>0.07 a ey= oss Se eeeciae iP Ly] LUsonst<br>0.05 eSae 0.02 =. eee PULSE TRAIN SHOWN READ TIME AT t 1 a t 1 t — 2 FHPoo<br>0.03 | 0.01 a T J(pk) - T C  = P (pk) 0 JC(t) DUTY CYCLE, D = t1/t2 tT TTT<br>0.02 SINGLE PULSE<br>a<br>0.01 a ell<br>0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 5 10 20 30 50 100 200 300 500 1 k<br>t, TIME (ms)<br>RESISTANCE (NORMALIZED)<br>r(t), EFFECTIVE TRANSIENT THERMAL<br>**----- End of picture text -----**<br>


**Figure 1. Thermal Response** 

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20 [J Coon<br>10 PEESSSR eS s toon s COU T<br>5<br>3 dc<br>2 pt Ns a ta ee<br>a ee<br>1 eS ee Se<br>See ll<br>0.5 THERMAL LIMIT @ TC = 25 °C SSS<br>0.3 ae WIRE BOND LIMIT e| | |NWI<br>0.1 ee eee<br>0.05<br>a a<br>Pe<br>0.02<br>1 3 5 7 10 20 30 50 70 100<br>VCE, COLLECTOR‐EMITTER VOLTAGE (VOLTS)<br>IC, COLLECTOR CURRENT (AMP)<br>**----- End of picture text -----**<br>


There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC − VCE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. 

The data of Figure 2 is based on TJ(pk) = 150 C; TC is variable depending on conditions. Second breakdown pulse limits are valid for duty cycles to 10% provided TJ(pk) ≤ 150 : C. TJ(pk) may be calculated from the data in Figure 1. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. 

**Figure 2. Maximum Forward Bias Safe Operating Area** 

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TA TC<br>2.5 25<br>2 20<br>TC<br>1.5 15 PSMA<br>P| RAL<br>1 10 pt TA<br>oP UAL<br>SURFACE<br>MOUNT<br>0.5 5<br>| | TS.<br>Po} | |SS<br>0 0 PF | tT tT | EE EE<br>25 50 75 100 125 150<br>T, TEMPERATURE (°C)<br>PD, POWER DISSIPATION (WATTS)<br>**----- End of picture text -----**<br>


**Figure 3. Power Derating** 

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**MJD44H11 (NPN), MJD45H11 (PNP)** 

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1000 1000<br>VCE = 1 V VCE = 1 V<br>150  ° C<br>p 150  ° C o Ht<br>EE 25  ° C EE e 25  ° C e<br>eer TAT P E ST<br>−55  ° C −55  ° C<br>100 S S 100 I o<br>F H NIL<br>ereeeees P oo<br>a (1 ||ee ees]| PENT |<br>10 Erte 10 ||<br>0.01 0.1  creat 1 10 0.01 EES 0.1 1 tt 10<br>IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A)<br>, DC CURRENT GAIN , DC CURRENT GAIN<br>FE FE<br>h h<br>**----- End of picture text -----**<br>


**Figure 4. MJD44H11 DC Current Gain** 

**Figure 5. MJD45H11 DC Current Gain** 

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1000 1000<br>VCE = 4 V VCE = 4 V<br>150  ° C<br>PT E Et<br>150  ° C<br>a | ee 25  ° C |<br>25  ° C<br>e −55  ° C d J −55  ° C<br>100 P ST 100 LL ET<br>10 poYtCeTTT ETT NYTT 10 p P| TTETToNT GT<br>0.01 0.1 Corn 1 crn 10 | 0.01 Tn 0.1 cen 1 ee 10<br>IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A)<br>Figure 6. MJD44H11 DC Current Gain Figure 7. MJD45H11 DC Current Gain<br>0.8 0.8<br>0.7 IC/IB = 20 0.7 IC/IB = 20<br>ee e ee 150  ° C p n nap −55  ° C<br>0.6 0.6<br>0.5 Sc ; 0.5 HT<br>PEE EE FL il<br>0.4 a | 0.4 a 25  ° C<br>0.3 pe 25  ° C 0.3 a e l<br>150  ° C<br>0.2 7 Ae 0.2 Rn A<br>All e T<br>0.1 EEN −55  ° C 0.1 7 Ao<br>0 2 0 Zel l<br>tT | e t | Till<br>0.01 0.1 1 10 0.01 0.1 1 10<br>IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A)<br>Figure 8. MJD44H11 Saturation Voltage Figure 9. MJD45H11 Saturation Voltage<br>V V<br>CE(sat) CE(sat)<br>, DC CURRENT GAIN , DC CURRENT GAIN<br>FE FE<br>h h<br>, COLL-EMIT SATURATION VOLTAGE (V) , COLL-EMIT SATURATION VOLTAGE (V)<br>CE(sat) CE(sat)<br>V V<br>**----- End of picture text -----**<br>


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**MJD44H11 (NPN), MJD45H11 (PNP)** 

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**----- Start of picture text -----**<br>
1.4 1.4<br>1.2 1.2<br>CTT nh §=onoo oom<br>1.0 1.0<br>CC IM ea ITa<br>−55  ° C −55  ° C<br>0.8 0.8<br>P 25  ° C erea T 25  ° C e<br>0.6 0.6<br>S t | cl<br>150  ° C 150  ° C<br>0.4 C MmeITI N | 0.4 U TE<br>0.2 IC/IB = 20 0.2 IC/IB = 20<br>0 a0 CCA alll 0 CErer TTTTll<br>0.01 0.1 1 10 0.01 0.1 1 10<br>IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A)<br>Figure 10. MJD44H11 Saturation Voltage Figure 11. MJD45H11 Saturation Voltage<br>V V<br>BE(sat) BE(sat)<br>2.0 2.0<br>1.8 TA = 25  ° C 1.8 TA = 25  ° C<br>1.6 HATAa aa aPEE te vc all| 1.6 HANPE TIEHEARTEA ElaLT fl|<br>1.41.2 PTIa aeEOEeeTATE TT 1.41.2 PLEPLETE EEETTTACTTATETT T<br>a ET T<br>1.0 1.0<br>0.8 PLETE ae NH 0.8 PLE EIT TIE NTE TTT<br>a ETE TIE ATE TT eT RR A N IC = 8 A<br>0.6 0.6<br>0.4 PLETE aE ll IC = 8 A 0.4 a ae | IC = 3 A<br>0.20 PL IC = 0.1 A SSS 0.5 A ETIHS 1 A TIE IC = 3 A TTT | 0.20 STpL IC = 0.1 A Till 0.5 A beterRR 1 A eee alll<br>[EIT<br>0.1 1 10 100 1000 10,000 0.1 1 10 100 1000 10,000<br>IB, BASE CURRENT (mA) IB, BASE CURRENT (mA)<br>Figure 12. MJD44H11 Collector Saturation Figure 13. MJD45H11 Collector Saturation<br>Region Region<br>1000 1000<br>Cob<br>ee Cob ee ell PPPS CET oT<br>100 S oe 100 L E<br>EHS n lHe EHth etEr e<br>ee el eeell<br>10 PCIE 10<br>0.1 1 PTT 10 C T 100 0.1 CCIE 1  PT 10 100<br>VR, REVERSE VOLTAGE (V) VR, REVERSE VOLTAGE (V)<br>VOLTAGE (V) VOLTAGE (V)<br>, BASE-EMIT SATURATION , BASE-EMIT SATURATION<br>BE(sat) BE(sat)<br>V V<br>, COLLECTOR-EMITTER VOLTAGE (V) , COLLECTOR-EMITTER VOLTAGE (V)<br>CE CE<br>V V<br>C, CAPACITANCE (pF) C, CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


**Figure 14. MJD44H11 Capacitance** 

**Figure 15. MJD45H11 Capacitance** 

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## **MJD44H11 (NPN), MJD45H11 (PNP)** 

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**----- Start of picture text -----**<br>
100 100<br>VCE = 2 V VCE = 2 V<br>rE<br>6Cen eeCCE con|| 4 zeee | |<br>10 10<br>0.01 0.1 1 10 0.01 0.1 1 10<br>IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A)<br>PRODUCT PRODUCT<br>, CURRENT-GAIN-BANDWIDTH , CURRENT-GAIN-BANDWIDTH<br>fTau fTau<br>**----- End of picture text -----**<br>


**Figure 16. MJD44H11 Current-Gain-Bandwidth Product** 

**Figure 17. MJD45H11 Current-Gain-Bandwidth Product** 

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## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**||||
|---|---|---|---|
|**Device**|**Package Type**|**Package**|**Shipping**†|
|MJD44H11G|DPAK<br>(Pb-Free)|369C|75 Units / Rail|
|NJVMJD44H11G|DPAK<br>(Pb-Free)|369C|75 Units / Rail|
|MJD44H11-1G|IPAK<br>(Pb-Free)|369D|75 Units / Rail|
|MJD44H11RLG|DPAK<br>(Pb-Free)|369C|1,800 / Tape & Reel|
|NJVMJD44H11RLG*|DPAK<br>(Pb-Free)|369C|1,800 / Tape & Reel|
|MJD44H11T4G|DPAK<br>(Pb-Free)|369C|2,500 / Tape & Reel|
|NJVMJD44H11T4G*|DPAK<br>(Pb-Free)|369C|2,500 / Tape & Reel|
|MJD45H11G|DPAK<br>(Pb-Free)|369C|75 Units / Rail|
|NJVMJD45H11G*|DPAK<br>(Pb-Free)|369C|75 Units / Rail|
|MJD45H11-1G|IPAK<br>(Pb-Free)|369D|75 Units / Rail|
|MJD45H11RLG|DPAK<br>(Pb-Free)|369C|1,800 / Tape & Reel|
|NJVMJD45H11RLG*|DPAK<br>(Pb-Free)|369C|1,800 / Tape & Reel|
|MJD45H11T4G|DPAK<br>(Pb-Free)|369C|2,500 / Tape & Reel|
|NJVMJD45H11T4G*<br>~~a~~|DPAK<br>(Pb-Free)<br>~~a~~|369C<br>~~a~~|2,500 / Tape & Reel<br>~~a~~|



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**MJD44H11 (NPN), MJD45H11 (PNP)** 

## **REVISION HISTORY** 

|**Revision**|**Description of Changes**|**Date**|
|---|---|---|
|22|Updated Package type in Ordering Information. MJD44H11T5G, NJVMJD44H11D3T4G,<br>NJVMJD45H11D3T4G OPNs marked as Discontinued.|12/12/2025|



This document has undergone updates prior to the inclusion of this revision history table. The changes tracked here only reflect updates made on the noted approval dates. 

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MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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4<br>1 [2]<br>3<br>SCALE 1:1<br>**----- End of picture text -----**<br>


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DPAK−3 6.10x6.54x2.28, 2.29P<br>CASE 369C<br>ISSUE K<br>**----- End of picture text -----**<br>


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DATE 14 MAY 2026<br>**----- End of picture text -----**<br>


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Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON10527D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: DPAK−3 6.10x6.54x2.28, 2.29P PAGE 1 OF 2** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

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© Semiconductor Components Industries, LLC, 2011 

DATE 13 MAY 2026 

**DPAK−3 6.10x6.54x2.28, 2.29P** CASE 369C ISSUE K 

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GENERIC<br>MARKING DIAGRAM*<br>XXXXXXG AYWW<br>ALYWW XXX<br>XXXXXG<br>IC Discrete<br>XXXXXX = Device Code<br>A = Assembly Location<br>L = Wafer Lot<br>Y =  Year<br>WW = Work Week<br>G = Pb−Free Package<br>**----- End of picture text -----**<br>


*This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ � ”, may or may not be present. Some products may not follow the Generic Marking. 

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STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5:<br>PIN 1. BASE PIN 1. GATE PIN 1. ANODE PIN 1. CATHODE PIN 1. GATE<br>2. COLLECTOR 2. DRAIN 2. CATHODE 2. ANODE 2. ANODE<br>3. EMITTER 3. SOURCE 3. ANODE 3. GATE 3. CATHODE<br>4. COLLECTOR 4. DRAIN 4. CATHODE 4. ANODE 4. ANODE<br>STYLE 6: STYLE 7: STYLE 8: STYLE 9: STYLE 10:<br>PIN 1. MT1 PIN 1. GATE PIN 1. N/C PIN 1. ANODE PIN 1. CATHODE<br>2. MT2 2. COLLECTOR 2. CATHODE 2. CATHODE 2. ANODE<br>3. GATE 3. EMITTER 3. ANODE 3. RESISTOR ADJUST 3. CATHODE<br>4. MT2 4. COLLECTOR 4. CATHODE 4. CATHODE 4. ANODE<br>**----- End of picture text -----**<br>


Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON10527D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: DPAK−3 6.10x6.54x2.28, 2.29P PAGE 2 OF 2** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

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© Semiconductor Components Industries, LLC, 2011 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**IPAK** CASE 369D ISSUE C 

DATE 15 DEC 2010 

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B C NOTES:<br>SCALE 1:1 1. DIMENSIONING AND TOLERANCING PER<br>V R E ANSI Y14.5M, 1982.<br>2. CONTROLLING DIMENSION: INCH.<br>INCHES MILLIMETERS<br>4 Z DIM MIN MAX MIN MAX<br>A 0.235 0.245 5.97 6.35<br>S A B 0.250 0.265 6.35 6.73<br>1 2 3 C 0.086 0.094 2.19 2.38<br>D 0.027 0.035 0.69 0.88<br>E 0.018 0.023 0.46 0.58<br>−T− F 0.037 0.045 0.94 1.14<br>SEATING G 0.090 BSC 2.29 BSC<br>PLANE K H 0.034 0.040 0.87 1.01<br>J 0.018 0.023 0.46 0.58<br>K 0.350 0.380 8.89 9.65<br>R 0.180 0.215 4.45 5.45<br>J S 0.025 0.040 0.63 1.01<br>F<br>H V 0.035 0.050 0.89 1.27<br>Z 0.155 −−− 3.93 −−−<br>D 3 PL<br>G 0.13 (0.005) M T<br>GENERIC MARKING<br>DIAGRAMS<br>STYLE 1:PIN 1. BASE STYLE 2:PIN 1. GATE STYLE 3:PIN 1. ANODE STYLE 4:PIN 1. CATHODE Integrated<br>2. COLLECTOR 2. DRAIN 2. CATHODE 2. ANODE Discrete Circuits<br>3. EMITTER 3. SOURCE 3. ANODE 3. GATE<br>4. COLLECTOR 4. DRAIN 4. CATHODE 4. ANODE<br>YWW xxxxx<br>STYLE 5: STYLE 6: STYLE 7: xxxxxxxx ALYWW<br>PIN 1. GATE PIN 1. MT1 PIN 1. GATE<br>2. ANODE 2. MT2 2. COLLECTOR x<br>3. CATHODE 3. GATE 3. EMITTER<br>4. ANODE 4. MT2 4. COLLECTOR<br>xxxxxxxxx = Device Code<br>A = Assembly Location<br>lL = Wafer Lot<br>Y =  Year<br>WW = Work Week<br>**----- End of picture text -----**<br>


- *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ � ”, may or may not be present. Some products may not follow the Generic Marking. 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON10528D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: IPAK (DPAK INSERTION MOUNT) PAGE 1 OF 1** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2010 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**DPAK−3, SURFACE MOUNT** CASE 369G ISSUE O 

**==> picture [45 x 58] intentionally omitted <==**

**----- Start of picture text -----**<br>
4<br>1<br>2<br>3<br>SCALE 1:1<br>**----- End of picture text -----**<br>


**==> picture [207 x 167] intentionally omitted <==**

**----- Start of picture text -----**<br>
−T− SEATING<br>PLANE<br>B C<br>V R E<br>4<br>A<br>1 2 3<br>U<br>K<br>F<br>L J<br>G H<br>D 2 PL<br>0.13 (0.005) T<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Z<br>**----- End of picture text -----**<br>


DATE 23 DEC 2003 

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**----- Start of picture text -----**<br>
NOTES:<br>1. DIMENSIONING AND TOLERANCING<br>PER ANSI Y14.5M, 1982.<br>2. CONTROLLING DIMENSION: INCH.<br>INCHES MILLIMETERS<br>DIM MIN MAX MIN MAX<br>A 0.235 0.245 5.97 6.22<br>B 0.250 0.265 6.35 6.73<br>C 0.086 0.094 2.19 2.38<br>D 0.027 0.035 0.69 0.88<br>E 0.018 0.023 0.46 0.58<br>F 0.037 0.045 0.94 1.14<br>G 0.180 BSC 4.58 BSC<br>H 0.034 0.040 0.87 1.01<br>J 0.018 0.023 0.46 0.58<br>K 0.102 0.114 2.60 2.89<br>L 0.090 BSC 2.29 BSC<br>R 0.180 0.215 4.57 5.45<br>U 0.020 −−− 0.51 −−−<br>V 0.035 0.050 0.89 1.27<br>Z 0.155 −−− 3.93 −−−<br>**----- End of picture text -----**<br>


## **GENERIC MARKING DIAGRAM*** 

- STYLE 1: STYLE 2: STYLE 3: STYLE 4: PIN 1. BASE PIN 1. GATE PIN 1. ANODE PIN 1. CATHODE 2. COLLECTOR 2. DRAIN 2. CATHODE 2. ANODE 3. EMITTER 3. SOURCE 3. ANODE 3. GATE 4. COLLECTOR 4. DRAIN 4. CATHODE 4. ANODE 

- STYLE 5: STYLE 6: STYLE 7: PIN 1. GATE PIN 1. MT1 PIN 1. GATE 2. ANODE 2. MT2 2. COLLECTOR 3. CATHODE 3. GATE 3. EMITTER 4. ANODE 4. MT2 4. COLLECTOR 

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**----- Start of picture text -----**<br>
YWW<br>xxxxxxxx<br>xxxxxxxxx = Device Code<br>Y =  Year<br>WW = Work Week<br>**----- End of picture text -----**<br>


- *This information is generic. Please refer to device data sheet for actual part marking. 

**==> picture [493 x 37] intentionally omitted <==**

**----- Start of picture text -----**<br>
Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>DOCUMENT NUMBER: 98AON13702D Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.<br>DESCRIPTION: DPAK−3, SURFACE MOUNT PAGE 1 OF 1<br>**----- End of picture text -----**<br>


**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2003 

**onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** ’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

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 



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---

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