# Bipolar (BJT) Single Transistor, Darlington, PNP, 100 V, 2 A, 1.75 W, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:1703972/)

**URL**: https://novapart.co/products/MJD117G/bipolar-bjt-single-transistor-darlington-pnp-100-v
**SKU**: MJD117G
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || Transistors || Bipolar Transistors || Single Bipolar Junction Transistors - BJT
**Price**: €0.6210
**Stock**: 10+
**Lead Time**: 168 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 4Pins |
| Qualification | AEC-Q101 |
| Power Dissipation | 1.75W |
| Dc Current Gain Hfe | 12hFE |
| Transistor Mounting | Surface Mount |
| Transistor Polarity | PNP |
| Transition Frequency | 25MHz |
| Transistor Case Style | TO-252 (DPAK) |
| Dc Current Gain Hfe Min | 12hFE |
| Operating Temperature Max | 150°C |
| Continuous Collector Current | 2A |
| Collector Emitter Voltage Max | 100V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:1703972/)

**Share Feedback DATA SHEET** Your Opinion Matters **www.onsemi.com** ~~ee~~ 

## Complementary Darlington Power Transistors 

## **DPAK For Surface Mount Applications** 

## **SILICON POWER TRANSISTORS 2 AMPERES 100 VOLTS, 20 WATTS** 

## MJD112 (NPN), MJD117 (PNP) 

Designed for general purpose power and switching such as output or driver stages in applications such as switching regulators, converters, and power amplifiers. 

## **Features** 

- Lead Formed for Surface Mount Applications in Plastic Sleeves (No Suffix) 

- Straight Lead Version in Plastic Sleeves (“−1” Suffix) 

- Electrically Similar to Popular TIP31 and TIP32 Series 

- NJV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable 

- These Devices are Pb−Free and are RoHS Compliant* 

**DPAK DPAK−3 CASE 369C CASE 369D MARKING DIAGRAMS** 

**==> picture [163 x 118] intentionally omitted <==**

**----- Start of picture text -----**<br>
AYWW YWW<br>J11xG J11xG<br>4) 3 )<br>DPAK DPAK−3<br>A = Assembly Location<br>Y = Year<br>WW = Work Week<br>x = 2 or 7<br>G = Pb−Free Package<br>**----- End of picture text -----**<br>


## **ORDERING INFORMATION** 

See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. 

> *For additional information on our Pb−Free strategy and soldering details, please download the **onsemi** Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

Publication Order Number: **MJD112/D** 

**1** 

© Semiconductor Components Industries, LLC, 2013 **July, 2025 − Rev. 15** 

**MJD112 (NPN), MJD117 (PNP)** 

## **MAXIMUM RATINGS** 

|**MAXIMUM RATINGS**||||
|---|---|---|---|
|**Rating**|**Symbol**|**Max**|**Unit**|
|Collector−Emitter Voltage|VCEO|100|Vdc|
|Collector−Base Voltage|VCB|100|Vdc|
|Emitter−Base Voltage|VEB|5|Vdc|
|Collector Current<br>Continuous<br>Peak|IC|2<br>4|Adc|
|Base Current|IB|50|mAdc|
|Total Power Dissipation<br>@ TC= 25°C<br>Derate above 25°C|PD|20<br>0.16|W<br>W/°C|
|Total Power Dissipation (Note1)<br>@ TA= 25°C<br>Derate above 25°C|PD|1.75<br>0.014|W<br>W/°C|
|Operating and Storage Junction Temperature Range|TJ, Tstg|−65 to +150|°C|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

## **THERMAL CHARACTERISTICS** 

|**THERMAL CHARACTERISTICS**||||
|---|---|---|---|
|**Characteristic**|**Symbol**|**Max**|**Unit**|
|Thermal Resistance, Junction−to−Case|R JC|6.25|°C/W|
|Thermal Resistance, Junction−to−Ambient (Note 1)|R JA|71.4|°C/W|



1. These ratings are applicable when surface mounted on the minimum pad sizes recommended. 

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## **MJD112 (NPN), MJD117 (PNP)** 

|ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ<br>**ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ**ÎÎÎÎÎÎÎÎÎÎÎÎ<br>**ELECTRICAL CHARACTERISTICS**(TC= 25 C unless otherwise noted)<br>ÎÎÎ**Î**<br>ÎÎ**Î**<br>ÎÎÎ<br>ÎÎÎÎ|
|---|
|**ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ**<br>**Characteristic**<br>ÎÎÎ**Î**<br>**Symbol**<br>ÎÎ**Î**<br>**Min**<br>ÎÎÎ<br>**Max**<br>ÎÎÎÎ<br>**Unit**<br>ÎÎÎÎÎÎÎÎÎÎÎÎ<br>**ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ**ÎÎÎÎÎÎÎÎÎÎÎÎ<br>**OFF CHARACTERISTICS**<br>ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ<br>**ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ**<br>Collector−Emitter Sustaining Voltage (Note 2)<br>(IC= 30 mAdc, IB= 0)<br>ÎÎÎ**Î**<br>ÎÎÎ**Î**<br>**ÎÎÎÎ**<br>VCEO(sus)<br>ÎÎ**Î**<br>ÎÎ**Î**<br>**ÎÎÎ**<br>100<br>ÎÎÎ<br>ÎÎÎ<br>**ÎÎÎ**<br>−<br>ÎÎÎÎ<br>ÎÎÎÎ<br>**ÎÎÎÎ**<br>Vdc<br>ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ<br>**ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ**<br>Collector Cutoff Current<br>(VCE= 50 Vdc, IB= 0)<br>ÎÎÎ**Î**<br>**ÎÎÎÎ**<br>ICEO<br>ÎÎ**Î**<br>**ÎÎÎ**<br>−<br>ÎÎÎ<br>**ÎÎÎ**<br>20<br>Î<br>ÎÎ<br>**Î**<br>**ÎÎ**<br>Adc<br>**ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ**<br>Collector Cutoff Current<br>(VCB= 100 Vdc, IE= 0)<br>**ÎÎÎÎ**<br>ICBO<br>**ÎÎÎ**<br>−<br>**ÎÎÎ**<br>20<br>**ÎÎÎÎ**<br>Adc<br>ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ<br>**ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ**<br>Emitter Cutoff Current<br>(VBE= 5 Vdc, IC= 0)<br>ÎÎÎ**Î**<br>**ÎÎÎÎ**<br>IEBO<br>ÎÎ**Î**<br>**ÎÎÎ**<br>−<br>ÎÎÎ<br>**ÎÎÎ**<br>2<br>ÎÎÎÎ<br>**ÎÎÎÎ**<br>mAdc<br>ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ<br>**ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ**<br>Collector−Cutoff Current<br>(VCB= 80 Vdc, IE= 0)<br>ÎÎÎ**Î**<br>**ÎÎÎÎ**<br>ICBO<br>ÎÎ**Î**<br>**ÎÎÎ**<br>−<br>ÎÎÎ<br>**ÎÎÎ**<br>10<br>Î<br>ÎÎ<br>**ÎÎÎÎ**<br>Adc<br>**ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ**<br>Emitter−Cutoff Current<br>(VBE= 5 Vdc, IC= 0)<br>ÎÎÎ**Î**<br>IEBO<br>ÎÎ**Î**<br>−<br>ÎÎÎ<br>2<br>ÎÎÎÎ<br>mAdc<br>ÎÎÎÎÎÎÎÎÎÎÎÎ<br>~~er~~|
|**ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ**ÎÎÎÎÎÎÎÎÎÎÎÎ<br>**ON CHARACTERISTICS**<br>ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ<br>ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ<br>**ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ**<br>DC Current Gain<br>(IC= 0.5 Adc, VCE= 3 Vdc)<br>(IC= 2 Adc, VCE= 3 Vdc)<br>(IC= 4 Adc, VCE= 3 Vdc)<br>ÎÎÎ**Î**<br>ÎÎÎ**Î**<br>ÎÎÎ**Î**<br>**ÎÎÎÎ**<br>hFE<br>ÎÎ**Î**<br>ÎÎ**Î**<br>ÎÎ**Î**<br>**ÎÎÎ**<br>500<br>1000<br>200<br>ÎÎÎ<br>ÎÎÎ<br>ÎÎÎ<br>**ÎÎÎ**<br>−<br>12,000<br>−<br>ÎÎÎÎ<br>ÎÎÎÎ<br>ÎÎÎÎ<br>**ÎÎÎÎ**<br>−<br>ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ<br>ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ<br>**ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ**<br>Collector−Emitter Saturation Voltage<br>(IC= 2 Adc, IB= 8 mAdc)<br>(IC= 4 Adc, IB= 40 mAdc)<br>ÎÎÎ**Î**<br>ÎÎÎ**Î**<br>**ÎÎÎÎ**<br>VCE(sat)<br>ÎÎ**Î**<br>ÎÎ**Î**<br>**ÎÎÎ**<br>−<br>−<br>ÎÎÎ<br>ÎÎÎ<br>**ÎÎÎ**<br>2<br>3<br>ÎÎÎÎ<br>ÎÎÎÎ<br>**ÎÎÎÎ**<br>Vdc<br>**ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ**<br>Base−Emitter Saturation Voltage<br>(IC= 4 Adc, IB= 40 mAdc)<br>**ÎÎÎÎ**<br>VBE(sat)<br>**ÎÎÎ**<br>−<br>**ÎÎÎ**<br>4<br>**ÎÎÎÎ**<br>Vdc<br>ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ<br>**ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ**<br>Base−Emitter On Voltage<br>(IC= 2 Adc, VCE= 3 Vdc)<br>ÎÎÎ**Î**<br>ÎÎÎ**Î**<br>VBE(on)<br>ÎÎ**Î**<br>ÎÎ**Î**<br>−<br>ÎÎÎ<br>ÎÎÎ<br>2.8<br>ÎÎÎÎ<br>ÎÎÎÎ<br>Vdc<br>ÎÎÎÎÎÎÎÎÎÎÎÎ<br>**ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ**ÎÎÎÎÎÎÎÎÎÎÎÎ<br>**DYNAMIC CHARACTERISTICS**<br>ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ<br>Current−Gain − Bandwidth Product<br>(IC= 0.75 Adc, VCE= 10 Vdc, f = 1 MHz)<br>ÎÎÎ**Î**<br>ÎÎÎ**Î**<br>fT<br>ÎÎ**Î**<br>ÎÎ**Î**<br>25<br>ÎÎÎ<br>ÎÎÎ<br>−<br>ÎÎÎÎ<br>ÎÎÎÎ<br>MHz<br>~~ee~~|
|**ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ**<br>**ÎÎÎÎ**<br>**ÎÎÎ**<br>**ÎÎÎ**<br>**ÎÎÎÎ**<br>ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ<br>ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ<br>Output Capacitance<br>(VCB= 10 Vdc, IE= 0, f = 0.1 Mhz)<br>MJD117, NJVMJD117T4G<br>MJD112, NJVMJD112G, NJVMJD112T4G<br>ÎÎÎ**Î**<br>ÎÎÎ**Î**<br>Cob<br>ÎÎ**Î**<br>ÎÎ**Î**<br>−<br>−<br>ÎÎÎ<br>ÎÎÎ<br>200<br>100<br>ÎÎÎÎ<br>ÎÎÎÎ<br>pF|



2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 

- *These ratings are applicable when surface mounted on the minimum pad sizes recommended. 

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**MJD112 (NPN), MJD117 (PNP)** 

**==> picture [487 x 390] intentionally omitted <==**

**----- Start of picture text -----**<br>
RB & RC VARIED TO OBTAIN DESIRED CURRENT LEVELS VCC 4<br>; 1 [, MUST BE FAST RECOVERY TYPE, e.g.:] B [≈][ 100 mA] ey SUNIL ts TL IVCCC/IB = 30 V = 250 ITB1J = 25 = IB2°C<br>MSD61001N5825 USEDUSED ABOVEBELOW| | B [≈][ 100 mA] RC SCOPE 2 GaN: Ww L l 4<br>TUT<br>APPROXV2 RB r—---~-t=5"° ARSx : tf NSS<br>1<br>+8V a Pe LUNy e LO N<br>0 ee ee"] 51 D1 l| HL ≈ 8 k ≈ 60 p || S8= 0.80.6 EpKSoCTENaESOS,NeeE E tr<br>V1<br>APPROX 7 | t nNO= eee S<br>-12 V 25 s + 4 V 0.4 PeTSS PSS r td @ VBE(off) = 0 V<br>tDUTY CYCLE = 1%r, tf ≤ 10 ns FOR tAND Vd2 AND t = 0 r, D1 IS DISCONNECTED 0.2 PNPNPN<br>aS sani<br>FOR NPN TEST CIRCUIT REVERSE ALL POLARITIES. 0.04 0.06 0.1 0.2 0.4 0.6 1 2 4<br>IC, COLLECTOR CURRENT (AMP)<br>Figure 1. Switching Times Test Circuit Figure 2. Switching Times<br>1<br>0.7 D = 0.5<br>= SSS SSae<br>0.5 Se ee nc<br>a aOt<br>0.3 0.2<br>a a<br>0.2 a 0.1 ee R JC(t) = r(t) R JC P (pk) ee<br>0.1 aeer 0.05 —— 2 — ae R JC = 6.25°C/W ; inna<br>0.07 ee 0.01 [ee] er TLeee| eeety D CURVES APPLY FOR POWERPULSE TRAIN SHOWN PLP t 1 ImeLee<br>0.050.03 =Lar = SINGLE PULSE |adT =TTeerT e e eeTTeee ee READ TIME AT t T J(pk) - T C = P (pk) 1 JC(t) =) DUTY CYCLE, D = t t 2 1 /t 2 InnEHHImani<br>0.02 eeeeoo Q tT<br>Pt | TP TTPT__---. — — —— —--2<br>0.01 ee ee ell<br>0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 5 10 20 30 50 100 200 300 500 1000<br>t, TIME OR PULSE WIDTH (ms)<br>r(t), EFFECTIVE TRANSIENT<br>THERMAL RESISTANCE (NORMALIZED)<br>**----- End of picture text -----**<br>


**Figure 3. Thermal Response** 

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**MJD112 (NPN), MJD117 (PNP)** 

## **ACTIVE−REGION SAFE−OPERATING AREA** 

**==> picture [488 x 406] intentionally omitted <==**

**----- Start of picture text -----**<br>
TA TC<br>10 2.5 25<br>7<br>5<br>s<br>3<br>2 s 2 20<br>Sesser] i P< | CPP Pr rrr tT<br>1 PN PN Tt<br>0.7 1.5 15<br>0.5 dc<br>0.30.2 EH BONDING WIRE LIMITED )  SSR 1 10 SSX TA TC<br>0.1 THERMAL LIMITSECOND BREAKDOWN LIMIT eee[Ns ee SURFACE  MOUNT RBS<br>= TJ = 150°C e 5S a 0.5 |AG 5 SSeS<br>CURVES APPLY BELOW RATED VCEO<br>= _ oos 0 0 SSFt tT | | | cE rE dE a<br>2 3 5 7 10 20 30 50 70 100 200 25 50 75 100 125 15<br>VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) T, TEMPERATURE (°C)<br>Figure 4. Maximum Rated Forward Biased Figure 5. Power Derating<br>Safe Operating Area<br>There are two limitations on the power handling ability of 200<br>a transistor: average junction temperature and second<br>breakdown. Safe operating area curves indicate IC − VCEC − VCE− VCECE foe ce TC = 25°C<br>100<br>limits of the transistor that must be observed for reliable<br>operation; i.e., the transistor must not be subjected to greater 70 PATHE ee SS EE<br>PTT TT PT PTT TPT AT TT<br>dissipation than the curves indicate. 50<br>° PLU Tt TT TT ET TT PETIA TT<br>The data of Figures 5 and 6 is based on TJ(pk) = 150J(pk) = 150 = 150 C; TCC C ob<br>is variable depending on conditions. Second breakdown 30 SSH TH) OS<br>pulse limits are valid for duty cycles to 10% provided Cib<br>J(pk) < 150 < 150 : C. TJ(pk) may be calculated from the data inJ(pk) may be calculated from the data in may be calculated from the data in 20 SeeCIE LE EATSHIT S<br>Figure 4. At high case temperatures, thermal limitations will PNP<br>reduce the power that can be handled to values less than the NPN<br>10<br>limitations imposed by second breakdown. 0.04 Lars 0.06 0.1 0.2 0.4 [LE] 0.6 1 2 4 6 10 Pi 20 40<br>VR, REVERSE VOLTAGE (VOLTS)<br>Figure 6. Capacitance<br>IC, COLLECTOR CURRENT (AMP) PD, POWER DISSIPATION (WATTS)<br>C, CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC − VCEC − VCE− VCECE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. 

The data of Figures 5 and 6 is based on TJ(pk) = 150J(pk) = 150 = 150 C; TCC is variable depending on conditions. Second breakdown pulse limits are valid for duty cycles to 10% provided TJ(pk) < 150 < 150 : C. TJ(pk) may be calculated from the data inJ(pk) may be calculated from the data in may be calculated from the data in Figure 4. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. 

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**MJD112 (NPN), MJD117 (PNP)** 

## **TYPICAL ELECTRICAL CHARACTERISTICS** 

## **NPN MJD112** 

## **PNP MJD117** 

**==> picture [490 x 590] intentionally omitted <==**

**----- Start of picture text -----**<br>
6 k 6 k<br>P| tt TJ = 125°C ATTEN VCE = 3 V PTT TTT TC = 125°C | TTT itt | VCE = 3 V<br>4 k 4 k<br>S a et<br>3 k 3 k<br>PIA EN TT PCT A 25°C a<br>2 k 25°C 2 k<br>ae a re nnN)40 Z N<br>A e A eeN<br>1 k Yo A 1 k<br>800 °C 800 °C<br>600 Pos ZoA LINN , 600 (AnyLA Anny N  oeAGNN<br>400 de at 400 HH 88 A HH AN<br>300 ©4800) en eete 300 PTTast ZeeTt TT ttt;eeTTT<br>0.04 0.06 0.1 0.2 0.4 0.6 1 2 4 0.04 0.06 0.1 0.2 0.4 0.6 1 2 4<br>IC, COLLECTOR CURRENT (AMP) IC, COLLECTOR CURRENT (AMP)<br>Figure 7. DC Current  Gain<br>3.4 3.4<br>TJ = 125°C TJ = 125°C<br>3 pif IC = EEEfeef EEpepeETT Hl 3 yfPTE fpET Tp EY|<br>0.5 A IC = 1 A 2 A 4 A<br>2.6 ee 1 A 2 A ell 4 A 2.6 | 0.5 A Sa eel<br>eeSe Peeee peeee || aee a r ell<br>2.2 a ee ell 2.2 ee ee ee ll<br>ae en eel ee ee ee ll<br>1.8 a ell 1.8 ee<br>1.4 aae ee lll 1.4 aeeee ll ll<br>a lllell Oeee eeSele l l<br>1 ICN IS EET 1 ee ee |<br>| | Se SS ee ST SET<br>0.6 Pet Pe 0.6 PTT ETE EerEooo IT TT<br>0.1 0.2 0.5 1 2 5 10 20 50 100 0.1 0.2 0.5 1 2 5 10 20 50 100<br>IB, BASE CURRENT (mA) IB, BASE CURRENT (mA)<br>Figure 8. Collector Saturation Region<br>2.2 2.2<br>TJ = 25°C TJ = 25°C<br>1.8 arm TT TE 1.8 pm TTT TT<br>| TATE a CTT<br>e e A<br>1.4 VBE(sat) @ IC/IB = 250 VBE @ VCE = 3 V 1.4 VBE(sat) @ IC/IB = 250 VBE @ VCE = 3 V<br>- e PCIE eee<br>ie TT ee=> ae<br>1 1<br>SI PTPr<br>peer VCE(sat) @ IC/IB = 250 VCE(sat) @ IC/IB = 250 ee t<br>0.6 Pte oo IE 0.6 P eoeeEd<br>| Le<br>0.2 EL 0.2 nL |<br>0.04 0.06 0.1 0.2 0.4 0.6 1 2 4 0.04 0.06 0.1 0.2 0.4 0.6 1 2 4<br>IC, COLLECTOR CURRENT (AMP) IC, COLLECTOR CURRENT (AMP)<br>hFE, DC CURRENT GAIN hFE, DC CURRENT GAIN<br>VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)<br>V, VOLTAGE (VOLTS) V, VOLTAGE (VOLTS)<br>**----- End of picture text -----**<br>


**Figure 9. “On Voltages** 

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**MJD112 (NPN), MJD117 (PNP)** 

**NPN MJD112** 

**PNP MJD117** 

**==> picture [484 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
*APPLIED FOR IC/IB < hFE/3 *APPLIES FOR IC/IB < hFE/3<br>we 0 PIT EE Pt 0 : HE<br>25°C TO 150°C<br>osa PT AG<br>LO FP Tr Pr yg PETE PT an<br>25°C TO 150°C<br>aeoy) PEPCOLO * VC FOR VCE(sat) FP ee 7ee PCO e * VC FOR V e CE(sat) eee °C TO 25°C<br>eeect °C TO 25°C ey 25°C TO 150°C AW,<br>salrLT FT t 25°C TO 150°C ew e e Se ee ea|<br>°C TO 25°C<br>VC [ FOR V] BE °C TO 25°C VB [ FOR V] BE<br>tLe | = aantil<br>ee = ey es [OO]<br>asL 0.04 LUT 0.06 0.1 PP 0.2 TT 0.4 0.6 1 2 4 gg 0.04 DEE 0.06 0.1 0.2 0.4 0.6 1 2 4<br>IC, COLLECTOR CURRENT (AMP) IC, COLLECTOR CURRENT (AMP)<br>C)° C)°<br>V, TEMPERATURE COEFFICIENTS (mV/ V, TEMPERATURE COEFFICIENTS (mV/<br>θ θ<br>**----- End of picture text -----**<br>


**Figure 10. Temperature Coefficients** 

**==> picture [481 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 [5] 10 [5]<br>REVERSE FORWARD REVERSE FORWARD<br>en 10 [4] SS 10 [4]<br>SS ee<br>10 [3] VCE = 30 V 10 [3] VCE = 30 V<br>cSS ess SSS SSES BES ESSS3 i BS SS oc Se eee SSS SS ESS eSSSS<br>10 [2] 10 [2]<br>TJ = 150 ° C TJ = 150 ° C<br>10 [1] 10 [1]<br>100°C<br>Bo  A SB OEAZ<br>10 [0] 100°C 10 [0] 25°C<br>25°C<br>10 [-1] Le —— ee ee ee e e 10 [-1] rraee e e<br>-0.6 -0.4 -0.2 0 +0.2 +04 +06 +08 +1 +12 +14 +0.6 +0.4 +0.2 0 -0.2 -04 -06 -08 -1 -12<br>VBE, BASE-EMITTER VOLTAGE (VOLTS) VBE, BASE-EMITTER VOLTAGE (VOLTS)<br>IC IC<br>**----- End of picture text -----**<br>


**Figure 11. Collector Cut−Off Region** 

**==> picture [408 x 121] intentionally omitted <==**

**----- Start of picture text -----**<br>
PNP COLLECTOR NPN COLLECTOR<br>a: | ae || a | ae ||<br>||<br>BASE | BASE |<br>||<br>| | | |<br>| ≈ 8 k ≈ 120 | ≈ 8 k ≈ 120<br>| | | |<br>e e e e| L—— —— — 4} [_] [_] J J<br>EMITTER EMITTER<br>**----- End of picture text -----**<br>


**Figure 12. Darlington Schematic** 

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**MJD112 (NPN), MJD117 (PNP)** 

## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**<br>~~es~~||||
|---|---|---|---|
|**Device**<br>~~es~~<br>~~a~~|**Package Type**<br>~~ee~~|**Package**<br>~~ee~~|**Shipping**†|
|MJD112G<br>~~es~~<br>~~a~~<br>~~a~~|DPAK<br>(Pb−Free)<br>~~ee~~<br>~~ee~~|369C<br>~~ee~~<br>~~ee~~|75 Units / Rail|
|NJVMJD112G*<br>~~a~~<br>~~a~~<br>~~a~~|DPAK<br>(Pb−Free)<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|369C<br>~~ee~~<br>~~ee~~<br>~~ee~~|75 Units / Rail|
|MJD112−1G<br>~~a~~<br>~~a~~<br>~~a~~|DPAK−3<br>(Pb−Free)<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|369D<br>~~ee~~<br>~~ee~~|75 Units / Rail|
|MJD112RLG<br>~~a~~<br>~~a~~<br>~~a~~|DPAK<br>(Pb−Free)<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|369C<br>~~ee~~|1,800 Tape & Reel|
|MJD112T4G<br>~~a~~<br>~~a~~<br>~~a~~|DPAK<br>(Pb−Free)<br>~~ee~~<br>~~ee~~<br>~~ee~~|369C|2,500 Tape & Reel|
|NJVMJD112T4G*<br>~~a~~<br>~~a~~<br>~~a~~|DPAK<br>(Pb−Free)<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|369C<br>~~ee~~|2,500 Tape & Reel|
|MJD117G<br>~~a~~<br>~~a~~<br>~~a~~|DPAK<br>(Pb−Free)<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|369C<br>~~ee~~|75 Units / Rail|
|MJD117−1G<br>~~a~~<br>~~a~~<br>~~a~~|DPAK−3<br>(Pb−Free)<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|369D<br>~~ee~~|75 Units / Rail|
|MJD117RLG<br>~~a~~<br>~~a~~<br>~~a~~|DPAK<br>(Pb−Free)<br>~~ee~~<br>~~ee~~<br>~~ee~~|369C|1,800 Tape & Reel|
|MJD117T4G<br>~~a~~<br>~~a~~|DPAK<br>(Pb−Free)<br>~~ee~~<br>~~ee~~|369C|2,500 Tape & Reel|
|NJVMJD117T4G*<br>~~a~~<br>~~a~~|DPAK<br>(Pb−Free)<br>~~ee~~|369C|2,500 Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

*NJV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable. 

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MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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DPAK−3 6.10x6.54x2.28, 2.29P<br>CASE 369C<br>ISSUE K<br>**----- End of picture text -----**<br>


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Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON10527D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: DPAK−3 6.10x6.54x2.28, 2.29P PAGE 1 OF 2** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2011 

DATE 13 MAY 2026 

**DPAK−3 6.10x6.54x2.28, 2.29P** CASE 369C ISSUE K 

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**----- Start of picture text -----**<br>
GENERIC<br>MARKING DIAGRAM*<br>XXXXXXG AYWW<br>ALYWW XXX<br>XXXXXG<br>IC Discrete<br>XXXXXX = Device Code<br>A = Assembly Location<br>L = Wafer Lot<br>Y =  Year<br>WW = Work Week<br>G = Pb−Free Package<br>**----- End of picture text -----**<br>


*This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ � ”, may or may not be present. Some products may not follow the Generic Marking. 

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**----- Start of picture text -----**<br>
STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5:<br>PIN 1. BASE PIN 1. GATE PIN 1. ANODE PIN 1. CATHODE PIN 1. GATE<br>2. COLLECTOR 2. DRAIN 2. CATHODE 2. ANODE 2. ANODE<br>3. EMITTER 3. SOURCE 3. ANODE 3. GATE 3. CATHODE<br>4. COLLECTOR 4. DRAIN 4. CATHODE 4. ANODE 4. ANODE<br>STYLE 6: STYLE 7: STYLE 8: STYLE 9: STYLE 10:<br>PIN 1. MT1 PIN 1. GATE PIN 1. N/C PIN 1. ANODE PIN 1. CATHODE<br>2. MT2 2. COLLECTOR 2. CATHODE 2. CATHODE 2. ANODE<br>3. GATE 3. EMITTER 3. ANODE 3. RESISTOR ADJUST 3. CATHODE<br>4. MT2 4. COLLECTOR 4. CATHODE 4. CATHODE 4. ANODE<br>**----- End of picture text -----**<br>


Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON10527D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: DPAK−3 6.10x6.54x2.28, 2.29P PAGE 2 OF 2** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2011 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**IPAK** CASE 369D ISSUE C 

DATE 15 DEC 2010 

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**----- Start of picture text -----**<br>
B C NOTES:<br>SCALE 1:1 1. DIMENSIONING AND TOLERANCING PER<br>V R E ANSI Y14.5M, 1982.<br>2. CONTROLLING DIMENSION: INCH.<br>INCHES MILLIMETERS<br>4 Z DIM MIN MAX MIN MAX<br>A 0.235 0.245 5.97 6.35<br>S A B 0.250 0.265 6.35 6.73<br>1 2 3 C 0.086 0.094 2.19 2.38<br>D 0.027 0.035 0.69 0.88<br>E 0.018 0.023 0.46 0.58<br>−T− F 0.037 0.045 0.94 1.14<br>SEATING G 0.090 BSC 2.29 BSC<br>PLANE K H 0.034 0.040 0.87 1.01<br>J 0.018 0.023 0.46 0.58<br>K 0.350 0.380 8.89 9.65<br>R 0.180 0.215 4.45 5.45<br>J S 0.025 0.040 0.63 1.01<br>F<br>H V 0.035 0.050 0.89 1.27<br>Z 0.155 −−− 3.93 −−−<br>D 3 PL<br>G 0.13 (0.005) M T<br>GENERIC MARKING<br>DIAGRAMS<br>STYLE 1:PIN 1. BASE STYLE 2:PIN 1. GATE STYLE 3:PIN 1. ANODE STYLE 4:PIN 1. CATHODE Integrated<br>2. COLLECTOR 2. DRAIN 2. CATHODE 2. ANODE Discrete Circuits<br>3. EMITTER 3. SOURCE 3. ANODE 3. GATE<br>4. COLLECTOR 4. DRAIN 4. CATHODE 4. ANODE<br>YWW xxxxx<br>STYLE 5: STYLE 6: STYLE 7: xxxxxxxx ALYWW<br>PIN 1. GATE PIN 1. MT1 PIN 1. GATE<br>2. ANODE 2. MT2 2. COLLECTOR x<br>3. CATHODE 3. GATE 3. EMITTER<br>4. ANODE 4. MT2 4. COLLECTOR<br>xxxxxxxxx = Device Code<br>A = Assembly Location<br>lL = Wafer Lot<br>Y =  Year<br>WW = Work Week<br>**----- End of picture text -----**<br>


- *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ � ”, may or may not be present. Some products may not follow the Generic Marking. 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON10528D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: IPAK (DPAK INSERTION MOUNT) PAGE 1 OF 1** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2010 

**onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** ’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

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- [Supplier page](https://es.farnell.com/en-ES/on-semiconductor/mjd117g/bipolar-transistor/dp/1703972)
---

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