# MEMS Accelerometer, ± 2g, ± 4g, ± 8g, ± 16g, X, Y, Z, I2C, MIPI I3C, SPI, LGA, 12 Pins
**URL**: https://novapart.co/products/MIS2DU12TR/mems-accelerometer-2g-4g-8g-16g-x-y-z-i2c-mipi-i3c
**SKU**: MIS2DU12TR
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - ICs || IC Sensors || MEMS Accelerometers
**Price**: €10.0600
**Stock**: 10+
## Specifications
| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 12Pins |
| Sensing Axis | X, Y, Z |
| Product Range | - |
| Qualification | - |
| Sensitivity Typ | - |
| Output Interface | I2C, MIPI I3C, SPI |
| Supply Voltage Max | 3.6V |
| Supply Voltage Min | 1.62V |
| Sensor Case / Package | LGA |
| Operating Temperature Max | 85°C |
| Operating Temperature Min | -40°C |
| Sensing Range - Accelerometer | ± 2g, ± 4g, ± 8g, ± 16g |
## Datasheet
📄 [Download PDF](https://novapart.co/datasheet/farnell:4843337/)
**MIS2DU12**
Datasheet
## Ultralow-power accelerometer with antialiasing and motion detection
## **Features**
- Supply voltage range from 1.62 to 3.6 V with independent I/O supply
- Ultralow power consumption
- Normal mode with antialiasing filter: 6.1 µA (typ.)
- Ultralow-power mode: 0.47 µA (typ.)
- One-shot mode: 0.2 µA (typ.)
- Power-down: 0.02 µA (typ.)
- Low noise down to 181 µg/√Hz (typ.) at ±8 _g_ full scale
- ±2 _g_ /±4 _g_ /±8 _g_ /±16 _g_ full scales
- ODR from 1.6 Hz to 800 Hz
- Embedded temperature sensor
- Embedded FIFO: up to 512 samples of accelerometer and temperature data in high resolution or up to 768 samples of acceleration data at low resolution
## **Product status link**
MIS2DU12
- High-speed I²C/SPI/MIPI I3C[®] digital output interface
- Embedded digital functions (free-fall, wake-up, single/double-tap recognition, activity/inactivity, 6D/4D orientation)
- Self-test
|**Product summary**|**Product summary**|
|---|---|
|**Order code**|MIS2DU12TR|
|**Temperature**
**range [°C]**|-40 to +85|
|**Package**|LGA-12L|
|**Packing**|Tape and reel|
## **Product resources**
- Small package: 2.0 x 2.0 x 0.74 (max) mm LGA 12-lead
- 10000 _g_ high shock survivability
- • ECOPACK and RoHS compliant
## **Applications**
• Activity monitoring and posture detection for medical FDA Class III applications when used as a non-life-sustaining component
- Patient monitoring and man down
- Motion-activated functions
TN0018 (handling, mounting, and soldering guidelines)
- Pedometer
## **Description**
The MIS2DU12 is a linear 3-axis accelerometer with advanced digital functions whose MEMS and ASIC have been expressly designed to build an outstanding ultralow-power architecture in which the antialiasing filter operates with a power consumption among the lowest in the market.
The device has user-selectable full scales of ±2 _g_ /±4 _g_ /±8 _g_ /±16 _g_ and is capable of measuring accelerations with output data rates from 1.6 Hz to 800 Hz.
The MIS2DU12 has an integrated 128-level FIFO buffer allowing to store a wide range of data, reducing system power consumption.
The embedded self-test capability allows the user to check that the sensor works in the final application.
The device has a dedicated internal engine to process motion and acceleration detection including free-fall, wake-up, single/double-tap recognition, activity/inactivity, and 6D/4D orientation.
**DS15012** - **Rev 2** - **December 2025** For further information, contact your local STMicroelectronics sales office.
www.st.com
**MIS2DU12**
The MIS2DU12 is available in a small 2.0 x 2.0 mm plastic, land grid array (LGA) package only 0.74 mm thin, which places it among the smallest solution available in the market. It is guaranteed to operate over an extended temperature range from -40°C to + 85°C.
**DS15012** - **Rev 2**
**page 2/56**
**MIS2DU12 Block diagram and pin description**
## **1 Block diagram and pin description**
## **1.1 Block diagram**
**Figure 1. Block diagram**
**==> picture [377 x 194] intentionally omitted <==**
**----- Start of picture text -----**
CHARGE
AMPLIFIER
X+
X AAF
X-
Y+ I C2 CSSCL/SPC
a Y- Y AAF A/DCONVERTER CONTROL LOGIC SPI SDA/SDO/SDI
MIPI I3C [®] SDO/TA0
Z+
Z- Z AAF
TEMPERATURE SENSOR
SELF TEST REFERENCE TRIMMINGCIRCUITS CLOCK 128 LevelFIFO INTERRUPT GEN.CONTROL LOGIC& INT1INT2
**----- End of picture text -----**
**DS15012** - **Rev 2**
**page 3/56**
**MIS2DU12 Block diagram and pin description**
## **1.2 Pin description**
**Figure 2. Pin connections**
||||
|---|---|---|
|1
9
8
7
2
3
4
6
5
11
12
10
GND
RES
SCL/SPC
CS
SDO/TA0
SDA/SDI/SDO
NC
INT2
INT1
(TOPVIEW)
DIRECTION OF THE
DETECTABLE
ACCELERATIONS
Y
1
X
Z
VDD
(BOTTOM VIEW)
GND
VDDIO
**Table 1.Pin description**|||
|**Pin#**|**Name**|**Function**|
|1|SCL
SPC|I²C/MIPI I3C®serial clock (SCL)
SPI serial port clock (SPC)|
|2(1)|CS|SPI/I²C/MIPI I3C®mode selection
(1: SPI idle mode / I²C/MIPI I3C®enabled;
0: SPI enabled / I²C/MIPI I3C®disabled)|
|3(1)|SDO
TA0|SPI serial data output (SDO)
I²C less significant bit of the device address (TA0)|
|4|SDA
SDI
SDO|I²C/MIPI I3C®serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)|
|5|NC|Internally not connected. Can be tied to VDD, VDDIO, or GND.|
|6|GND|0 V supply|
|7|RES|Connect to GND|
|8|GND|0 V supply|
|9|VDD|Power supply|
|10|VDDIO|Power supply for I/O pins|
|11(2)|INT2|Interrupt pin 2. Clock input when selected in single data conversion on demand.|
|12(2)|INT1|Interrupt pin 1|
_1. CS and SDO/TA0 pins are internally pulled up. The pull-up of the CS pin can be disconnected by setting bit CS_PU_DIS of register IF_PU_CTRL (0Ch) to 1. The pull-up of the SDO pin can be disconnected by setting bit SDO_PU_DIS of register IF_PU_CTRL (0Ch) to 1._
_2. The INT1 and INT2 pins are internally pulled down. The internal pull-down of the INT1 pin can be disconnected by setting the PD_DIS_INT1 bit in IF_CTRL (0Eh) to 1. The internal pull-down of the INT2 pin can be disconnected by setting the PD_DIS_INT2 bit in MD2_CFG (20h) to 1._
**DS15012** - **Rev 2**
**page 4/56**
**MIS2DU12 Mechanical and electrical specifications**
## **2 Mechanical and electrical specifications**
## **2.1 Mechanical characteristics**
@ VDD = 1.8 V, T = 25°C unless otherwise noted.
The product is factory calibrated at 1.8 V. The operational power supply range is from 1.62 V to 3.6 V.
**Table 2. Mechanical characteristics**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.(1)**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|FS|Measurement range|||±2||_g_|
|||||±4|||
|||||±8|||
|||||±16|||
|LA_Cx|Linear acceleration cross-axis sensitivity||-2.5||+2.5|%|
|LA_ODR|Linear acceleration output data rate||-3||+3|%|
|So|Sensitivity|@ FS ±2_g_||0.976||m_g_/digit|
|||@ FS ±4_g_||1.952|||
|||@ FS ±8_g_||3.904|||
|||@ FS ±16_g_||7.808|||
|So%|Sensitivity tolerance|@ FS ±2_g_|-9||+9|%|
|An|Noise density - normal mode|FS = ±2_g_, ODR = 800 Hz, BW = ODR/2,
VDD = 1.8 V|||436|μ_g_/√Hz|
|TyOff|Zero-_g_level offset accuracy(2)||-160||+160|m_g_|
|TCO|Zero-_g_offset change vs. temperature|||±1||m_g_/°C|
|TCS|Sensitivity change vs. temperature|||±0.035||%/°C|
|ST|Self-test positive difference|X-axis|50||700|m_g_|
|||Y-axis|50||700||
|||Z-axis|200||1200||
_1. Typical specifications are not guaranteed._
_2. Values after factory calibration test and trimming._
**DS15012** - **Rev 2**
**page 5/56**
**MIS2DU12 Mechanical and electrical specifications**
## **2.2 Electrical characteristics**
@ VDD = 1.8 V, T = 25°C unless otherwise noted.
The product is factory calibrated at 1.8 V. The operational power supply range is from 1.62 V to 3.6 V.
**Table 3. Electrical characteristics**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ(1)**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VDD|Supply voltage||1.62|1.8|3.6|V|
|VDDIO|I/O pins supply voltage(2)||1.62||VDD + 0.1|V|
|IddNM|Supply current in normal mode with antialiasing
filter|FS = ±2_g_, ODR = 100 Hz, BW = ODR/2, VDD = 2.2 V|||5.6|µA|
|||FS = ±2_g_, ODR = 800 Hz, BW = ODR/2, VDD = 2.2 V|||9.2||
|||FS = ±2_g_, ODR = 200 Hz, BW = ODR/2, VDD = 2.2 V|||6.3||
|||FS = ±2_g_, ODR = 100 Hz, BW = ODR/2, VDD = 1.8 V|||5.2||
|||FS = ±2_g_, ODR = 200 Hz, BW = ODR/2, VDD = 1.8 V|||6.1||
|||FS = ±2_g_, ODR = 800 Hz, BW = ODR/2, VDD = 1.8 V|||8.6||
|IddULP|Supply current in ultralow-power mode|FS = ±8_g_, ODR = 1.6 Hz, BW = ODR/2||0.47||µA|
|Idd_PD|Supply current in power-down|VDD = 2.2 V|||100|nA|
|||VDD = 1.8 V|||100||
|VIH|Digital high-level input voltage||0.7*VDDIO|||V|
|VIL|Digital low-level input voltage||||0.3*VDDIO|V|
|VOH|Digital high-level output voltage|IOH= 4 mA(3)|VDDIO - 0.2|||V|
|VOL|Digital low-level output voltage|IOL= 4 mA(3)|||0.2|V|
_1. Typical specifications are not guaranteed._
_2. It is possible to remove VDD, maintaining VDDIO without blocking the communication busses. In this condition the measurement chain is powered off._
_3. 4 mA is the maximum driving capability, that is, the maximum DC current that can be sourced/sunk by the digital pin in order to guarantee the correct digital output voltage levels VOH and VOL._
## **2.3 Temperature sensor characteristics**
@ VDD = 1.8 V, T = 25°C unless otherwise noted.
**Table 4. Temperature sensor characteristics**
|**Symbol**|**Parameter**|**Min.**|**Typ.(1)**|**Max.**|**Unit**|
|---|---|---|---|---|---|
|Top|Operating temperature range|-40||+85|°C|
|Toff|Temperature offset(2)|-15||+15|°C|
|TSDr|Temperature sensor output change vs. temperature||0.045(3)||°C/LSB|
|TODR|Temperature refresh rate||ODR||Hz|
_1. Typical specifications are not guaranteed._
_2. The output of the temperature sensor is 0 LSB (typ.) at 25°C._
_3. 12-bit resolution._
**DS15012** - **Rev 2**
**page 6/56**
**MIS2DU12 Mechanical and electrical specifications**
## **2.4 Communication interface characteristics**
## **2.4.1 SPI - serial peripheral interface**
Subject to general operating conditions for VDD and Top.
**Table 5. SPI target timing values**
|**Smbol**|**Parameter**|**Value(1)**|**Value(1)**|**Unit**|
|---|---|---|---|---|
|**y**||**Min**|**Max**||
|tc(SPC)|SPI clock cycle|100||ns|
|fc(SPC)|SPI clock frequency||10|MHz|
|tsu(CS)|CS setup time|6||ns|
|th(CS)|CS hold time|40|||
|tsu(SI)|SDI input setup time|12|||
|th(SI)|SDI input hold time|15|||
|tv(SO)|SDO valid output time||50||
|th(SO)|SDO output hold time|9|||
|tdis(SO)|SDO output disable time||50||
_1. 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production._
**Figure 3. SPI target timing diagram**
**==> picture [385 x 148] intentionally omitted <==**
**----- Start of picture text -----**
CS
tsu(CS) tc(SPC) th(CS)
SPC
tsu(SI) th(SI)
SDI MSB IN LSB IN
tv(SO) th(SO) tdis(SO)
SDO MSB OUT LSB OUT
**----- End of picture text -----**
_Note: Measurement points are done at 0.3·VDDIO and 0.7·VDDIO for both input and output ports._
**DS15012** - **Rev 2**
**page 7/56**
**MIS2DU12 Mechanical and electrical specifications**
## **2.4.2 I²C - inter-IC control interface**
Subject to general operating conditions for VDD and Top.
## **Table 6. I²C target timing values**
|**Smbol**|**Parameter**|**I²C fast mode(1)(2)**|**I²C fast mode(1)(2)**|**I²C fast mode plus(1)(2)**|**I²C fast mode plus(1)(2)**|**Unit**|
|---|---|---|---|---|---|---|
|**y**||**Min**|**Max**|**Min**|**Max**||
|f(SCL)|SCL clock frequency|0|400|0|1000|kHz|
|tw(SCLL)|SCL clock low time|1.3||0.5||µs|
|tw(SCLH)|SCL clock high time|0.6||0.26|||
|tsu(SDA)|SDA setup time|100||50||ns|
|th(SDA)|SDA data hold time|0|0.9|0||µs|
|th(ST)|START/REPEATED START condition hold time|0.6||0.26|||
|tsu(SR)|REPEATED START condition setup time|0.6||0.26|||
|tsu(SP)|STOP condition setup time|0.6||0.26|||
|tw(SP:SR)|Bus free time between STOP and START condition|1.3||0.5|||
||Data valid time||0.9||0.45||
||Data valid acknowledge time||0.9||0.45||
|CB|Capacitive load for each bus line||400||550|pF|
_1. Data based on standard I²C protocol requirement, not tested in production._
_2. Data for I²C fast mode and I²C fast mode plus have been validated by characterization, not tested in production._
## **Figure 4. I²C target timing diagram**
**==> picture [391 x 150] intentionally omitted <==**
**----- Start of picture text -----**
REPEATED
START
START
tsu(SR)
SDA tw(SP:SR) START
tsu(SDA) th(SDA)
tsu(SP) STOP
SCL
th(ST) tw(SCLL) tw(SCLH)
**----- End of picture text -----**
_Note: Measurement points are done at 0.3·VDDIO and 0.7·VDDIO for both ports._
**DS15012** - **Rev 2**
**page 8/56**
**MIS2DU12 Mechanical and electrical specifications**
## **2.5 Absolute maximum ratings**
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
**Table 7. Absolute maximum ratings**
|**Symbol**
~~a~~|**Ratings**
~~ee~~|**Maximum value**
~~ee~~
~~ee~~|**Unit**
~~ee~~
e~~e~~|
|---|---|---|---|
|VDD|Supply voltage|-0.3 to +4.3
~~ee ~~|V
e~~e~~|
|VDDIO|I/O pins supply voltage|-0.3 to +4.3|V|
|Vin|Input voltage on any control pin
(CS, SCL/SPC, SDA/SDI/SDO, SDO/TA0)|-0.3 to VDDIO+0.3|V|
|AUNP|Acceleration (any axis, unpowered)|3000_g_for 0.5 ms|_g_|
|||10000_g_for 0.2 ms|_g_|
|TOP|Operating temperature range|-40 to +85|°C|
|TSTG|Storage temperature range|-40 to +125|°C|
|ESD|Electrostatic discharge protection|2 (HBM)|kV|
_Note:_
_Supply voltage on any pin should never exceed 4.3 V._
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.
**DS15012** - **Rev 2**
**page 9/56**
**MIS2DU12 Terminology and functionality**
## **3 Terminology and functionality**
## **3.1 Terminology**
## **3.1.1 Sensitivity**
Sensitivity describes the gain of the sensor and can be determined by applying 1 _g_ acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ±1 _g_ acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and time. The sensitivity tolerance describes the range of sensitivities of a large population of sensors.
## **3.1.2 Zero-** _**g**_ **level offset**
Zero- _g_ level offset describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface measures 0 _g_ on the X-axis and 0 _g_ on the Y-axis whereas the Z-axis measures 1 _g_ . The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as two’s complement number). A deviation from ideal value in this case is called zero- _g_ level offset. Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zero- _g_ level offset change vs. temperature”.
## **3.2 Functionality**
## **3.2.1 Operating modes**
The MIS2DU12 has three operating modes: normal, ultralow-power, and one-shot mode. In normal mode, an aggressive antialiasing filter is active regardless, but the overall supply current remains extraordinarily low (refer to Table 3).
## **3.2.2 Single data conversion on-demand modes**
The device features two single data conversion on-demand modes: one-shot triggered by the INT2 pin, and oneshot triggered by the I²C/SPI/I3C digital interface.
## **3.2.3 Self-test**
Self-test mode allows checking the sensor functionality without moving it, applying an actuation force to the sensor and simulating a definite input acceleration.
**DS15012** - **Rev 2**
**page 10/56**
**MIS2DU12 Terminology and functionality**
## **3.2.4**
## **Activity/inactivity, Android stationary/motion detection functions**
The activity/inactivity function recognizes the device’s sleep state and allows reducing system power consumption.
When the activity/inactivity function is activated by setting the SLEEP_ON bit in WAKE_UP_THS (1Ch), the device automatically goes to the inactivity output data rate selected by the INACT_ODR[1:0] bits in register CTRL4 (13h).
With this feature the system may be efficiently switched from low-power mode to full performance depending on user-selectable positioning and acceleration events, thus ensuring power saving and flexibility.
The Android stationary/motion detection function only recognizes the device’s sleep state.
When the Android stationary/motion detection function is activated by setting to a STATIONARY condition the INACT_ODR[1:0] bits in register CTRL4 (13h), the device detects acceleration below a fixed threshold but does not change the ODR after sleep state detection.
The activity/inactivity recognition and Android stationary/motion detection functions are activated by writing the desired threshold in the WAKE_UP_THS (1Ch) register. The high-pass filter is automatically enabled.
If the device is in sleep (inactivity/stationary) mode, when at least one of the axes exceeds the threshold in WAKE_UP_THS (1Ch), the device goes into a sleep-to-wake state (as wake-up).
For the activity/inactivity function, the device, in a wake-up state, returns to the ODR before sleep state detection.
Activity/inactivity, Android stationary/motion detection threshold and duration can be configured in the following control registers:
WAKE_UP_THS (1Ch)
WAKE_UP_DUR (1Dh)
## **3.2.5**
## **High tap/double-tap user configurability**
The device embeds the possibility to select the following parameters:
- single axis or multiple axes in TAP_THS_Z (1Ah)
- axis priority in TAP_THS_Y (19h)
- threshold value of each axis in TAP_THS_X (18h), TAP_THS_Y (19h), and TAP_THS_Z (1Ah)
- max time threshold between two consecutive taps for double-tap recognition, min time threshold between two consecutive taps to detect a new tap event in INT_DUR (1Bh)
## **3.2.6**
## **Interrupt event recognition**
The device may be configured to generate interrupt signals coming from an independent inertial wake-up/free-fall event or from the position of the device itself. Thresholds and timing of this interrupt generator are programmable by the end user in runtime.
Automatic programmable sleep-to-wake-up and return-to-sleep functions are also available for enhanced power saving.
The device interrupts signal can behave as:
- Free-fall: 3-axis subthreshold recognition;
- Wake-up: axis recognition;
- Wake-to-sleep: change of state recognition active-sleep (also known as activity-inactivity);
- 6D and 4D orientation detection: change of position recognition;
- Tap-tap: single, double, axis and sign recognition.
All these functions are parallel but during sleep it is not possible to recognize a tap-tap event. All these signals can be driven to the two interrupt pins (INT1 and INT2) through registers MD1_CFG (1Fh) and MD2_CFG (20h). All these functions are enabled by setting the INTERRUPTS_ENABLE bit in register INTERRUPT_CFG (17h) to 1.
It is possible to configure the duration of the interrupt using the LIR and INT_SHORT_EN bits in INTERRUPT_CFG (17h) as shown in the following table.
**DS15012** - **Rev 2**
**page 11/56**
**MIS2DU12 Terminology and functionality**
**Table 8. Configuration of duration of interrupt**
|**LIR**|**INT_SHORT_EN**|**Interrupt type**|
|---|---|---|
|0|0|Interrupt level mode|
|1|1|Interrupt latched mode|
- Interrupt level mode: the interrupt signal goes high when an interrupt event occurs and is reset when the acceleration data fall below the threshold.
- Interrupt latched mode: the interrupt signal is the OR between the interrupt flags that are monitored on the INT1/INT2 pins. The interrupt signal goes high when interrupt event occurs and is reset when ALL_INT_SRC (24h) is read. The status flags inside the interrupt source registers are coherent with the behavior of the INT1/INT2 pins. The interrupt generator block is inhibited for 1 ODR after the interrupt event.
## **3.3**
## **Sensing element**
A proprietary process is used to create a surface micromachined accelerometer. The technology allows processing suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. In order to be compatible with the traditional packaging techniques, a cap is placed on top of the sensing element to avoid blocking the moving parts during the molding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor.
At steady-state the nominal value of the capacitors are a few pF and when an acceleration is applied, the maximum variation of the capacitive load is in the fF range.
## **3.4**
## **IC interface**
The complete measurement chain is composed of a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage using an analog-to-digital converter.
The acceleration data may be accessed through an I²C/SPI/MIPI I3C[®] interface thus making the device particularly suitable for direct interfacing with a microcontroller.
The MIS2DU12 features a data-ready signal which indicates when a new set of measured acceleration data is available, thus simplifying data synchronization in the digital system that uses the device.
## **3.5**
## **Factory calibration**
The IC interface is factory-calibrated for sensitivity (So) and zero- _g_ level offset.
The trim values are stored inside the device in nonvolatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during active operation. This allows using the device without further calibration. If an accidental write occurs in the registers where the trimming parameters are stored, the BOOT bit in CTRL4 (13h) can help to retrieve the correct trimming parameters from nonvolatile memory without the need to switch on/off the device. This bit is automatically reset at the end of the download operation. Setting this bit has no impact on the control registers.
## **3.6**
## **Temperature sensor**
The temperature is available in OUT_T_L (2Eh), OUT_T_H (2Fh) stored as two's complement data, left-justified in 12-bit mode and duplicated in registers TEMP_OUT_L (30h) - TEMP_OUT_H (31h).
Refer to Table 4. Temperature sensor characteristics for the conversion factor.
**DS15012** - **Rev 2**
**page 12/56**
**MIS2DU12 Application hints**
**4 Application hints**
**Figure 5. MIS2DU12 electrical connections (top view)**
**==> picture [419 x 238] intentionally omitted <==**
**----- Start of picture text -----**
VDDIO
100nF
HOST
I [2] C /
GND MIPI I3C ® /
VDD SPI (3/4-w)
10µF MIS2DU12
SCL/SPC VDDIO
1 12 11 10
CS VDD
2 9 100nF
GND I [2] C configuration
SDO/TA0 GND
3 8 VDDIO
SDA/SDI/SDO
RES
4 5 6 7
Rpu Rpu
SCL
SDA
Pull-up to be added
Rpu=10kOhm
INT1 INT2
NC GND
**----- End of picture text -----**
The device core is supplied through the VDD line while the I/O pins are supplied through the VDDIO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF aluminum) should be placed as near as possible to pin 9 of the device (common design practice).
All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to Figure 5). It is possible to remove VDD while maintaining VDDIO without blocking the communication bus, in this condition the measurement chain is powered off.
The functionality of the device and the measured acceleration data are selectable and accessible through the I²C/ MIPI I3C[®] or SPI interfaces. When using the I²C, CS must be tied high (that is, connected to VDDIO).
The functions, the threshold and the timing of the two interrupt pins (INT1 and INT2) can be completely programmed by the user through the I²C/MIPI I3C[®] /SPI interface.
**DS15012** - **Rev 2**
**page 13/56**
**MIS2DU12 Application hints**
**Table 9. Internal pin status**
|**Pin #**|**Name**|**Function**|**Pin status**|
|---|---|---|---|
|1|SCL
SPC|I²C/MIPI I3C®serial clock (SCL)
SPI serial port clock (SPC)|Default: input without pull-up|
|2|CS|SPI/I²C/MIPI I3C®mode selection
1: SPI idle mode / I²C/MIPI I3C®enabled
0: SPI enabled / I²C/MIPI I3C®disabled|Default: input with internal pull-up|
|3|SDO
TA0|Serial data output (SDO)
I²C less significant bit of the device address (TA0)|Default: input with internal pull-up|
|4|SDA
SDI
SDO|I²C/MIPI I3C®serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)|Default: (SDA) input without pull-up|
|5|NC|Internally not connected. Can be tied to VDD, VDDIO, or GND.||
|6|GND|0 V supply||
|7|RES|Connect to GND||
|8|GND|0 V supply||
|9|VDD|Power supply||
|10|VDDIO|Power supply for I/O pins||
|11|INT2|Interrupt pin 2. Clock input when selected in single data conversion on demand.|Default: input with internal pull-down(1)(2)|
|12|INT1|Interrupt pin 1|Default: input with internal pull-down(3)|
_1. The INT2 pin is configured as "push-pull output forced to GND" as soon as it is configured with the interruption bits in the CTRL3 (12h) and MD2_CFG (20h) registers._
_2. In order to disable the internal pull-down on the INT2 pin, write 1 to the PD_DIS_INT2 bit in MD2_CFG (20h)._
_3. The INT1 pin is configured as "push-pull output forced to GND" as soon as it is configured with interruption bits in the CTRL2 (11h) and MD1_CFG (1Fh) registers. The internal pull-down can be disconnected by setting the PD_DIS_INT1 bit of register IF_CTRL (0Eh) to 1. When this is done, the INT1 pin needs to be externally biased. If INT1 = VDD, only the SPI and I3C interfaces are available. If INT1 = GND, then the I²C, I3C and SPI interfaces are active._
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**MIS2DU12 Digital main blocks**
## **5 Digital main blocks**
## **5.1**
## **FIFO**
The MIS2DU12 embeds 128 slots of 12-bit FIFO data for each of the three output channels X, Y and Z of acceleration data and 12-bit FIFO data for temperature data. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO.
In order to maximize the amount of data collected in FIFO, it is possible to double the slots of FIFO data (from 128 to 256) by writing the FIFO_DEPTH bit in FIFO_CTRL (15h) with 2X depth mode.
When this mode is enabled, the most significant 8 bits for each acceleration axis are stored in FIFO. Each FIFO data word contains data of two consecutive ODRs, the actual and the previous one. The temperature data is no longer stored in FIFO but is available in the TEMP_OUT_L (30h) and TEMP_OUT_H (31h) registers.
In high-resolution batch mode, accelerometer and temperature FIFO are stored in FIFO as 12 bits at ODR.
In 2X depth batch mode, each word contains two accelerometer data as 8 bits in FIFO at ODR/2. The FIFO buffer can work according to six different modes:
- Bypass mode
- FIFO mode
- Continuous mode
- Continuous-to-FIFO mode
- Bypass-to-continuous
- Bypass-to-FIFO
Each mode is selected by the FIFO_MODE[2:0] bits in the FIFO_CTRL (15h) register. A programmable FIFO watermark is selected in the FIFO_WTM (16h) register.
FIFO status is available in the FIFO_STATUS1 (26h) and FIFO_STATUS2 (27h) registers and can be used to generate dedicated interrupts on the INT1 and INT2 pins using the CTRL2 (11h) and CTRL3 (12h) registers.
The FTH bit in FIFO_STATUS1 (26h) register goes to 1 when the number of unread samples is greater than or equal to FTH[6:0] in FIFO_WTM (16h). If FTH[6:0] is equal to 0, the FTH bit in FIFO_STATUS1 (26h) goes to 0.
The FIFO_OVR bit in FIFO_STATUS1 (26h) is equal to 1 if a FIFO sample is overwritten.
FSS[7:0] in FIFO_STATUS2 (27h) contains stored data levels of unread samples.
When FSS[7:0] is equal to 00000000, FIFO is empty. When FSS[7:0] is equal to 10000000, FIFO is full and the unread samples are 128.
## **5.1.1**
## **Bypass mode**
In bypass mode FIFO_CTRL (15h) (FIFO_MODE[2:0] = 000), the FIFO is not operational, no data is collected in FIFO memory, and it remains empty with only the actual sample available in the output registers. Bypass mode is also used to reset the FIFO when in FIFO mode.
For each channel only the first address is used. When new data is available, the old data is overwritten.
## **5.1.2 FIFO mode**
In FIFO mode FIFO_CTRL (15h) (FIFO_MODE[2:0] = 001) data from the output channels are stored in the FIFO memory until it is full. When 128 unread samples are stored in memory, data collecting is stopped.
To reset FIFO content, bypass mode should be selected by writing FIFO_CTRL (15h) (FIFO_MODE[2:0]) to 000. After this reset command, it is possible to restart FIFO mode, writing FIFO_CTRL (15h) (FIFO_MODE[2:0]) to 001.
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**MIS2DU12 Digital main blocks**
**5.1.3 Continuous mode** Continuous mode FIFO_CTRL (15h) (FIFO_MODE[2:0] = 110) provides a continuous FIFO update: when 128 unread samples are stored in memory, as new data arrives, the oldest data is discarded and overwritten by the newer.
A FIFO threshold flag FIFO_FTH bit in FIFO_STATUS1 (26h) is asserted when the number of unread samples in FIFO is greater than or equal to FTH[6:0] in FIFO_WTM (16h).
It is possible to route the FTH bit to the INT1 pin by writing the INT1_F_FTH bit to 1 in register CTRL2 (11h) or to the INT2 pin by writing the INT2_F_FTH bit to 1 in register CTRL3 (12h).
If an overrun occurs, the oldest sample in FIFO is overwritten and the FIFO_OVR flag in FIFO_STATUS1 (26h) is asserted.
**5.1.4 Continuous-to-FIFO mode** In continuous-to-FIFO mode FIFO_MODE[2:0] = 011 in the FIFO_CTRL (15h) register, FIFO operates in continuous mode and FIFO mode starts upon an edge trigger event. When the FIFO is full, data collecting is stopped. The trigger event could be single or double-tap, wake-up, free-fall, 6D interrupt or any combination of these events, but every interrupt has to be routed to the corresponding pin to be used as a trigger.
## **5.1.5**
## **Bypass-to-continuous mode**
In bypass-to-continuous mode FIFO_CTRL (15h) (FIFO_MODE[2:0] = 100), data measurement storage inside FIFO starts in continuous mode upon an edge trigger event.
The trigger event could be single or double-tap, wake-up, free-fall, 6D interrupt, or any combination of these events, but every interrupt has to be routed to the corresponding pin to be used as a trigger. The sample that generated the trigger is available in FIFO.
**5.1.6 Bypass-to-FIFO** In bypass-to-FIFO mode FIFO_CTRL (15h)(FIFO_MODE_[2:0] = 111), data measurement storage inside FIFO operates in FIFO mode when selected triggers are equal to 1, otherwise FIFO content is reset (bypass mode). The trigger event could be single or double-tap, wake-up, free-fall, 6D interrupt, or any combination of these events, but every interrupt has to be routed to the corresponding pin to be used as a trigger. The sample that generated the trigger is available in FIFO.
## **5.1.7**
## **Output data read sequence from FIFO**
Automatic address increment is provided to minimize interface transfer.
In high-resolution batching mode, if both the accelerometer and temperature data are read from FIFO, a read operation is automatically performed from 8 output registers for every FIFO word (OUT_X_L (28h) - OUT_T_H (2Fh)). If only accelerometer data are read from FIFO, a read operation is automatically performed from 6 output registers for every FIFO word, skipping temperature data (OUT_X_L (28h) – OUT_Z_H (2Dh)). The ROUNDING_XYZ bit in the FIFO_CTRL (15h) register must be written to enable this rounding of the read address.
In 2X depth mode, all FIFO words can be read in a single interface transfer from 6 output registers (OUT_X_L (28h) – OUT_Z_H (2Dh)). In this case, the rounding of the read address is automatically enabled.
If the IF_ADD_INC bit of register CTRL1 (10h) is set to 1, all FIFO words can be read in a single interface transfer. Different read modes using a single interface transfer supported by the MIS2DU12 are:
- FIFO_STATUS_2 register + N* FIFO_WORDS
- FIFO_STATUS_1 register + FIFO_STATUS_2 register + N* FIFO_WORDS
- TEMP_OUT + FIFO_STATUS_1 register + FIFO_STATUS_2 register + N* FIFO_WORDS
**DS15012** - **Rev 2**
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**MIS2DU12 Digital main blocks**
## **5.1.8 FIFO empty condition**
When FIFO is emptied, a special value is used in order to recognize an empty condition and no duplicated samples are read.
In high-resolution batch mode, the least significant 4 bits of data read during an empty condition are 1111.
In 2X depth mode the empty condition corresponds to 7Fh code. The accelerometer data are assigned to 7Eh in order to discriminate the empty condition.
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**MIS2DU12 Digital interfaces**
## **6 Digital interfaces**
The registers embedded inside the MIS2DU12 may be accessed through both the I²C, MIPI I3C[®] and SPI serial interfaces. The latter may be software configured to operate either in 3-wire or 4-wire interface mode.
The serial interfaces are mapped to the same pins. To select/exploit the I²C/MIPI I3C[®] interface, the CS line must be tied high (that is, connected to VDDIO).
**Table 10. Serial interface pin description**
|**Pin name**|**Pin description**|
|---|---|
|CS|SPI/I²C/MIPI I3C®mode selection
1: SPI idle mode / I²C/MIPI I3C®enabled
0: SPI enabled / I²C/MIPI I3C®disabled|
|SCL
SPC|I²C/MIPI I3C®serial clock (SCL)
SPI serial port clock (SPC)|
|SDA
SDI
SDO|I²C/MIPI I3C®serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)|
|TA0
SDO|I²C address selection (TA0)
SPI serial data output (SDO)|
## **6.1**
## **I²C serial interface**
The MIS2DU12 I²C is a bus target. The I²C is employed to write data into registers whose content can also be read back.
The relevant I²C terminology is given in the table below.
## **Table 11. I²C terminology**
|**Term**|**Description**|
|---|---|
|Transmitter|The device that sends data to the bus|
|Receiver|The device that receives data from the bus|
|Controller|The device that initiates a transfer, generates clock signals, and terminates a transfer|
|Target|The device addressed by the controller|
There are two signals associated with the I²C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both lines must be connected to VDDIO through an external pull-up resistor. When the bus is free, both the lines are high.
The I²C interface supports fast mode (400 kHz) I²C standards as well as fast mode plus (1000 kHz).
In order to disable the I²C block, IF_CTRL (0Eh) (I2C_DISABLE) = 1 must be set.
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**MIS2DU12 Digital interfaces**
## **6.1.1 I²C operation**
The transaction on the bus is started through a start (ST) signal. A start condition is defined as a high to low transition on the data line while the SCL line is held high. After this has been transmitted by the controller, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the target in the first 7 bits and the eighth bit tells whether the controller is receiving data from the target or transmitting data to the target. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the controller.
The target address (TAD) associated to the MIS2DU12 is 001100xb where the x bit is modified by the TA0/SDO pin in order to modify the device address. If the TA0/SDO pin is connected to the supply voltage, the address is 0011001b, otherwise if the TA0/SDO pin is connected to ground, the address is 0011000b. This solution permits to connect and address two different accelerometers to the same I²C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.
The I²C embedded inside the MIS2DU12 behaves like a target device and the following protocol must be adhered to. After the start condition (ST), a target address is sent. Once a target acknowledge (TAK) has been returned, an 8-bit subaddress (SUB) is transmitted. The 7 LSb represents the actual register address while the CTRL1 (10h) (IF_ADD_INC) bit defines the address increment.
The target address is completed with a read/write bit. If the bit is 1 (read), a repeated start (SR) condition must be issued after the two subaddress bytes. If the bit is 0 (write) the controller transmits to the target with direction unchanged. Table 12 explains how the TAD+read/write bit pattern is composed, listing all the possible configurations.
**Table 12. TAD+read/write patterns**
|**Command**|**TAD[6:1]**|**TAD[0] = TA0**|**R/W**|**TAD+R/W**|
|---|---|---|---|---|
|Read|001100|0|1|00110001 (31h)|
|Write|001100|0|0|00110000 (30h)|
|Read|001100|1|1|00110011 (33h)|
|Write|001100|1|0|00110010 (32h)|
**Table 13. Transfer when controller is writing one byte to target**
|Controller|ST|TAD+W||SUB||DATA||SP|
|---|---|---|---|---|---|---|---|---|
|Target|||TAK||TAK||TAK||
## **Table 14. Transfer when controller is writing multiple bytes to target**
|Controller|Controller|ST|ST|TAD+W|TAD+W|||SUB|SUB|||DATA|DATA|||DATA|DATA|||SP|SP|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Target||||||TAK||||TAK||||TAK||||TAK||||
|**Table 15.Transfer when controller is receiving (reading) one byte of data from target**||||||||||||||||||||||
|Controller|ST||TAD+W||||SUB||||SR||TAD+R||||||NCAK||SP|
|Target|||||TAK||||TAK||||||TAK||DATA|||||
**Table 16. Transfer when controller is receiving (reading) multiple bytes of data from target**
|Controller|ST|TAD+W||SUB||SR|TAD+R|||CAK||CAK||NCAK|SP|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Target|||TAK||TAK|||TAK|DATA||DATA||DATA|||
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**MIS2DU12 Digital interfaces**
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit (MSb) first. If a target receiver doesn’t acknowledge the target address (that is, it is not able to receive because it is performing some real-time function) the data line must be left high by the target. The controller can then abort the transfer. A low to high transition on the SDA line while the SCL line is high is defined as a stop condition. Each data transfer must be terminated by the generation of a stop (SP) condition.
In the presented communication format, CAK is controller acknowledge and NCAK is no controller acknowledge.
## **6.2 SPI bus interface**
The MIS2DU12 SPI is a bus target. The SPI allows writing to and reading from the registers of the device. The serial interface interacts with the application using four wires: **CS** , **SPC** , **SDI** and **SDO** .
**Figure 6. Read and write protocol**
**==> picture [327 x 103] intentionally omitted <==**
**----- Start of picture text -----**
CS
SPC
SDI
RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
**----- End of picture text -----**
**CS** enables the serial port and it is controlled by the SPI controller. It goes low at the start of the transmission and goes back high at the end. **SPC** is the serial port clock and it is controlled by the SPI controller. It is stopped high when **CS** is high (no transmission). **SDI** and **SDO** are respectively the serial port data input and output. Those lines are driven at the falling edge of **SPC** and should be captured at the rising edge of **SPC** .
Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of **SPC** . The first bit (bit 0) starts at the first falling edge of **SPC** after the falling edge of **CS** while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of **CS** .
**bit 0** : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In the latter case, the chip drives SDO at the start of bit 8.
**bit 1-7** : address AD(6:0). This is the address field of the indexed register.
**bit 8-15** : data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
**bit 8-15** : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands additional blocks of 8 clock periods are added. When the CTRL1 (10h) (IF_ADD_INC) bit is 0, the address used to read/write data remains the same for every block. When the CTRL1 (10h) (IF_ADD_INC) bit is 1, the address used to read/write data is increased at every block.
The function and the behavior of **SDI** and **SDO** remain unchanged.
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**MIS2DU12 Digital interfaces**
## **6.2.1 SPI read**
**Figure 7. SPI read protocol**
**==> picture [355 x 112] intentionally omitted <==**
**----- Start of picture text -----**
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
**----- End of picture text -----**
The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.
**bit 0** : READ bit. The value is 1.
**bit 1-7** : address AD(6:0). This is the address field of the indexed register.
**bit 8-15** : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
**bit 16-...** : data DO(...-8). Additional data in multiple byte reads.
**Figure 8. Multiple byte SPI read protocol (2-byte example)**
**==> picture [351 x 95] intentionally omitted <==**
**----- Start of picture text -----**
CS
SPC
SDI
RW
AD6 AD5 AD4AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11DO10 DO9 DO8
**----- End of picture text -----**
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**MIS2DU12 Digital interfaces**
## **6.2.2 SPI write**
## **Figure 9. SPI write protocol**
**==> picture [364 x 80] intentionally omitted <==**
**----- Start of picture text -----**
CS
SPC
SDI
RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
AD6 AD5 AD4 AD3 AD2 AD1 AD0
**----- End of picture text -----**
The SPI write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.
**bit 0** : WRITE bit. The value is 0.
**bit 1-7** : address AD(6:0). This is the address field of the indexed register.
**bit 8-15** : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first). **bit 16-...** : data DI(...-8). Additional data in multiple byte writes.
**Figure 10. Multiple byte SPI write protocol (2-byte example)**
**==> picture [374 x 82] intentionally omitted <==**
**----- Start of picture text -----**
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
**----- End of picture text -----**
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**MIS2DU12 Digital interfaces**
## **6.2.3 SPI read in 3-wire mode**
- 3-wire mode is entered by setting the CTRL1 (10h) (SIM) bit equal to 1 (SPI serial interface mode selection).
## **Figure 11. SPI read protocol in 3-wire mode**
**==> picture [354 x 79] intentionally omitted <==**
**----- Start of picture text -----**
CS
SPC
SDI/O
RW DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
AD6 AD5 AD4 AD3 AD2 AD1 AD0
**----- End of picture text -----**
The SPI read command is performed with 16 clock pulses: **bit 0** : READ bit. The value is 1.
**bit 1-7** : address AD(6:0). This is the address field of the indexed register.
**bit 8-15** : data DO(7:0) (read mode). This is the data that is read from the device (MSb first). A multiple read command is also available in 3-wire mode.
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**MIS2DU12 Digital interfaces**
## **6.3 MIPI I3C[®] interface**
## **6.3.1 MIPI I3C[®] target interface**
The MIS2DU12 interface includes an MIPI I3C[®] SDR only target interface able to work up to 8 MHz of the SCL frequency (compliant with release 1.0 of the specification) with MIPI I3C[®] SDR embedded features:
- CCC command
- Direct CCC communication (SET and GET)
- Broadcast CCC communication
- Private communications
- Private read and write for single byte
- Multiple read and write
- In-band interrupt request
Refer to Section 6.4: I²C/I3C coexistence in MIS2DU12 for details concerning the choice of the interface when powering up the device.
**DS15012** - **Rev 2**
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**MIS2DU12 Digital interfaces**
## **6.3.2 MIPI I3C[®] CCC supported commands**
The list of MIPI I3C[®] CCC commands supported by the device is detailed in the following table.
**Table 17. MIPI I3C[®] CCC commands**
|**Command**|**Command code**|**Default**|**Description**|
|---|---|---|---|
|SETDASA|0x87||Assign dynamic address using static address.
Static address values are: 0x18/0x19 depending on SDO pin if I2C_SA1 bit in
registerIF_CTRL (0Eh)is equal to 0.|
|ENEC|0x80 / 0x00||Target activity control (direct and broadcast)|
|DISEC|0x81/ 0x01||Target activity control (direct and broadcast)|
|ENTAS0|0x82 / 0x02||Enter activity state (direct and broadcast)|
|ENTAS1|0x83 / 0x03||Enter activity state (direct and broadcast)|
|ENTAS2|0x84 / 0x04||Enter activity state (direct and broadcast)|
|ENTAS3|0x85 / 0x05||Enter activity state (direct and broadcast)|
|RSTDAA|0x86 / 0x06||Reset the assigned dynamic address (direct and broadcast)|
|SETMWL|0x89 / 0x08||Define maximum write length during private write (direct and broadcast)|
|SETMRL|0x8A / 0x09||Define maximum read length during private read (direct and broadcast)|
|SETNEWDA|0x88||Change dynamic address|
|GETMWL|0x8B|0x00
0x08
(2 byte)|Get maximum write length during private write|
|GETMRL|0x8C|0x00
0x10
0x04
(3 byte)|Get maximum read length during private read|
|GETPID|0x8D|0x02
0x08
0x00
0x45
0x10
0x0B|Device ID register|
|GETBCR|0x8E|0x07
(1 byte)|Bus characteristics register|
|GETDCR|0x8F|0x41 default|MIPI I3C®device characteristics register|
|GETSTATUS|0x90|0x00
0x00
(2 byte)|Status register|
|GETMXDS|0x94|0x01
0x39
(2 byte)|Return max data speed|
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**page 25/56**
**MIS2DU12 Digital interfaces**
## **6.4 I²C/I3C coexistence in MIS2DU12**
In the MIS2DU12, the SDA and SCL lines are common to both I²C and I3C. The I²C bus requires antispike filters on the SDA and SCL pins that are not compatible with I3C timing.
The device can be connected to both I²C and I3C or only to the I3C bus depending on the connection of the INT1 pin when the device is powered up:
- INT1 pin floating (internal pull-down): I²C/I3C both active, see Figure 12
- INT1 pin connected to VDDIO: only I3C active, see Figure 13
**Figure 12. I²C and I3C both active (INT1 pin not connected)**
**==> picture [371 x 214] intentionally omitted <==**
**----- Start of picture text -----**
INT1 pin not connected
I²C/I3C both active
I²C/I3C
(both active)
I²C bus case I3C bus case
Controller sends Controller resets
Controller assigns DA
I²C R/W DA
to the target [(1)]
Target performs
I3C private R/W with and without 7Eh
requested R/W
CCC commands
Target event management
Error detection and recovery
**----- End of picture text -----**
_1. Address assignment (SETDASA) must be performed with I²C fast mode plus timing. When the target is addressed, the I²C target is disabled and the timing is compatible with I3C specifications._
**Figure 13. Only I3C active (INT1 pin connected to VDDIO)**
**==> picture [387 x 167] intentionally omitted <==**
**----- Start of picture text -----**
INT1 pin connected to VDDIO I²C/I3C I3C bus case
Only I3C active
Dynamic
Controller resets
Address
DA
Assignment (1)
I3C private R/W with and without 7Eh
CCC commands
Target event management
Error detection and recovery
**----- End of picture text -----**
_1. When the target is I3C only, the I²C target is always disabled. The address can be assigned using I3C SDR timing._
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**MIS2DU12 Register mapping**
## **7 Register mapping**
The table given below provides a list of the 8-bit registers embedded in the device and the corresponding addresses.
**Table 18. Register map**
|**Name**|**T(1)**|**Register address**|**Register address**|**Defalt**|**Comment**|
|---|---|---|---|---|---|
||**ype**|**Hex**|**Binary**|**u**||
|IF_PU_CTRL|R/W|0C|00001100|00000000||
|IF_CTRL|R/W|0E|00001110|00000000||
|CTRL1|R/W|10|00010000|00000000||
|CTRL2|R/W|11|00010001|00000000||
|CTRL3|R/W|12|00010010|00000000||
|CTRL4|R/W|13|00010011|00000000||
|CTRL5|R/W|14|00010100|00000000||
|FIFO_CTRL|R/W|15|00010101|00000000||
|FIFO_WTM|R/W|16|00010110|00000000||
|INTERRUPT_CFG|R/W|17|00010111|00000000||
|TAP_THS_X|R/W|18|00011000|00000000||
|TAP_THS_Y|R/W|19|00011001|00000000||
|TAP_THS_Z|R/W|1A|00011010|00000000||
|INT_DUR|R/W|1B|00011011|00000000||
|WAKE_UP_THS|R/W|1C|00011100|00000000||
|WAKE_UP_DUR|R/W|1D|00011101|00000000||
|FREE_FALL|R/W|1E|00011110|00000000||
|MD1_CFG|R/W|1F|00011111|00000000||
|MD2_CFG|R/W|20|00100000|00000000||
|WAKE_UP_SRC|R|21|00100001|00000000||
|TAP_SRC|R|22|00100010|00000000||
|SIXD_SRC|R|23|00100011|00000000||
|ALL_INT_SRC|R|24|00100100|00000000||
|STATUS|R|25|00100101|00000000||
|FIFO_STATUS1|R|26|00100110|00000000||
|FIFO_STATUS2|R|27|00100111|00000000||
|OUT_X_L|R|28|00101000|00000000||
|OUT_X_H|R|29|00101001|00000000||
|OUT_Y_L|R|2A|00101010|00000000||
|OUT_Y_H|R|2B|00101011|00000000||
|OUT_Z_L|R|2C|00101100|00000000||
|OUT_Z_H|R|2D|00101101|00000000||
|OUT_T_L|R|2E|00101110|00000000||
|OUT_T_H|R|2F|00101111|00000000||
|TEMP_OUT_L|R|30|00110000|00000000||
**DS15012** - **Rev 2**
**page 27/56**
**MIS2DU12 Register mapping**
|**Name**|**T(1)**|**Register address**|**Register address**|**Defalt**|**Comment**|
|---|---|---|---|---|---|
||**ype**|**Hex**|**Binary**|**u**||
|TEMP_OUT_H|R|31|00110001|00000000||
|WHO_AM_I|R|43|01000011|01000101||
|ST_SIGN|R/W|58|01011000|110XXXXX||
_1. R = read-only register, R/W = readable/writable register_
Reserved registers must not be changed. Writing to those registers may cause permanent damage to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
**DS15012** - **Rev 2**
**page 28/56**
**MIS2DU12 Register description**
## **8 Register description**
## **8.1 IF_PU_CTRL (0Ch)**
R/W
This register contains bits to control the pull-ups of SDO, SDA and CS, modifying a default state.
## **Table 19. IF_PU_CTRL register**
|SDO_PU
_DIS|SDA_PU_EN|0(1)|0(1)|0(1)|CS_PU_DIS|0(1)|0(1)|
|---|---|---|---|---|---|---|---|
_1. This bit must be set to 0 for the correct operation of the device._
## **Table 20. IF_PU_CTRL register description**
||**Table 20.IF_PU_CTRL register description**|
|---|---|
|SDO_PU_DIS|If 1, disconnects the internal pull-up of the SDO pin.|
|SDA_PU_EN|If 1, connects the internal pull-up of the SDA pin.|
|CS_PU_DIS|If 1, disconnects the internal pull-up of the CS pin.|
## **8.2 IF_CTRL (0Eh)**
R/W
## **Table 21. IF_CTRL register**
|0(1)|0(1)|0(1)|0(1)|0(1)|PD_DIS
_INT1|I3C_
DISABLE|I2C_
DISABLE|
|---|---|---|---|---|---|---|---|
_1. This bit must be set to 0 for the correct operation of the device._
## **Table 22. IF_CTRL register description**
||**Table 22.IF_CTRL register description**|
|---|---|
|PD_DIS_INT1|If 1, pull-down of INT1 is disabled.|
|I3C_DISABLE|If 1, MIPI I3C®interface is disabled.|
|I2C_DISABLE|If 1, I²C interface is disabled.|
**DS15012** - **Rev 2**
**page 29/56**
**MIS2DU12 Register description**
## **8.3 CTRL1 (10h)**
R/W
## **Table 23. CTRL1 register**
|PP_OD|SIM|SW_
RESET|IF_ADD_
INC|DRDY_
PULSED|WU_X_EN|WU_Y_EN|WU_Z_EN|
|---|---|---|---|---|---|---|---|
## **Table 24. CTRL1 register description**
|PP_OD|Push-pull/open-drain mode for INT pins
(0: INT pins in push-pull mode (default);
1: INT pins in open-drain mode)|
|---|---|
|SIM|SPI 3 or 4-wire mode
(0: 4-wire SPI (default); 1: 3-wire SPI)|
|SW_RESET|Software reset, resets all CTRL registers to their default values. The software reset procedure has to be
executed with the accelerometer in power-down mode.|
|IF_ADD_INC|Register address is automatically incremented during a multiple-byte access with a serial interface.
(0: disabled (default);
1: enabled)|
|DRDY_PULSED|Enables pulsed data-ready mode
(0: data-ready latched mode (returns to 0 only after reading over an interface) (default);
1: data-ready pulsed mode (the data-ready pulses are typ. 90 µs long))|
|WU_X_EN|Enables wake-up event detection status on X-axis. Default value: 0 (0: disabled; 1: enabled)|
|WU_Y_EN|Enables wake-up event detection status on Y-axis. Default value: 0 (0: disabled; 1: enabled)|
|WU_Z_EN|Enables wake-up event detection status on Z-axis. Default value: 0 (0: disabled; 1: enabled)|
## **8.4 CTRL2 (11h)**
R/W
## **Table 25. CTRL2 register**
|INT1_
BOOT|INT1_F_
FULL|INT1_F_
FTH|INT1_F_
OVR|INT1_
DRDY|0(1)|0(1)|0(1)|
|---|---|---|---|---|---|---|---|
_1. This bit must be set to 0 for the correct operation of the device._
## **Table 26. CTRL2 register description**
|INT1_BOOT|Enables boot status on INT1 pin. Default value: 0 (0: disabled; 1: enabled)|
|---|---|
|INT1_F_FULL|Enables FIFO full on INT1 pin. Default value: 0 (0: disabled; 1: enabled)|
|INT1_F_FTH|Enables FIFO threshold interrupt on INT1 pin. Default value: 0 (0: disabled; 1: enabled)|
|INT1_F_OVR|Enables overrun interrupt on INT1 pin. Default value: 0 (0: disabled; 1: enabled)|
|INT1_DRDY|Enables data-ready interrupt on INT1 pin. Default value: 0 (0: disabled; 1: enabled)|
**DS15012** - **Rev 2**
**page 30/56**
**MIS2DU12 Register description**
## **8.5 CTRL3 (12h)**
R/W
## **Table 27. CTRL3 register**
|INT2_
BOOT|INT2_F_
FULL|INT2_F_
FTH|INT2_F_
OVR|INT2_
DRDY|0(1)|ST1|ST0|
|---|---|---|---|---|---|---|---|
_1. This bit must be set to 0 for the correct operation of the device._
## **Table 28. CTRL3 register description**
||**Table 28.CTRL3 register description**|
|---|---|
|INT2_BOOT|Enables boot status on INT2 pin. Default value: 0 (0: disabled; 1: enabled)|
|INT2_F_FULL|Enables FIFO full on INT2 pin. Default value: 0 (0: disabled; 1: enabled)|
|INT2_F_FTH|Enables FIFO threshold interrupt on INT2 pin. Default value: 0 (0: disabled; 1: enabled)|
|INT2_F_OVR|Enables overrun interrupt on INT2 pin. Default value: 0 (0: disabled; 1: enabled)|
|INT2_DRDY|Enables data-ready interrupt on INT2 pin. Default value: 0 (0: disabled; 1: enabled)|
|ST[1:0]|These bits enable data acquisition during the self-test procedure.|
## **8.6 CTRL4 (13h)**
R/W
## **Table 29. CTRL4 register**
|INACT_
ODR1|INACT_
ODR0|BDU|0(1)|0(1)|0(1)|SOC|BOOT|
|---|---|---|---|---|---|---|---|
_1. This bit must be set to 0 for the correct operation of the device._
## **Table 30. CTRL4 register description**
|INACT_ODR[1:0]|If the activity/inactivity function is enabled, then these bits select the accelerometer ODR during inactivity
status, seeTable 31.|
|---|---|
|BDU|Sensing chain block data update
(0: output registers MSByte and LSByte independent continuous update (default);
1: output registers are not updated until MSByte and LSByte have both been read)|
|SOC|Start of conversion bit. When one-shot mode is enabled, this bit provides the start for the measurement.
This bit is automatically cleared.|
|BOOT|Reboots memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
This bit is automatically cleared.|
## **Table 31. ODR frequency in inactivity state**
|**INACT_ODR1**|**INACT_ODR0**|**Frequency [Hz]**|
|---|---|---|
|0|0|Stationary/motion detection:
when selected, no ODR change is done if inactivity condition is detected|
|0|1|1.6|
|1|0|3|
|1|1|6|
**DS15012** - **Rev 2**
**page 31/56**
**MIS2DU12 Register description**
## **8.7 CTRL5 (14h)**
R/W
## **Table 32. CTRL5 register**
ODR3 ODR2 ODR1 ODR0 BW1 BW0 FS1 FS0
## **Table 33. CTRL5 register description**
||**Table 33.CTRL5 register description**|
|---|---|
|ODR[3:0]|ODR selection, seeTable 34.|
|BW[1:0]|Selects the device bandwidth which is dependent on the ODR selected. The available bandwidths are ODR/2,
ODR/4, ODR/8, and ODR/16 for ODR ≥ 50 Hz as shown inTable 35. For ODR < 50 Hz, refer toTable 36.|
|FS[1:0]|Sets the full scale, seeTable 37.|
**Table 34. Operating modes**
|**ODR[3:0]**|**Operating mode**|
|---|---|
|0000|Power-down|
|0001|1.6 Hz in ultralow-power mode|
|0010|3 Hz in ultralow-power mode|
|0011|6 Hz in ultralow-power mode|
|0100|6 Hz in normal mode|
|0101|12.5 Hz in normal mode|
|0110|25 Hz in normal mode|
|0111|50 Hz in normal mode|
|1000|100 Hz in normal mode|
|1001|200 Hz in normal mode|
|1010|400 Hz in normal mode|
|1011|800 Hz in normal mode|
|1110|One-shot using the INT2 pin|
|1111|One-shot using the interface|
**DS15012** - **Rev 2**
**page 32/56**
**MIS2DU12 Register description**
**Table 35. Bandwidth selection (ODR ≥ 50 Hz)**
|**ODR [Hz]**|**BW[1:0]**|**BW [Hz]**|**Settling time**
**[samples to be discarded]**|
|---|---|---|---|
|50|00|25|1|
||01|12.5|2|
||10|6|6|
||11|3|14|
|100|00|50|1|
||01|25|2|
||10|12.5|6|
||11|6|14|
|200|00|100|0|
||01|50|2|
||10|25|4|
||11|12.5|14|
|400|00|200|0|
||01|100|0|
||10|50|4|
||11|25|8|
|800|00|400|0|
||01|200|0|
||10|100|0|
||11|50|1|
**Table 36. Bandwidth selection (ODR < 50 Hz)**
|**ODR [Hz]**|**BW[1:0]**|**BW [Hz]**|**Settling time**
**[samples to be discarded]**|
|---|---|---|---|
|6|00|-||
||01|-||
||10|-||
||11|3|11|
|12.5|00|-||
||01|-||
||10|6|5|
||11|3|11|
|25|00|-||
||01|12.5|1|
||10|6|5|
||11|3|11|
**DS15012** - **Rev 2**
**page 33/56**
**MIS2DU12 Register description**
## **Table 37. Full-scale selection**
|**FS1**|**FS0**|**Full scale**|
|---|---|---|
|0|0|±2_g_|
|0|1|±4_g_|
|1|0|±8_g_|
|1|1|±16_g_|
## **8.8 FIFO_CTRL (15h)**
R/W
|ROUNDING
_XYZ|FIFO_
DEPTH|0(1)|0(1)|STOP_ON
_FTH|FIFO_MODE2|FIFO_MODE1|FIFO_MODE0|
|---|---|---|---|---|---|---|---|
_1. This bit must be set to 0 for the correct operation of the device._
## **Table 38. FIFO_CTRL register description**
||**Table 38.FIFO_CTRL register description**|
|---|---|
|ROUNDING_XYZ|This function is used to auto address the correct registers for a circular continuous read fromOUT_X_L
(28h)toOUT_Z_H (2Dh).|
|FIFO_DEPTH|If 1, enables 2X FIFO.|
|STOP_ON_FTH|Sensing chain FIFO stop values memorization at threshold level.
(0: FIFO depth is not limited (default);
1: FIFO depth is limited to threshold level)|
|FIFO_MODE[2:0]|Different FIFO modes are enabled as shown inTable 39.|
**Table 39. Selection of FIFO mode**
|**FIFO_MODE2 **|**FIFO_MODE1 **|**FIFO_MODE0**|**Mode**|
|---|---|---|---|
|0|0|0|Bypass mode|
|0|0|1|FIFO mode: stops collecting data when FIFO is full|
|0|1|0|Reserved|
|0|1|1|Continuous-to-FIFO: stream mode until trigger is deasserted, then FIFO
mode|
|1|0|0|Bypass-to-continuous: bypass mode until trigger is deasserted, then
continuous mode|
|1|0|1|Reserved|
|1|1|0|Continuous mode: if the FIFO is full, the new sample overwrites the older
sample.|
|1|1|1|Bypass-to-FIFO: bypass mode until trigger is deasserted, then FIFO mode|
**DS15012** - **Rev 2**
**page 34/56**
**MIS2DU12 Register description**
## **8.9 FIFO_WTM (16h)**
R/W
## **Table 40. FIFO_WTM register**
- FTH6 FTH5 FTH4 FTH3 FTH2 FTH1 FTH0
## **Table 41. FIFO_WTM register description**
FTH[6:0] FIFO watermark threshold, maximum value is 127.
## **8.10 INTERRUPT_CFG (17h)**
R/W
## **Table 42. INTERRUPT_CFG register**
|-|INT_
SHORT_EN|WAKE_
THS_W|-|SLEEP_
STATUS_ON
_INT|H_
LACTIVE|LIR|INTERRUPTS
_ENABLE|
|---|---|---|---|---|---|---|---|
## **Table 43. INTERRUPT_CFG register description**
||**Table 43.INTERRUPT_CFG register description**|
|---|---|
|INT_SHORT_EN|In combination with the LIR bit, this bit allows selecting the desired interruption configuration (see
Table 8).|
|WAKE_THS_W|Weight of 1 LSB of wake-up threshold. Default value: 0
(0: 1 LSB = FS_XL / (26);
1: 1 LSB = FS_XL / (28) )|
|SLEEP_STATUS_ON_INT|Sends the sleep status instead of sleep change to INT pins
(only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits are enabled, respectively in
registersMD1_CFG (1Fh)andMD2_CFG (20h)).|
|H_LACTIVE|Interrupt active level
(0: interrupts active-high (default);
1: Interrupts active-low)|
|LIR|In combination with the INT_SHORT_EN bit, this bit allows selecting the desired interrupt
configuration (seeTable 8).|
|INTERRUPTS_ ENABLE|Enables basic interrupts (6D/4D, free-fall, wake-up, single/double tap, activity/inactivity).
Default value: 0
(0: interrupt disabled; 1: interrupt enabled)|
**DS15012** - **Rev 2**
**page 35/56**
**MIS2DU12 Register description**
## **8.11 TAP_THS_X (18h)**
R/W
## **Table 44. TAP_THS_X register**
D4D_EN D6D_THS1 D6D_THS0 TAP_THS_X_4 TAP_THS_X_3 TAP_THS_X_2 TAP_THS_X_1 TAP_THS_X_0
## **Table 45. TAP_THS_X register description**
||**Table 45.TAP_THS_X register description**|
|---|---|
|D4D_EN|Portrait/landscape position detection and face-up/down position enabled (4D orientation)|
|D6D_THS[1:0]|Thresholds for D4D/D6D function
(00: 80 degrees;
01: 70 degrees;
10: 60 degrees;
11: 50 degrees)|
|TAP_THS_X_[4:0]|X-axis recognition threshold. 1 LSB: FS / (25). Default value: 0|
## **8.12 TAP_THS_Y (19h)**
R/W
## **Table 46. TAP_THS_Y register**
|TAP_
PRIORITY_2|TAP_
PRIORITY_1|TAP_
PRIORITY_0|TAP_THS_Y_4|TAP_THS_Y_3|TAP_THS_Y_2|TAP_THS_Y_1|TAP_THS_Y_0|
|---|---|---|---|---|---|---|---|
## **Table 47. TAP_THS_Y register description**
||**Table 47.TAP_THS_Y register description**|
|---|---|
|TAP_PRIORITY_[2:0]|Selection of axis priority for TAP detection (seeTable 48)|
|TAP_THS_Y_[4:0]|Y-axis recognition threshold. 1 LSB: FS / (25). Default value: 0|
## **Table 48. Selection of axis priority for tap detection**
|**TAP_PRIORITY_[2:0]**|**Max priority**|**Mid priority**|**Min priority**|
|---|---|---|---|
|000|X|Y|Z|
|001|Y|X|Z|
|010|X|Z|Y|
|011|Z|Y|X|
|100|X|Y|Z|
|101|Y|Z|X|
|110|Z|X|Y|
|111|Z|Y|X|
**DS15012** - **Rev 2**
**page 36/56**
**MIS2DU12 Register description**
## **8.13 TAP_THS_Z (1Ah)**
R/W
|**Table 49.TAP_THS_Z register**|**Table 49.TAP_THS_Z register**|**Table 49.TAP_THS_Z register**|**Table 49.TAP_THS_Z register**|**Table 49.TAP_THS_Z register**|**Table 49.TAP_THS_Z register**|**Table 49.TAP_THS_Z register**|**Table 49.TAP_THS_Z register**|
|---|---|---|---|---|---|---|---|
|TAP_X_EN|TAP_Y_EN|TAP_Z_EN|TAP_THS_Z_4|TAP_THS_Z_3|TAP_THS_Z_2|TAP_THS_Z_1|TAP_THS_Z_0|
## **Table 50. TAP_THS_Z register description**
||**Table 50.TAP_THS_Z register description**|
|---|---|
|TAP_{X,Y,Z}_EN|Enables tap recognition in {X,Y,Z} direction|
|TAP_THS_Z_[4:0]|Z-axis recognition threshold. 1 LSB: FS / (25). Default value: 0|
**8.14 INT_DUR (1Bh)**
R/W
|**Table 51. INT_DUR register**|**Table 51. INT_DUR register**|**Table 51. INT_DUR register**|**Table 51. INT_DUR register**|**Table 51. INT_DUR register**|**Table 51. INT_DUR register**|**Table 51. INT_DUR register**|**Table 51. INT_DUR register**|
|---|---|---|---|---|---|---|---|
|LATENCY3|LATENCY2|LATENCY1|LATENCY0|QUIET1|QUIET0|SHOCK1|SHOCK0|
**Table 52. INT_DUR register description**
||**Table 52.INT_DUR register description**|
|---|---|
|LATENCY[3:0]|Maximum time gap for double-tap recognition duration. Default value: 0000 which corresponds to 16
ODR_time
Maximum time between two subsequent detected taps to determine a double-tap event (when double-tap
recognition is enabled).
1 LSB: 32 ODR_time.|
|QUIET[1:0]|Expected quiet time after a tap detection. Default value: 00 which corresponds to 2 ODR_time
Time after the first detected tap in which there must not be an overthreshold event.
1 LSB : 4 ODR_time.|
|SHOCK[1:0]|Maximum overthreshold event. Default value: 00 which corresponds to 4 ODR_time
Maximum time for an overthreshold signal detection to be recognized as a tap event.
1 LSB : 8 ODR_time.|
**DS15012** - **Rev 2**
**page 37/56**
**MIS2DU12 Register description**
## **8.15 WAKE_UP_THS (1Ch)**
R/W
## **Table 53. WAKE_UP_THS register**
|SINGLE_
DOUBLE_TAP|SLEEP_
ON|WK_THS5|WK_THS4|WK_THS3|WK_THS2|WK_THS1|WK_THS0|
|---|---|---|---|---|---|---|---|
## **Table 54. WAKE_UP_THS register description**
||**Table 54.WAKE_UP_THS register description**|
|---|---|
|SINGLE_DOUBLE_TAP|Enables single/double-tap event. Default value: 0
(0: only single-tap event enabled;
1: both single and double-tap events enabled)|
|SLEEP_ON|If 1, activity/inactivity function is enabled.|
|WK_THS[5:0]|Threshold for wake-up: 1 LSB weight depends on WAKE_THS_W inINTERRUPT_CFG (17h).
Default value: 000000|
## **8.16 WAKE_UP_DUR (1Dh)**
R/W
## **Table 55. WAKE_UP_DUR register**
|FF_DUR5|WAKE_
DUR1|WAKE_
DUR0|0(1)|SLEEP_
DUR3|SLEEP_
DUR2|SLEEP_
DUR1|SLEEP_
DUR0|
|---|---|---|---|---|---|---|---|
_1. This bit must be set to 0 for the correct operation of the device._
## **Table 56. WAKE_UP_DUR register description**
||**Table 56.WAKE_UP_DUR register description**|
|---|---|
|FF_DUR5|Free-fall duration. Default value: 0
In conjunction with FF_DUR[4:0] inFREE_FALL (1Eh).
1 LSB: 1 ODR_time|
|WAKE_DUR[1:0]|Wake-up duration. Default value: 00
When the WU_DUR_X4 bit in registerMD1_CFG (1Fh)is set to 0, 1 LSB of WAKE_DUR = 1 ODR_time,
otherwise the following durations are selectable:
(00: 3 ODR_time;
01: 7 ODR_time;
10: 11 ODR_time;
11: 15 ODR_time)|
|SLEEP_DUR[3:0]|Duration to go in sleep mode. Default value: 0000 which corresponds to 16 ODR_time
1 LSB: 512 ODR_time|
**DS15012** - **Rev 2**
**page 38/56**
**MIS2DU12 Register description**
## **8.17 FREE_FALL (1Eh)**
R/W
## **Table 57. FREE_FALL register**
FF_DUR4 FF_DUR3 FF_DUR2 FF_DUR1 FF_DUR0 FF_THS2 FF_THS1 FF_THS0
## **Table 58. FREE_FALL register description**
||**Table 58.FREE_FALL register description**|
|---|---|
|FF_DUR[4:0]|Free-fall duration. Default value: 0
In conjunction with FF_DUR5 inWAKE_UP_DUR (1Dh)
1 LSB: 1 ODR_time|
|FF_THS[2:0]|Free-fall threshold
(000: 156 m_g_;
001: 219 m_g_;
010: 250 m_g_;
011: 312 m_g_;
100: 344 m_g_;
101: 406 m_g_;
110: 469 m_g_;
111: 500 m_g_)|
## **8.18 MD1_CFG (1Fh)**
## R/W
Each bit in this register enables a signal to be carried over INT1; the pin's output is the OR combination of the signals selected here and in register CTRL2 (11h).
## **Table 59. MD1_CFG register**
|INT1_ SLEEP
CHANGE|INT1_
SINGLE_TAP|INT1_WU|INT1_FF|INT1_
DOUBLE_TAP|INT1_6D|WU_DUR_X4|-|
|---|---|---|---|---|---|---|---|
## **Table 60. MD1_CFG register description**
||**Table 60.MD1_CFG register description**|
|---|---|
|INT1_SLEEP_CHANGE|Enables sleep change (or sleep status, depending on SLEEP_STATUS_ON_INT bit) on the INT1
pin. Default value: 0 (0: disabled; 1: enabled)|
|INT1_SINGLE_TAP|Enables routing single-tap event to the INT1 pin. Default value: 0 (0: disabled; 1: enabled)|
|INT1_WU|Enables routing wake-up event to the INT1 pin. Default value: 0 (0: disabled; 1: enabled)|
|INT1_FF|Enables routing free-fall event to the INT1 pin. Default value: 0 (0: disabled; 1: enabled)|
|INT1_DOUBLE_TAP|Enables routing double-tap event to the INT1 pin. Default value: 0 (0: disabled; 1: enabled)|
|INT1_6D|Enables routing 6D recognition event to the INT1 pin. Default value: 0 (0: disabled; 1: enabled)|
|WU_DUR_X4|This bit is used to select the resolution of the WAKE_DUR[1:0] bits in registerWAKE_UP_DUR
(1Dh). Default value: 0|
**DS15012** - **Rev 2**
**page 39/56**
**MIS2DU12 Register description**
## **8.19 MD2_CFG (20h)**
R/W
Each bit in this register enables a signal to be carried over INT2; the pin's output is the OR combination of the signals selected here and in register CTRL3 (12h).
## **Table 61. MD2_CFG register**
|INT2_ SLEEP
CHANGE|INT2_
SINGLE_TAP|INT2_WU|INT2_FF|INT2_
DOUBLE_TAP|INT2_6D|PD_DIS
_INT2|-|
|---|---|---|---|---|---|---|---|
## **Table 62. MD2_CFG register description**
||**Table 62.MD2_CFG register description**|
|---|---|
|INT2_SLEEP_CHANGE|Enables sleep change (or sleep status, depending on SLEEP_STATUS_ON_INT bit) on the INT2
pin. Default value: 0 (0: disabled; 1: enabled)|
|INT2_SINGLE_TAP|Enables routing single-tap event to the INT2 pin. Default value: 0 (0: disabled; 1: enabled)|
|INT2_WU|Enables routing wake-up event to the INT2 pin. Default value: 0 (0: disabled; 1: enabled)|
|INT2_FF|Enables routing free-fall event to the INT2 pin. Default value: 0 (0: disabled; 1: enabled)|
|INT2_DOUBLE_TAP|Enables routing the double-tap event to the INT2 pin. Default value: 0 (0: disabled; 1: enabled)|
|INT2_6D|Enables routing 6D recognition event to the INT2 pin. Default value: 0 (0: disabled; 1: enabled)|
|PD_DIS_INT2|If 1, disables pull-down of INT2 pin.|
## **8.20 WAKE_UP_SRC (21h)**
R
## **Table 63. WAKE_UP_SRC register**
|-|SLEEP_
CHANGE_IA|FF_IA|SLEEP_
STATE|WU_IA|X_WU|Y_WU|Z_WU|
|---|---|---|---|---|---|---|---|
## **Table 64. WAKE_UP_SRC register description**
Detection of change in activity/inactivity status. Default value: 0 SLEEP_CHANGE_IA (0: change status not detected; 1: change status detected) Free-fall event detection status. Default value: 0 FF_IA (0: free-fall event not detected; 1: free-fall event detected) Sleep status bit. Default value: 0 SLEEP_STATE (0: activity status; 1: inactivity status) Wake-up event detection status. Default value: 0 WU_IA (0: wake-up event not detected; 1: wake-up event detected) Wake-up event detection status on X-axis. Default value: 0 X_WU (0: wake-up event on X-axis not detected; 1: wake-up event on X-axis detected) Wake-up event detection status on Y-axis. Default value: 0 Y_WU (0: wake-up event on Y-axis not detected; 1: wake-up event on Y-axis detected) Wake-up event detection status on Z-axis. Default value: 0 Z_WU (0: wake-up event on Z-axis not detected; 1: wake-up event on Z-axis detected)
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**MIS2DU12 Register description**
## **8.21 TAP_SRC (22h)**
R
## **Table 65. TAP_SRC register**
|-|TAP_IA|SINGLE_
TAP_IA|DOUBLE_
TAP_IA|TAP_SIGN|X_TAP|Y_TAP|Z_TAP|
|---|---|---|---|---|---|---|---|
## **Table 66. TAP_SRC register description**
||**Table 66.TAP_SRC register description**|
|---|---|
|TAP_IA|Tap event detection status. Default: 0
(0: tap event not detected; 1: tap event detected)|
|SINGLE_TAP_IA|Single-tap event status. Default value: 0
(0: single-tap event not detected; 1: single-tap event detected)|
|DOUBLE_TAP_IA|Double-tap event detection status. Default value: 0
(0: double-tap event not detected; 1: double-tap event detected)|
|TAP_SIGN|Sign of acceleration detected by tap event. Default: 0
(0: positive sign of acceleration detected by tap event;
1: negative sign of acceleration detected by tap event)|
|X_TAP|Tap event detection status on X-axis. Default value: 0
(0: tap event on X-axis not detected; 1: tap event on X-axis detected)|
|Y_TAP|Tap event detection status on Y-axis. Default value: 0
(0: tap event on Y-axis not detected; 1: tap event on Y-axis detected)|
|Z_TAP|Tap event detection status on Z-axis. Default value: 0
(0: tap event on Z-axis not detected; 1: tap event on Z-axis detected)|
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**MIS2DU12 Register description**
## **8.22 SIXD_SRC (23h)**
R
|**Table 67.SIXD_SRC register**|**Table 67.SIXD_SRC register**|**Table 67.SIXD_SRC register**|**Table 67.SIXD_SRC register**|**Table 67.SIXD_SRC register**|**Table 67.SIXD_SRC register**|**Table 67.SIXD_SRC register**|**Table 67.SIXD_SRC register**|
|---|---|---|---|---|---|---|---|
||D6D_IA|ZH|ZL|YH|YL|XH|XL|
|**Table 68.SIXD_SRC register description**||||||||
|D6D_IA|Source of change in 6D/4D orientation. Default value: 0
(0: change orientation not detected; 1: change orientation detected)|||||||
|ZH|Z-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over threshold) detected)|||||||
|ZL|Z-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)|||||||
|YH|Y-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over-threshold) detected)|||||||
|YL|Y-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)|||||||
|XH|X-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over threshold) detected)|||||||
|XL|X-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)|||||||
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**MIS2DU12 Register description**
## **8.23 ALL_INT_SRC (24h)**
R
## **Table 69. ALL_INT_SRC register**
|-|INT_
GLOBAL|SLEEP_CHANGE
_IA_ALL|D6D_
IA_ALL|DOUBLE_
TAP_ALL|SINGLE_
TAP_ALL|WU_IA_
ALL|FF_IA_
ALL|
|---|---|---|---|---|---|---|---|
## **Table 70. ALL_INT_SRC register description**
||**Table 70.ALL_INT_SRC register description**|
|---|---|
|INT_GLOBAL|This bit is 1 if one of the following events occur:
•
detection of change in activity/inactivity status
•
source of change in 6D/4D orientation
•
double-tap event status
•
single-tap event status
•
wake-up event detection status
•
free-fall event detection status
•
sleep event status|
|SLEEP_CHANGE_IA_ALL|Detection of change in activity/inactivity status. Default value: 0
(0: change in status not detected; 1: change in status detected)|
|D6D_IA_ALL|Source of change in 6D/4D orientation. Default value: 0
(0: change in orientation not detected; 1: change in orientation detected)|
|DOUBLE_TAP_ALL|Double-tap event status. Default value: 0
(0: event not detected, 1: event detected)|
|SINGLE_TAP_ALL|Single-tap event status. Default value: 0
(0: event not detected, 1: event detected)|
|WU_IA_ALL|Wake-up event status. Default value: 0
(0: event not detected, 1: event detected)|
|FF_IA_ALL|Free-fall event status. Default value: 0
(0: event not detected, 1: event detected)|
## **8.24 STATUS (25h)**
R
## **Table 71. STATUS register**
|-|-|-|-|-|-|PD_
STATUS|DRDY|
|---|---|---|---|---|---|---|---|
## **Table 72. STATUS register description**
PD_STATUS Monitors power-down. This bit is 1 when new accelerometer data is available and until the MSB of one of the output registers has DRDY been read.
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**MIS2DU12 Register description**
## **8.25 FIFO_STATUS1 (26h)**
R
## **Table 73. FIFO_STATUS1 register**
|FTH|FIFO_OVR|-|-|-|-|-|-|
|---|---|---|---|---|---|---|---|
|**Table 74.FIFO_STATUS1 register description**||||||||
|FTH|FIFO watermark status. The watermark is set through bits FTH[6:0] inFIFO_WTM (16h).
(0: FIFO filling is lower than WTM;
1: FIFO filling is equal to or higher than WTM)|||||||
|FIFO_OVR|FIFO overrun status: equal to 1 if FIFO has overwritten data.|||||||
## **8.26 FIFO_STATUS2 (27h)**
R
## **Table 75. FIFO_STATUS2 register**
|FSS7|FSS6|FSS6|FSS5|FSS4|FSS3|FSS2|FSS1|FSS0|
|---|---|---|---|---|---|---|---|---|
|**Table 76.FIFO_STATUS2 register description**|||||||||
|FSS[7:0]||Number of unread data stored in FIFO|||||||
## **8.27 OUT_X_L (28h)**
R
## **Table 77. OUT_X_L register**
|OUTX7|OUTX6|OUTX5|OUTX4|OUTX3|OUTX2|OUTX1|OUTX0|
|---|---|---|---|---|---|---|---|
|**Table 78.OUT_X_L register description**||||||||
|OUTX[7:0]|LSBs of X data output. The last four bits are always zero since the data is 12-bit.|||||||
## **8.28 OUT_X_H (29h)**
R
## **Table 79. OUT_X_H register**
|OUTX15|OUTX14|OUTX13|OUTX13|OUTX12|OUTX11|OUTX10|OUTX9|OUTX8|
|---|---|---|---|---|---|---|---|---|
|**Table 80.OUT_X_H register description**|||||||||
|OUTX[15:8]|||MSBs of X data output||||||
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**MIS2DU12 Register description**
## **8.29 OUT_Y_L (2Ah)** R
|**Table 81.OUT_Y_L register**|**Table 81.OUT_Y_L register**|**Table 81.OUT_Y_L register**|**Table 81.OUT_Y_L register**|**Table 81.OUT_Y_L register**|**Table 81.OUT_Y_L register**|**Table 81.OUT_Y_L register**|**Table 81.OUT_Y_L register**|
|---|---|---|---|---|---|---|---|
|OUTY7|OUTY6|OUTY5|OUTY4|OUTY3|OUTY2|OUTY1|OUTY0|
|**Table 82.OUT_Y_L register description**||||||||
|OUTY[7:0]|LSBs of Y data output. The last four bits are always zero since the data is 12-bit.|||||||
|**8.30**
**8.31**
**8.32**|**OUT_Y_H (2Bh)**
R
**Table 83.OUT_Y_H register**|**OUT_Y_H (2Bh)**
R
**Table 83.OUT_Y_H register**|**OUT_Y_H (2Bh)**
R
**Table 83.OUT_Y_H register**|**OUT_Y_H (2Bh)**
R
**Table 83.OUT_Y_H register**|**OUT_Y_H (2Bh)**
R
**Table 83.OUT_Y_H register**|**OUT_Y_H (2Bh)**
R
**Table 83.OUT_Y_H register**|**OUT_Y_H (2Bh)**
R
**Table 83.OUT_Y_H register**|**OUT_Y_H (2Bh)**
R
**Table 83.OUT_Y_H register**|**OUT_Y_H (2Bh)**
R
**Table 83.OUT_Y_H register**|
|---|---|---|---|---|---|---|---|---|---|
||OUTY15|OUTY14|OUTY13||OUTY12|OUTY11|OUTY10|OUTY9|OUTY8|
||**Table 84.OUT_Y_H register description**|||||||||
||OUTY[15:8]|||MSBs of Y data output.||||||
||**OUT_Z_L (2Ch)**
R
**Table 85.OUT_Z_L register**|||||||||
||OUTZ7|OUTZ6|OUTZ5||OUTZ4|OUTZ3|OUTZ2|OUTZ1|OUTZ0|
||**Table 86.OUT_Z_L register description**|||||||||
||OUTZ[7:0]|LSBs of Z data output. The last four bits are always zero since the data is 12-bit.||||||||
||**OUT_Z_H (2Dh)**
R|||||||||
## **Table 87. OUT_Z_H register**
|OUTZ15|OUTZ14|OUTZ13|OUTZ13|OUTZ12|OUTZ11|OUTZ10|OUTZ9|OUTZ8|
|---|---|---|---|---|---|---|---|---|
|**Table 88.OUT_Z_H register description**|||||||||
|OUTZ[15:8]|||MSBs of Z data output||||||
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**MIS2DU12 Register description**
|**8.33**
**8.34**
**8.35**
**8.36**|**OUT_T_L (2Eh)**
R
**Table 89.OUT_T_L register**|**OUT_T_L (2Eh)**
R
**Table 89.OUT_T_L register**|**OUT_T_L (2Eh)**
R
**Table 89.OUT_T_L register**|**OUT_T_L (2Eh)**
R
**Table 89.OUT_T_L register**|**OUT_T_L (2Eh)**
R
**Table 89.OUT_T_L register**|**OUT_T_L (2Eh)**
R
**Table 89.OUT_T_L register**|**OUT_T_L (2Eh)**
R
**Table 89.OUT_T_L register**|**OUT_T_L (2Eh)**
R
**Table 89.OUT_T_L register**|**OUT_T_L (2Eh)**
R
**Table 89.OUT_T_L register**|**OUT_T_L (2Eh)**
R
**Table 89.OUT_T_L register**|
|---|---|---|---|---|---|---|---|---|---|---|
||OUTT7||OUTT6|OUTT5||OUTT4|OUTT3|OUTT2|OUTT1|OUTT0|
||**Table 90.OUT_T_L register description**||||||||||
||OUTT[7:0]|LSBs of temperature data output. The last four bits are always zero since the data is 12-bit.|||||||||
||**OUT_T_H (2Fh)**
R
**Table 91.OUT_T_H register**||||||||||
||OUTT15||OUTT14|OUTT13||OUTT12|OUTT11|OUTT10|OUTT9|OUTT8|
||**Table 92.OUT_T_H register description**||||||||||
||OUTT[15:8]||||MSBs of temperature data output||||||
||**TEMP_OUT_L (30h)**
R
**Table 93.TEMP_OUT_L register**||||||||||
||OUTT7||OUTT6|OUTT5||OUTT4|OUTT3|OUTT2|OUTT1|OUTT0|
||**Table 94.TEMP_OUT_L register description**||||||||||
||OUTT[7:0]|LSBs of temperature data output. The last four bits are always zero since the data is 12-bit.|||||||||
||**TEMP_OUT_H (31h)**
R||||||||||
## **Table 95. TEMP_OUT_H register**
|OUTT15|OUTT14|OUTT13|OUTT13|OUTT12|OUTT11|OUTT10|OUTT9|OUTT8|
|---|---|---|---|---|---|---|---|---|
|**Table 96.TEMP_OUT_H register description**|||||||||
|OUTT[15:8]|||MSBs of temperature data output||||||
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**MIS2DU12 Register description**
## **8.37 WHO_AM_I (43h)**
This register is a read-only register. Its value is fixed at 45h.
## **Table 97. WHO_AM_I register default values**
0 1 0 0 0 1 0 1
## **8.38 ST_SIGN (58h)**
R/W
## **Table 98. ST_SIGN register**
STSIGN2 STSIGN1 STSIGN0 Reserved[(1)] Reserved[(1)] Reserved[(1)] Reserved[(1)] Reserved[(1)]
_1. Bits marked as Reserved must not be changed._
## **Table 99. ST_SIGN register description**
These bits set the sign of the self-test procedure. STSIGN[2:0] (110: positive sign (default); 001: negative sign)
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**MIS2DU12 Package information**
## **9 Package information**
To meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions, and product status are available at: www.st.com. ECOPACK is an ST trademark.
## **9.1 Soldering information**
The LGA package is compliant with the ECOPACK and RoHS standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
For the land pattern and soldering recommendations, consult technical note TN0018 available on www.st.com.
## **9.2 LGA-12L package information**
## **Figure 14. LGA-12L 2.0 x 2.0 x 0.74 mm package outline and mechanical data**
**==> picture [128 x 117] intentionally omitted <==**
**==> picture [120 x 123] intentionally omitted <==**
Dimensions are in millimeter unless otherwise specified. General Tolerance is +/-0.1mm unless otherwise specified.
## OUTER DIMENSIONS
|ITEM|DIMENSION [mm]|TOLERANCE [mm]|
|---|---|---|
|]
L
[
h
t
g
n
e
L|2|1
.
0
±|
|]
W
[
h
t
di
W|2|1
.
0
±|
|]
H
[ t
h
gie
H|X
A
M
4
7
.
0|/|
DM00794797_1
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**MIS2DU12 Package information**
## **Revision history**
## **Table 100. Document revision history**
|**Date**|**Version**|**Changes**|
|---|---|---|
|03-Jul-2025|1|Initial release|
|03-Dec-2025|2|First public release|
**DS15012** - **Rev 2**
**page 49/56**
**MIS2DU12 Contents**
|**Contents**|**Contents**||
|---|---|---|
|**1**|**Block**|**diagram and pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3**|
||**1.1**|Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3|
||**1.2**|Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
|**2**|**Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5**||
||**2.1**|Mechanical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
||**2.2**|Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
||**2.3**|Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
||**2.4**|Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|||**2.4.1**
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|||**2.4.2**
I²C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
||**2.5**|Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
|**3**|**Terminology and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10**||
||**3.1**|Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10|
|||**3.1.1**
Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10|
|||**3.1.2**
Zero-_g_level offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10|
||**3.2**|Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10|
|||**3.2.1**
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10|
|||**3.2.2**
Single data conversion on-demand modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10|
|||**3.2.3**
Self-test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10|
|||**3.2.4**
Activity/inactivity, Android stationary/motion detection functions . . . . . . . . . . . . . . . . . . . . 11|
|||**3.2.5**
High tap/double-tap user configurability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
|||**3.2.6**
Interrupt event recognition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
||**3.3**|Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12|
||**3.4**|IC interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12|
||**3.5**|Factory calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12|
||**3.6**|Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12|
|**4**|**Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13**||
|**5**|**Digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15**||
||**5.1**|FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15|
|||**5.1.1**
Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|||**5.1.2**
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|||**5.1.3**
Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
|||**5.1.4**
Continuous-to-FIFO mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
|||**5.1.5**
Bypass-to-continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
|||**5.1.6**
Bypass-to-FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
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**MIS2DU12 Contents**
|||**5.1.7**
Output data read sequence from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
|---|---|---|
|||**5.1.8**
FIFO empty condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17|
|**6**|**Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18**||
||**6.1**|I²C serial interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18|
|||**6.1.1**
I²C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
||**6.2**|SPI bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20|
|||**6.2.1**
SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21|
|||**6.2.2**
SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22|
|||**6.2.3**
SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
||**6.3**|MIPI I3C®interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24|
|||**6.3.1**
MIPI I3C®target interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|||**6.3.2**
MIPI I3C®CCC supported commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
||**6.4**|I²C/I3C coexistence in MIS2DU12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26|
|**7**|**Register mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27**||
|**8**|**Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29**||
||**8.1**|IF_PU_CTRL (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29|
||**8.2**|IF_CTRL (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29|
||**8.3**|CTRL1 (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30|
||**8.4**|CTRL2 (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30|
||**8.5**|CTRL3 (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31|
||**8.6**|CTRL4 (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31|
||**8.7**|CTRL5 (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32|
||**8.8**|FIFO_CTRL (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34|
||**8.9**|FIFO_WTM (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35|
||**8.10**|INTERRUPT_CFG (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35|
||**8.11**|TAP_THS_X (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36|
||**8.12**|TAP_THS_Y (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36|
||**8.13**|TAP_THS_Z (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37|
||**8.14**|INT_DUR (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37|
||**8.15**|WAKE_UP_THS (1Ch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38|
||**8.16**|WAKE_UP_DUR (1Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38|
||**8.17**|FREE_FALL (1Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39|
||**8.18**|MD1_CFG (1Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39|
||**8.19**|MD2_CFG (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40|
||**8.20**|WAKE_UP_SRC (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40|
||**8.21**|TAP_SRC (22h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41|
**DS15012** - **Rev 2**
**page 51/56**
**MIS2DU12 Contents**
||**8.22**|SIXD_SRC (23h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42|
|---|---|---|
||**8.23**|ALL_INT_SRC (24h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43|
||**8.24**|STATUS (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43|
||**8.25**|FIFO_STATUS1 (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44|
||**8.26**|FIFO_STATUS2 (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44|
||**8.27**|OUT_X_L (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44|
||**8.28**|OUT_X_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44|
||**8.29**|OUT_Y_L (2Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45|
||**8.30**|OUT_Y_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45|
||**8.31**|OUT_Z_L (2Ch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45|
||**8.32**|OUT_Z_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45|
||**8.33**|OUT_T_L (2Eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46|
||**8.34**|OUT_T_H (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46|
||**8.35**|TEMP_OUT_L (30h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46|
||**8.36**|TEMP_OUT_H (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46|
||**8.37**|WHO_AM_I (43h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47|
||**8.38**|ST_SIGN (58h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47|
|**9**|**Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48**||
||**9.1**|Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48|
||**9.2**|LGA-12L package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48|
|**Revision**||**history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49**|
|**List**|**of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53**||
|**List**|**of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55**||
**DS15012** - **Rev 2**
**page 52/56**
**MIS2DU12 List of tables**
## **List of tables**
|**Table**|**1.**|Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
|---|---|---|
|**Table**|**2.**|Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
|**Table**|**3.**|Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**Table**|**4.**|Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**Table**|**5.**|SPI target timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|**Table**|**6.**|I²C target timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|**Table**|**7.**|Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
|**Table**|**8.**|Configuration of duration of interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|**Table**|**9.**|Internal pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|**Table**|**10.**|Serial interface pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|**Table**|**11.**|I²C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|**Table**|**12.**|TAD+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|**Table**|**13.**|Transfer when controller is writing one byte to target. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|**Table**|**14.**|Transfer when controller is writing multiple bytes to target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|**Table**|**15.**|Transfer when controller is receiving (reading) one byte of data from target . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|**Table**|**16.**|Transfer when controller is receiving (reading) multiple bytes of data from target . . . . . . . . . . . . . . . . . . . . . . . 19|
|**Table**|**17.**|MIPI I3C®CCC commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|**Table**|**18.**|Register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27|
|**Table**|**19.**|IF_PU_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|**Table**|**20.**|IF_PU_CTRL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|**Table**|**21.**|IF_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|**Table**|**22.**|IF_CTRL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|**Table**|**23.**|CTRL1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|**Table**|**24.**|CTRL1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|**Table**|**25.**|CTRL2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|**Table**|**26.**|CTRL2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|**Table**|**27.**|CTRL3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|**Table**|**28.**|CTRL3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|**Table**|**29.**|CTRL4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|**Table**|**30.**|CTRL4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|**Table**|**31.**|ODR frequency in inactivity state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|**Table**|**32.**|CTRL5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
|**Table**|**33.**|CTRL5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
|**Table**|**34.**|Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
|**Table**|**35.**|Bandwidth selection (ODR ≥ 50 Hz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
|**Table**|**36.**|Bandwidth selection (ODR < 50 Hz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
|**Table**|**37.**|Full-scale selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
|**Table**|**38.**|FIFO_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
|**Table**|**39.**|Selection of FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
|**Table**|**40.**|FIFO_WTM register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|**Table**|**41.**|FIFO_WTM register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|**Table**|**42.**|INTERRUPT_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|**Table**|**43.**|INTERRUPT_CFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|**Table**|**44.**|TAP_THS_X register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|**Table**|**45.**|TAP_THS_X register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|**Table**|**46.**|TAP_THS_Y register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|**Table**|**47.**|TAP_THS_Y register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|**Table**|**48.**|Selection of axis priority for tap detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|**Table**|**49.**|TAP_THS_Z register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
|**Table**|**50.**|TAP_THS_Z register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
|**Table**|**51.**|INT_DUR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
|**Table**|**52.**|INT_DUR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
|**Table**|**53.**|WAKE_UP_THS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
**DS15012** - **Rev 2**
**page 53/56**
**MIS2DU12 List of tables**
**Table 54.** WAKE_UP_THS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 **Table 55.** WAKE_UP_DUR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 **Table 56.** WAKE_UP_DUR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 **Table 57.** FREE_FALL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 **Table 58.** FREE_FALL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 **Table 59.** MD1_CFG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 **Table 60.** MD1_CFG register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 **Table 61.** MD2_CFG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 **Table 62.** MD2_CFG register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 **Table 63.** WAKE_UP_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 **Table 64.** WAKE_UP_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 **Table 65.** TAP_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 **Table 66.** TAP_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 **Table 67.** SIXD_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 **Table 68.** SIXD_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 **Table 69.** ALL_INT_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 **Table 70.** ALL_INT_SRC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 **Table 71.** STATUS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 **Table 72.** STATUS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 **Table 73.** FIFO_STATUS1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 **Table 74.** FIFO_STATUS1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 **Table 75.** FIFO_STATUS2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 **Table 76.** FIFO_STATUS2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 **Table 77.** OUT_X_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 **Table 78.** OUT_X_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 **Table 79.** OUT_X_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 **Table 80.** OUT_X_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 **Table 81.** OUT_Y_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 82.** OUT_Y_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 83.** OUT_Y_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 84.** OUT_Y_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 85.** OUT_Z_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 86.** OUT_Z_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 87.** OUT_Z_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 88.** OUT_Z_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 89.** OUT_T_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 90.** OUT_T_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 91.** OUT_T_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 92.** OUT_T_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 93.** TEMP_OUT_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 94.** TEMP_OUT_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 95.** TEMP_OUT_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 96.** TEMP_OUT_H register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 97.** WHO_AM_I register default values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 **Table 98.** ST_SIGN register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 **Table 99.** ST_SIGN register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 **Table 100.** Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
**DS15012** - **Rev 2**
**page 54/56**
**MIS2DU12 List of figures**
## **List of figures**
|**Figure**|**1.**|Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3|
|---|---|---|
|**Figure**|**2.**|Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
|**Figure**|**3.**|SPI target timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|**Figure**|**4.**|I²C target timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|**Figure**|**5.**|MIS2DU12 electrical connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
|**Figure**|**6.**|Read and write protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|**Figure**|**7.**|SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21|
|**Figure**|**8.**|Multiple byte SPI read protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21|
|**Figure**|**9.**|SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22|
|**Figure**|**10.**|Multiple byte SPI write protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22|
|**Figure**|**11.**|SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
|**Figure**|**12.**|I²C and I3C both active (INT1 pin not connected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|**Figure**|**13.**|Only I3C active (INT1 pin connected to VDDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|**Figure**|**14.**|LGA-12L 2.0 x 2.0 x 0.74 mm package outline and mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48|
**DS15012** - **Rev 2**
**page 55/56**
**MIS2DU12 List of figures**
## **IMPORTANT NOTICE – READ CAREFULLY**
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The purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of the purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2025 STMicroelectronics – All rights reserved
**DS15012** - **Rev 2**
**page 56/56**
## Links
- [View this product on Novapart](https://novapart.co/products/MIS2DU12TR/mems-accelerometer-2g-4g-8g-16g-x-y-z-i2c-mipi-i3c)
- [Request a quote for this part](https://novapart.co/quote/)
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---
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