# Graphic OLED, 256 x 64 Pixels, Green on Black, 3.3V, Parallel, SPI, 100.5mm x 33.5mm, -40 °C

![Product image](https://novapart.co/image/farnell:3154934/)

**URL**: https://novapart.co/products/MDOB256064BX-GM/graphic-oled-256-x-64-pixels-green-on-black-33v
**SKU**: MDOB256064BX-GM
**Manufacturer**: MIDAS DISPLAYS
**Category**: Optoelectronics & Displays || Displays || OLED Displays || Graphic OLED Displays
**Price**: €49.1000
**Stock**: 10+
**Lead Time**: 176 days (indicative)

## Description

Resolution:256 x 64 Pixels; Display Appearance:Green on Black; Logic Voltage:3.3V; Interface Type:Parallel, SPI; Module Size:100.5mm x 33.5mm; Operating Temperature Min:-40°C; Ope

## Specifications

| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| Resolution | 256 x 64 Pixels |
| Module Size | 100.5mm x 33.5mm |
| Logic Voltage | 3.3V |
| Product Range | - |
| Interface Type | Parallel, SPI |
| Display Appearance | Green on Black |
| Display Construction | COB |
| Operating Temperature Max | 85°C |
| Operating Temperature Min | -40°C |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3154934/)

**Sauls Wharf House Crittens Road Great Yarmouth Norfolk NR31 0AG** 

Telephone +44 (0)1493 602602 Email:sales@midasdisplays.com Email:tech@midasdisplays.com www.midasdisplays.com 

|MDOB256064BX-GM|MDOB256064BX-GM|256 x 64|256 x 64|OLED Module|
|---|---|---|---|---|
|**Specification **|||||
|Version:    1|||Date:15/10/2013||
|**Revision**|||||
|1|15/10/2013||First Issue||



|DisplayFeatures|DisplayFeatures|||
|---|---|---|---|
|Resolution|256 x 64|||
|Appearance|Green on Black|||
|Logic Voltage|3.3V|||
|Interface|Parallel,SPI|||
|Module Size|100.50 x 33.50 x 6.30mm|||
|OperatingTemperature|-40°C ~ +85°C|BoxQuantity|Weight / Display|
|Construction|COB|---|---|



* - For full design functionality, please use this specification in conjunction with the SSD1322 specification. (Provided Separately) 

|**Display Accessories**|**Display Accessories**|
|---|---|
|**Part Number**|**Description**|



|**Optional Variants**||
|---|---|
|**Appearance**|**Voltage**|



Page 1 of 19 

## **1. FUNCTIONS & FEATURES** 

Features 

|Item<br>~~=—~~|Specs<br>~~=—~~|
|---|---|
|Display Mode/Colour<br>~~=—~~|Passive Matrix OLED.YELLOW/WHITE/GREEN<br>~~=—~~|
|Interface<br>~~=—~~|8-Bit 68XX/80XX Parallel、SPI<br>~~=—~~|
|Drive Duty<br>~~=—~~|1/64<br>~~=—~~|
|Driver IC<br>~~=—~~|SSD1322<br>~~=—~~|
|Shell<br>~~=—~~|0.5T<br>~~=—~~|
|Other<br>~~=—~~|- 256X64 dots<br>~~=—~~|



## **2. MECHANICAL SPECIFICATIONS** 

|**ITEM**|**SPECIFICATIONS**|**UNIT**|
|---|---|---|
|Module Size|100.5L×33.5W×6.3H|mm|
|View<br>Area|78.78×21.18|mm|
|Effective Area|256×64|dots|
|Pixel Size|0.28×0.28|mm|
|Pixel Pitch|0.30×0.30|mm|



## **3. EXTERNAL DIMENSIONS** 

Page 2 of 19 

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Page 3 of 19 

## **4. BLOCK DIAGRAM** 

Page 4 of 19 

## **5. POWER SUPPLY** 

## **6. PIN DESCRIPTION** 

## Parallel Interface(8080): (R18,R21 USE; R19,R20 NO USE) 

|ITEM|SYMBOL|LEVEL|FUNCTION|
|---|---|---|---|
|1|GND|0V|Power Ground|
|2|VDD|+3.3~+5.0V|Power SupplyFor Logic|
|3|NC|-|No connect|
|4~11|D0～D7|H/L|Data Bus|
|12|RD|H/L|8080: Active LOW Read signal|
|13|WR|H/L|8080:Active LOW Write signal|
|14|D/C(RS)|H/L|H：Data<br>L：Command|
|15|/RST|H/L|Active LOW Reset signal|
|16|/CS|L|ChipSelect|



## Parallel Interface(6800): (R18,R20 USE; R19,R21 NO USE) 

|ITEM|SYMBOL|LEVEL|FUNCTION|
|---|---|---|---|
|1|GND|0V|Power Ground|
|2|VDD|+3.3~+5.0V|Power SupplyFor Logic|
|3|NC|-|No connect|
|4~11|D0～D7|H/L|Data Bus|
|12|RD|H/L|6800:Operation enable signal. Fallingedge triggered.|
|13|WR|H/L|6800:Read/Write select signal, R/W=1: Read R/W:<br>=0: Write|
|14|D/C(RS)|H/L|H：Data<br>L：Command|
|15|/RST|H/L|Active LOW Reset signal|
|16|/CS|L|ChipSelect|



Page 5 of 19 

## 4-SPI: (R19,R21 USE; R18,R20 NO USE) 

|4-SPI: (R19,R21 USE; R18,R20 NO USE)|4-SPI: (R19,R21 USE; R18,R20 NO USE)|4-SPI: (R19,R21 USE; R18,R20 NO USE)|4-SPI: (R19,R21 USE; R18,R20 NO USE)|
|---|---|---|---|
|ITEM|SYMBOL|LEVEL|FUNCTION|
|1|GND|0V|Power Ground|
|2|VDD|+3.3~+5.0V|Power SupplyFor Logic|
|3|NC|-|No connect|
|4|SCLK(D0)|H/L|Serial Clock signal|
|5|SDIN(D1)|H/L|Serial Data input signal|
|6|NC(D2)|-|No connect|
|7~11|D3~D7|0V|Power Ground|
|12|RD|0V|Power Ground|
|13|WR|0V|Power Ground|
|14|D/C(RS)|H/L|H：Data<br>L：Command|
|15|/RST|H/L|Active LOW Reset signal|
|16|/CS|L|ChipSelect|



## **3-SPI :** (R19,R20 USE; R18,R21 NO USE) 

|ITEM|SYMBOL|LEVEL|FUNCTION|
|---|---|---|---|
|1|GND|0V|Power Ground|
|2|VDD|+3.3~+5.0V|Power SupplyFor Logic|
|3|NC|-|No connect|
|4|SCLK(D0)|H/L|Serial Clock signal|
|5|SDIN(D1)|H/L|Serial Data input signal|
|6|NC(D2)|-|No connect|
|7~11|D3~D7|0V|Power Ground|
|12|RD|0V|Power Ground|
|13|WR|0V|Power Ground|
|14|D/C(RS)|0V|Power Ground|
|15|/RST|H/L|Active LOW Reset signal|
|16|/CS|L|ChipSelect|



Page 6 of 19 

|**7 .**<br>**Absolute Maximum Ratings**||
|---|---|
|**Parameter**<br>**Symbol**<br>**Min**<br>**Max**<br>**Unit**<br>**Notes**<br>SupplyVoltage for Logic<br>Vdd<br>3.3<br>5<br>V<br>1,2<br>SupplyVoltage for Display<br>VCC<br>0<br>15<br>V<br>1,2<br>OperatingTemperature<br>Top<br>-40<br>85<br>℃<br>-<br>Storage Temperature<br>Tst<br>-45<br>90<br>℃<br>-<br>~~SSE~~||
|Note 1: All the above voltages are on the basis of “VSS = 0V”.||
|Note 2: When this module is used beyond the above absolute maximum ratings,||
|permanent breakage of the module may occur. Also, for normal operations, it||
|is desirable to use this module under the conditions according to Section 3.||
|“Optics & Electrical Characteristics”. If this module is used beyond these||
|conditions, malfunctioning of the module can occur and the reliability of the||
|module may deteriorate.||



## **8 . ELECTRICAL CHARACTERISTICS** 

|**Items**|**Symbol**|**Condition**|**Min**|**TY**<br>**P**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Operating Temperature Range|Top|Absolute Max|-40|—|+85|⁰C|
|Storage Temperature Range|Tst|Absolute Max|-45|—|+90|⁰C|
||||||||
|Supply Voltage|Vdd||2.8|3.0|3.3|V|
|Supply Current (logic)|Idd|Ta=25°C, VDD=3.3V|—|180|300|μA|
|Supply Current (display)|ICC|50% ON, VDD=3.3V|—|62|70|mA|
|||100% ON, VDD=3.3V|—|113|120|mA|
|Sleep Mode Current|IDD+ICCS<br>LEEP||—|3|15|μA|
|“H” Level input|Vih||0.8*VDD|—|VDD|V|
|“L” Level input|Vil||VSS|—|0.2*VDD|V|
|“H” Level output|Voh||0.9*VDD|—|VDD|V|
|“L” Level output<br>~~See~~|Vol<br>~~See~~|~~See~~|VSS<br>~~See~~|—<br>~~See~~|0.1*VDD<br>~~See~~|V<br>~~See~~|



## 9 . Optical Characteristics 

|Item|Symbol|Condition|Min.|Typ.|Max.|Unit|
|---|---|---|---|---|---|---|
|ViewingAngle– Top|AV||—|80|—||
|Viewing Angle–Bottom|AV||—|80|—||
|ViewingAngle– Left|AH||—|80|—||
|Viewing Angle–Right|AH||—|80|—||



Page 7 of 19 

|Contrast Ratio|Cr||2000:1|—|—|—|
|---|---|---|---|---|---|---|
|Response Time (rise)|Tr|—|—|10|—|us|
|Response Time (fall)|Tf|—|—|10|—|us|
|Brightness||50% checkerboard|100|120|—|cd/m2|
|Lifetime||Ta=25°C, 50%<br>checkerboard|10,000|—|—|Hrs|



Note: Lifetime at typical temperature is based on accelerated high‐temperature operation. Lifetime is tested at average 50% pixels on and is rated as Hours until Half‐Brightness. The Display OFF command can be used to extend the lifetime of the display. 

Luminance of active pixels will degrade faster than inactive pixels. Residual (burn‐in) images may occur. To avoid this, every pixel should be illuminated uniformly. 

Page 8 of 19 

## **10. COMMAND TABLE** 

## **Built** ‐ **in SSD1322 controller.** 

Page 9 of 19 

|**_DIC#_**|**Hex**<br>**D7D6**<br>**D5**<br>**D4**|**D3D2**<br>**D2**|**DO**|**Command**|**Description**|
|---|---|---|---|---|---|
|0<br>I|A2<br>I<br>0<br>I<br>0<br>A[6:0]<br>*<br>A6<br>As<br>A4|0<br>0<br>I<br>A3<br>A2<br>A,|0<br>Ao|Set Display<br>Offset|Set vertical scroll by COM from 0-127<br>The value is reset to OOH after RESET<br>A4h = Entire Display OFF, all pixels turns OFF in GS level 0|
|0<br>0<br>I<br>I|A4~A7<br>I<br>0<br>I<br>0<br>AS<br>I<br>0<br>I<br>0<br>A[6:0]<br>0<br>A6<br>As<br>A4<br>B[6:0]<br>0<br>B6<br>B,<br>B•|0<br>X2~~x,~~<br>I<br>0<br>0<br>A3<br>A2<br>A,<br>B3<br>B2<br>B,|Xo<br>0<br>Ao<br>Bo|Set Display<br>Mode<br>Enable Partial<br>Display|A4h = Entire Display OFF, all pixels turns OFF in GS level 0<br>A5h = Entire Display ON, all pixels turns ON in GS level 15<br>A6h = Normal Display [reset]<br>A7h = Inverse Display (GS0 ➔ GSI5, OSI ➔ GS14, GS2<br>➔GS13, ... )<br>This command turns ON partial mode. The partial mode<br>display area is defined by the following two parameters,<br>A[6:0]: Address of start row in the display area<br>8[6:0]: Address of end row in the display area,<br>where B[6:0] must be 2'. A[6:0]|
|0<br>0<br>I|A9<br>I<br>0<br>I<br>0<br>AB_t' _<br>0<br>I<br>0<br>A[0]<br>0<br>0<br>0|I<br>0<br>0<br>I<br>o,l<br>0<br>0|I<br>I(<br>Ao<br>,|(<br>Exit Partial<br>Display<br>,-funetion-<br>Selection|This command is sent to exit the Partial Display mode<br>A[0] 0b, Select external Y00<br>:,.,...-<br>A[0]=lb, Enable internal Y00re\utior [reset]|
|||**r**|||:,.,...-<br>A[0]=lb, Enable internal Y|
|0|AE~AF<br>I<br>0<br>I<br>0|I<br>I<br>I|Xo|Set Sleep mode<br>ON/OFF|AEh\<br>AFJ|
|0<br>I|BI<br>I~~I~~<br>0<br>I<br>A[7:0]<br>A6<br>As<br>_A11_<br>1<br>Ay|0<br>**J**<br> <br>A3<br>0}<br>0<br>Ao|<br>Ay|I<br>Ao(|(<br>_(3·0]_Phase I period (reset phase length) of5~3 l Q,CL (s)<br>locks as follow:<br>Af3:0l<br>Phase I period<br>0000<br>invalid<br>0001<br>invalid<br>0010<br>5 DCLKs<br>001 I<br>7 DCLKs<br>0100<br>9 DCLKs fresetl<br>:<br>:<br>1111<br>31 DCLKs<br>Set Phase<br>A[7:4] Phase 2 period (first pre-charge phase length) of<br>Length<br>3~15 DCLK(s) clocks as follow:<br>A[?:41<br>Phase2period<br>0000<br>invalid<br>0001<br>invalid<br>0010<br>invalid<br>0011<br>3 DCLKs<br>:<br>:<br>OJ I I<br>7 DCLKs f resetl<br>:<br>:<br>1111<br>15 DCLKs<br>P<br>.<br>K<br>r||



Page 10 of 19 

|_DIC#_<br>**Hex**<br>**0**<br>**83**<br>[=a|_DIC#_<br>**Hex**<br>**0**<br>**83**<br>[=a|**D7**<br>**I**<br> ae|**D7D6**<br>**0**<br> (a|**D7D6**<br>**0**<br> (a|**D6**|**DS**<br>**I**|**D4D3**<br>**I**<br>**0**<br>a|**D4D3**<br>**I**<br>**0**<br>a|**D2**<br>**0**<br> a|**D2**<br>**I**<br> ee|**DO**<br>**I**<br> ee|**Command**<br>re|**Command**<br>re|**A[3:0J**|**A[3:0J**|**Description**<br>**[3:0J[resc-0], divide by DIVSET where**||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**I**|**A[7:0J**|_A1_|A6|||**As**|**A4**|_A3 _|**A2**|**A1**|**Ao**|||||**Af3:0l**<br>**DIVSET**||
|||||||||||||||||**0000**<br>**divide bv I**||
|||||||||||||||||**0001**<br>**divide by 2**||
|||||||||||||||||**0010**<br>**divide by 4**||
|||||||||||||||||**0011**<br>**divide bv 8**||
|||||||||||||||||**0100**<br>**divide by 16**||
|||||||||||||||||**0101**<br>**divide bv 32**||
|||||||||||||**I Set Front Clock**<br>**Di ider/ **||**I Set Front Clock**||**0110**<br>**divide by 64**<br>**Ol li**<br>**divide by 128**||
|||||||||||||**0 cillator**||||**1000**<br>**divide bv 256**||
|||||||||||||**Frequency**|**Frequency**|||**1001**<br>**divide by 512**||
|||||||||||||||||**1010**<br>**divide bv I 024**||
|||||||||||||||||**>=1011 **<br>**invalid**||
|||||||||||||||**A[7:4J O cillator frequency, frequency increases as level**||**A[7:4J O cillator frequency, frequency increases as level**<br>Ss||
|||||||||||||||**increases [ reset=0 I 0 I b J**||||
|**0**<br>**I**|**B4**<br>**A[I :OJ**|**I**<br>; Ww<br>r|.|**0**<br>**0**||I<br>**I**|I<br>**0**|**0**<br>**0**|**0**<br>Ley<br>yo ||**0**<br>**A1**|**0, **<br>**Ao**|**,**<br>—<br>_|**rA[l :OJ - 00b: Enable external VSL**<br>**-IAl I :OJ**<br>le||**rA[l :OJ - 00b: Enable external VSL**<br>**Al I :OJ**|**rA[l :OJ - 00b: Enable external VSL4"**<br>**Al I :OJ= I Oh: InternalV L [reset]**<br>=<br>———s<br>S<br>i||
|**I**|**8[7:3]**|7|**B6**|||**8s**|**84**|**BJ **|**I**|**0**|**I**|||||||
|**0**|**85**|..<br>**I**|..|**0**|·|**I**|vj<br>**I**|vj<br>**0**<br>dy|I<br>**I**|**0**|**I**|**Display**<br>**Enhancement A**|**8[7:3**<br>**11 I 11 b: Enhanced low Gdi play-q**<br>**Enhancement A8[7:31**<br>**IOI I Oh:onnal [re cl]**<br>J/<br>1,<br>.<br>**A[I :OJ GPIO0: 00 pin HiZ, Input disabled**<br>=<br>N<br>s||||**ity**<br>_|
|**I**|**A[3:0]**|•||• •|• •|• •|•|**AJ **|**A2**|**A1**|**Ao**|||||**01 pin HiZ, Input enabled**<br>**I 0 pin output LOW [reset]**||
|||||||||||||||||**11 pin output HIGH**||
|||||||||||||**et GPIO**||**A[3:2J GPIO I: 00 pin HiZ, Input di abled**||**A[3:2J GPIO I: 00 pin HiZ, Input di abled**||
|||||||||||||||||**01 pin HiZ, Input enabled**||
|||||||||||||||||**I 0 pin output LOW [reset]**||
|||||||||||||||||**11 pin output HIGH**||
|**0**|**86**|**I**||**0**||**I**|**I**|**0**|**I**|**I**|**0**|||**A[3:0J Second Pre-charge period**||**A[3:0J Second Pre-charge period**||
|**I**|**A[3:0]**|•||•||•|•|**AJ **|**A2**|**A1**|**Ao**|||||**0000b 0 dclk**<br>**0001bI dclk**||
|||||||||||||**et econd**<br>**Precharge**|**et econd**|||......<br>**1000b8 dclks [reset]**||
|||||||||||||**Period**||||......<br>**II lib15 dclks**||



Page 11 of 19 

Page 12 of 19 

For detailed instruction information, see SSD1322 datasheet . 

## **11 . MPU Interface** 

Page 13 of 19 

Page 14 of 19 

Page 15 of 19 

Page 16 of 19 

## **12. GDDRAM** 

12.1 GDDRAM structure in Gray Scale mode 

The GDDRAM address map in Table 8-6 shows the GDDRAM in Gray Scale mode. Since in Gray 

Page 17 of 19 

Scale mode, there are 16 gray levels. Therefore four bits (one nibble) are allocated for each pixel. For example D30480[3:0] in Table 8-6 corresponds to the pixel located in (COM127, SEG2). So the lower nibble and higher nibble of D0, D1, D2, …, D30717, D30718, D30719 in Table 8-6 represent the 480x128 data nibbles in the GDDRAM. 

12.2 Data bus to RAM mapping 

## **14 . DESIGN AND HANDING PRECAUTION** 

14.1 The LCD panel is made by glass. Any mechanical shock (eg. Dropping form high place) will damage the LCD module. Do not add excessive force on the surface of the 

Page 18 of 19 

display, which may cause the Display color change abnormally. 

14.2 The polarizer on the LCD is easily get scratched. If possible, do not remove the LCD protective film until the last step of installation. 

- 14.3 Never attempt to disassemble or rework the LCD module. 

14.4 Only Clean the LCD with Isopropyl Alcohol or Ethyl Alcohol. Other solvents (eg. water) may damage the LCD. 

14.5 When mounting the LCD module, make sure that it is free form twisting, warping and distortion. 

14.6 Ensure to provide enough space(with cushion) between case and LCD panel to prevent external force adding on it, or it may cause damage to the LCD or degrade the display result 

14.7 Only hold the LCD module by its side. Never hold LCD module by add force on the heat seal or TAB. 

14.8 Never add force to component of the LCD module. It may cause invisible damage or degrade of the reliability. 

14.9 LCD module could be easily damaged by static electricity. Be careful to maintain an optimum anti-static work environment to protect the LCD module. 

14.10 When peeling of the protective film form LCD, static charge may cause abnormal display pattern. It is normal and will resume to normal in a short while. 

14.11 Take care and prevent get hurt by the LCD panel edge. 

14.12 Never operate the LCD module exceed the absolute maximum ratings. 

14.13 Keep the signal line as short as possible to prevent noisy signal applying to LCD module. 

14.14 Never apply signal to the LCD module without power supply. 

14.15 IC chip (eg. TAB or COG) is sensitive to the light. Strong lighting environment could possibly cause malfunction. Light sealing structure casing is recommend. 

14.16 LCD module reliability may be reduced by temperature shock. 

14.17 When storing the LCD module, avoid exposure to the direct sunlight, high humidity, high temperature or low temperature. They may damage or degrade the LCD module 

Page 19 of 19 



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- [View this product on Novapart](https://novapart.co/products/MDOB256064BX-GM/graphic-oled-256-x-64-pixels-green-on-black-33v)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/midas/mdob256064bx-gm/oled-graphic-display-cob-256x64pixels/dp/3154934)
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