# Graphic OLED, 256 x 64 Pixels, Green on Black, 2.8V, Multi, 146mm x 45mm, -40 °C
**URL**: https://novapart.co/products/MCOT256064CY-GM/graphic-oled-256-x-64-pixels-green-on-black-28v
**SKU**: MCOT256064CY-GM
**Manufacturer**: MIDAS DISPLAYS
**Category**: Optoelectronics & Displays || Displays || OLED Displays || Graphic OLED Displays
**Price**: €72.0600
**Stock**: 25+
**Lead Time**: 92 days (indicative)
## Specifications
| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| Resolution | 256 x 64 Pixels |
| Module Size | 146mm x 45mm |
| Logic Voltage | 2.8V |
| Product Range | - |
| Interface Type | Multi |
| Display Appearance | Green on Black |
| Display Construction | COT |
| Operating Temperature Max | 80°C |
| Operating Temperature Min | -40°C |
## Datasheet
📄 [Download PDF](https://novapart.co/datasheet/farnell:4685237/)
**Sauls Wharf House Crittens Road Great Yarmouth Norfolk NR31 0AG**
Telephone +44 (0)1493 602602 Email:sales@midasdisplays.com Email:tech@midasdisplays.com www.midasdisplays.com
|MCOT256064CY-GM|MCOT256064CY-GM|256 x 64|256 x 64|OLED Module|
|---|---|---|---|---|
|**Specification **|||||
|Version: 1|||Date: 16/05/2017||
|**Revision**|||||
|1|11/05/2017||First Issue||
|DisplayFeatures|DisplayFeatures|||
|---|---|---|---|
|Resolution|256 x 64|||
|Appearance|Green on Black|||
|Logic Voltage|2.8V|||
|Interface|Multi|||
|Module Size|146.00 x 45.00 x 2.00mm|||
|OperatingTemperature|-40°C ~ +80°C|BoxQuantity|Weight / Display|
|Construction|COT|---|---|
* - For full design functionality, please use this specification in conjunction with the SSD1322 specification. (Provided Separately)
|**Display Accessories**|**Display Accessories**||**Optional Variants**||
|---|---|---|---|---|
|**Part Number**|**Description**||**Appearance**|**Voltage**|
Page 1 of 22
- 1) Display Mode:
Passive Matrix
- 2) Display Color: Monochrome with 16 Gray Scales (Green) 3) Drive Duty: 1/64 Duty
- 1) Outline Drawing: According to the annexed outline drawing
- 2) Number of Pixels: 256 64 x 3) Panel Size: 146.00 45.00 2.00 (mm) xx 4) Active Area: 135.65 33.89 (mm) x 5) Pixel Pitch: 0.53 0.53 (mm) x
- 6) Pixel Size:
- 0.50 0.50 (mm) x
- 7) Weight: 27.1 (g)
**==> picture [255 x 70] intentionally omitted <==**
**----- Start of picture text -----**
( Column 1 ) ( Column 256 )
Segment 239 Segment 240
( Column 128 ) ( Column 129 )
Common AO Common BO
( Row 64 ) ( Row 64 )
Common A63 Common B63
Row 1 Row 1
UA) Cm)
**----- End of picture text -----**
Page 2 of 22
**==> picture [252 x 350] intentionally omitted <==**
**----- Start of picture text -----**
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Polarizert=0.2mm Contact Side
i
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Column 256 Row 64 Row 1
Column 129
Column 128
Column 1 Row 64 Row 1
Signature
Customer Approval
**----- End of picture text -----**
Page 3 of 22
|||||
|---|---|---|---|
|PowerSupply||||
|26
25
24
2
3, 29
5, 28
OS
OO
po
OO
OS|VCI
VDD
VDDIO
VSS
VCC
VLSS|P
P
P
P
P
P|This is a voltage supply pin. It must be connected to external source & always be
equal to or higher than VDD& VDDIO.
This is a voltage supply pin. It can be supplied externally (within the range of
2.4~2.6V) or regulated internally from VCI. A capacitor should be connected
between this pin & VSSunder all circumstances.
This pin is a power supply pin of I/O buffer. It should be connected to VCI or
external source. All I/O signal should have VIHreference to VDDIO. When I/O
signal pins (BS0~BS1, D0~D7, control signals…) pull high, they should be
connected to VDDIO.
This is a ground pin. It also acts as a reference for the logic pins. It must be
connected to external ground.
These are the most positive voltage supply pin of the chip. They must be
connected to external source.
These are the analog ground pins. They should be connected to VSSexternally.
Power Supply forOperation
~~r~~ee
Supply forCore Logic Circuit
Power Supply forI/O Pin
Ground of Logic Cireatt
ee rreee
Supply forOEL Panel
~~Ground ofanalog Cireut~~
ofAnalog Circuit|
|~~Ground ofanalog Cireut~~||||
|22
4
27
i
OS|IREF
VCOMH
VSL|I
P
P|This pin is segment current reference pin. A resistor should be connected
between this pin and VSS
This pin is the input pin for the voltage output high level for COM signals. A
tantalum capacitor should be connected between this pin and VSS.
This is segment voltage reference pin.
When external VSLis not used, this pin should be left open.
When external VSL is used, this pin should connect with resistor and diode to
ground.
Current Reference for BrightnessAdjustment
._
Set the current at 10UA maximum.
Voltage Output High Level forCOM Signal
Output Low Level for SEG Signal|
|TestingPads
~~DESIGN-MANUFACTURE~~||||
|21
~~DESIGN~~|FR
~~DESIGN-MA~~|O
~~MA~~|This pin will send out a signal that could be used to identify the driver status.
Nothing should be connected to this pin. It should be left open individually.
~~NUFACTURE~~|
|~~DESIGN - MANUFACTURE~~
Interface||||
|16
17
20
19
18
OS|BS0
BS1
RES#
CS#
D/C#|I
I
I
I|These pins are MCU interface selection input. See thefollowing table:
BS0
BS1
3-wire Serial
1
0
4-wire Serial
0
0
8-bit 68XX Parallel
1
1
8-bit 80XX Parallel
0
1
This pin is reset signal input. When the pin is low, initialization of the chip is
executed. Keep this pin pull high during normal operation.
This pin is the chip select input. The chip is enabled for MCU communication only
when CS# is pulled low.
This pin is Data/Command control pin. When the pin is pulled high, the input at
D7~D0 is treated as display data. When the pin is pulled low, the input at D7~D0
will be transferred to the command register.
When the pin is pulled high and serial interface mode is selected, the data at SDIN
is treated as data. When it is pulled low, the data at SDIN will be transferred to
the command register.
When 3-wire serial mode is selected, this pin must be connected to VSS.
For detail relationship to MCU interface signals, please refer to the Timing
CharacteristicsDiagrams.
Communicating Protocol Select
~~ee~~
~~ee ee~~
~~Po~~
Power Reset for Controller and Driver
~~O~~o
Command Control|
Page 4 of 22
|||||
|---|---|---|---|
|14
E/RD#
I
This pin is MCU interface input. When interfacing to a 68XX-series
microprocessor, this pin will be used as the Enable (E) signal. Read/write operation
is initiated when this pin is pulled high and the CS# is pulled low.
When connecting to an 80XX-microprocessor, this pin receives the Read (RD#)
signal. Data read operation is initiated when this pin is pulled low and CS# is
pulled low.
When serial mode is selected, this pin must be connected to VSS.
15
R/W#
I
This pin is MCU interface input. When interfacing to a 68XX-series
microprocessor, this pin will be used as Read/Write (R/W#) selection input. Pull
this pin to “High” for read mode and pull it to “Low” for write mode.
When 80XX interface mode is selected, this pin will be the Write (WR#) input.
Data write operation is initiated when this pin is pulled low and the CS# is pulled
low.
When serial mode is selected, this pin must be connected to VSS.
6~13
D7~D0
I/O
These pins are 8-bit bi-directional data bus to be connected to the
microprocessor’s data bus. When serial mode is selected, D1 will be the serial
data input SDIN and D0 will be the serial clock input SCLK.
Unused pins must be connected to VSSexcept for D2 in serial mode.
Interface (Continued)
~~pte~~
Enableor Read
i
Read/Write Select or Write
OO
Host Data Input/Output Bus||||
|Reserve||||
|23
1, 30|N.C.
N.C. (GND)|-
-|The N.C. pin between function pins is reserved for compatible and flexible design.
The supporting pins can reduce the influences from stresses on the function pins.
These pinsmust be connected to externalground as theESDprotectioncircuit.
Reserved Pin (Supporting Pin)|
Page 5 of 22
MCU Interface Selection: BS0 and BS1 Pins connected to MCU interface: D7~D0, E/RD#, R/W#, D/C#, CS#, and RES# C1, C3, C5: 0.1NF C2, C4: 4.7UF C6: 20uF C7: 1yF C8: 4.7uF / 25V Tantalum Capacitor R1: 910k Q , R1 = (Voltage at IREF - VSS) / IREF R2: 50 Q , 1/4W D1: 1.4V, 0.5W
Page 6 of 22
|||||||
|---|---|---|---|---|---|
|Supply Voltage for Operation
Supply Voltage for Logic
Supply Voltage for I/O Pins
Supply Voltage for Display
Operating Current for VCC
Operating Temperature
Storage Temperature|VCI
VDD
VDDIO
VCC
ICC
TOP
TSTG|-0.3
-0.5
-0.5
-0.5
-
-40
-40|4
2.75
VCI
16
80
70
85|V
V
V
V
mA
C
C|1, 2
1, 2
1, 2
1, 2
1, 2
3
3|
- Note 1: All the above voltages are on the basis of “VSS = 0V”.
- Note 2: When this module is used beyond the above absolute maximum ratings, permanent breakage of the module may occur. Also, for normal operations, it is desirable to use this module under the conditions according to Section 3. “Optics & Electrical Characteristics”. If this module is used beyond these conditions, malfunctioning of the module can occur and the reliability of the module may deteriorate.
- Note 3: The defined temperature ranges do not include the polarizer. The maximum withstood temperature of the polarizer should be 80 C.
- Note 4: VCC = 15.0V, Ta = 25°C, 50% Checkerboard.
- Software configuration follows Section 4.4 Initialization.
- End of lifetime is specified as 50% of initial brightness reached. The average operating lifetime at room temperature is estimated by the accelerated operation at high temperature conditions.
Page 7 of 22
|Optics Characteristics|||||||
|---|---|---|---|---|---|---|
|~~|Characteristics|~~|~~|Symbol~~|~~|__Conditions|~~|~~|Min|~~|~~|Typ|~~|~~|Max|~~|~~|Unit~~|
|Brightness
C.I.E. (Green)
Dark Room Contrast
Viewing Angle
~~| Characteristics |~~|Lbr
(x)
(y)
CR
~~| Symbol ~~
~~ee~~|Note 5
C.I.E. 1931
~~| __Conditions |~~|60
0.27
0.58
-
-
~~| Min |~~|80
0.31
0.62
>10,000:1
Free
~~| Typ |~~|-
0.35
0.66
-
-
~~| Max |~~
~~|~~|cd/m2
degree
~~| Unit~~|
* Optical measurement taken at VCI = 2.8V, VCC = 15.0V. Software configuration follows Section 4.4 Initialization.
|~~|Characteristics|~~|~~|symbol|~~|~~|_Conditions|~~|~~|_Min|~~|~~|Typ|~~|~~|Max|~~|~~|Unit~~|
|---|---|---|---|---|---|---|
|Supply Voltage for Operation
Supply Voltage for Logic
Supply Voltage for I/O Pins
Supply Voltage for Display
High Level Input
Low Level Input
High Level Output
Low Level Output
Operating Current for VCI
Operating Current for VCC
Sleep Mode Current for VCI
Sleep Mode Current for VCC
~~| Characteristics |~~|VCI
VDD
VDDIO
VCC
VIH
VIL
VOH
VOL
ICI
ICC
ICI, SLEEP
ICC, SLEEP
~~| symbol |~~
~~ee~~|Note 5
Iout= 100 A
Iout= 100 A
Note 6
Note 7
Note 8
~~| _Conditions |~~
~~e~~ner
e~~l~~
~~o~~o|2.4
2.4
1.65
14.5
0.8 VDDIO
0
0.9 VDDIO
0
-
-
-
-
-
~~| _Min |~~
~~l~~|2.8
2.5
1.8
15.0
-
-
-
-
180
25.9
39.8
64.0
20
2
~~| Typ |~~|3.5
2.6
VCI
15.5
VDDIO
0.2 VDDIO
VDDIO
0.1 VDDIO
300
32.4
49.8
80.0
100
10
~~| Max |~~|V
V
V
V
V
V
mA
mA
mA
~~| Unit~~
~~uA~~|
Note 5: Brightness (Lbr) and Supply Voltage for Display (VCC) are subject to the change of the panel characteristics and the customer’s request.
Note 6: VCI = 2.8V, VCC = 15.0V, 30% Display Area Turn on.
Note 7: VCI = 2.8V, VCC = 15.0V, 50% Display Area Turn on. Note 8: VCI = 2.8V, VCC = 15.0V, 100% Display Area Turn on.
* Software configuration follows Section 4.4 Initialization.
Page 8 of 22
68XX-Series MPU Parallel Interface Timing Characteristics:
|68XX-Series MPU Parallel Interface Timing Characteristics:|68XX-Series MPU Parallel Interface Timing Characteristics:||||
|---|---|---|---|---|
|~~Symbol~~~~**|**~~|~~**|**Description~~|~~Min_|~~|~~|“Max|~~|~~|Unit|~~|
|tcycle
tAS
tAH
tDSW
tDHW
tDHR
tOH
tACC
PWCSL
PWCSH
tR
tF
~~Symbol ~~~~**|**~~|Clock Cycle Time
Address Setup Time
Address Hold Time
Write Data Setup Time
Write Data Hold Time
Read Data Hold Time
Output Disable Time
Access Time
Chip Select Low Pulse Width (Read)
Chip Select Low Pulse Width (Write)
Chip Select High Pulse Width (Read)
Chip Select High Pulse Width (Write)
Rise Time
Fall Time
~~**|**Description~~|300
10
0
40
7
20
-
-
120
60
60
60
-
-
~~Min_ |~~|-
-
-
-
-
-
70
140
-
-
15
15
~~| “Max |~~|ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
~~| Unit |~~|
* (VDD - VSS = 2.4V to 2.6V, VDDIO = 1.65V, VCI = 2.8V, Ta = 25°C)
Page 9 of 22
80XX-Series MPU Parallel Interface Timing Characteristics:
|80XX-Series MPU Parallel Interface Timing Characteristics:|80XX-Series MPU Parallel Interface Timing Characteristics:||||
|---|---|---|---|---|
||||||
|tcycle
tAS
tAH
tDSW
tDHW
tDHR
tOH
tACC
tPWLR
tPWLW
tPWHR
tPWHW
tCS
tCSH
tCSF
tR
tF|Clock Cycle Time
Address Setup Time
Address Hold Time
Write Data Setup Time
Write Data Hold Time
Read Data Hold Time
Output Disable Time
Access Time
Read Low Time
Write Low Time
Read High Time
Write High Time
Chip Select Setup Time
Chip Select Hold Time to Read Signal
Chip Select Hold Time
Rise Time
Fall Time|300
10
0
40
7
20
-
-
150
60
60
60
0
0
20
-
-|-
-
-
-
-
-
70
140
-
-
-
-
-
-
-
15
15|ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns|
* (VDD - VSS = 2.4V to 2.6V, VDDIO = 1.65V, VCI = 2.8V, Ta = 25°C)
Page 10 of 22
Serial Interface Timing Characteristics: (4-wire Serial)
||||||
|---|---|---|---|---|
|tcycle
tAS
tAH
tCSS
tCSH
tDSW
tDHW
tCLKL
tCLKH
tR
tF|Clock Cycle Time
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Data Setup Time
Write Data Hold Time
Clock Low Time
Clock High Time
Rise Time
Fall Time|100
15
15
20
10
15
15
20
20
-
-|-
-
-
-
-
-
-
-
-
15
15|ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns|
* (VDD - VSS = 2.4V to 2.6V, VDDIO = 1.65V, VCI = 2.8V, Ta = 25°C)
Page 11 of 22
Serial Interface Timing Characteristics: (3-wire Serial)
||||||
|---|---|---|---|---|
|tcycle
tCSS
tCSH
tDSW
tDHW
tCLKL
tCLKH
tR
tF|Clock Cycle Time
Chip Select Setup Time
Chip Select Hold Time
Write Data Setup Time
Write Data Hold Time
Clock Low Time
Clock High Time
Rise Time
Fall Time|100
20
10
15
15
20
20
-
-|-
-
-
-
-
-
-
15
15|ns
ns
ns
ns
ns
ns
ns
ns
ns|
* (VDD - VSS = 2.4V to 2.6V, VDDIO = 1.65V, VCI = 2.8V, Ta = 25°C)
Page 12 of 22
Refer to the Technical Manual for the SSD1322
To protect OEL panel and extend the panel life time, the driver IC power up/down routine should include a delay period between high voltage and low voltage power sources during turn on/off. It gives the OEL panel enough time to complete the action of charge and discharge before/after the operation.
## Power up Sequence:
1. Power up VCI / VDDIO
2. Send Display off command
3. Initialization
4. Clear Screen
5. Power up VCC
6. Delay 200ms
- (When VCC is stable)
7. Send Display on command
Power down Sequence:
1. Send Display off command
2. Power down VCC
3. Delay 100ms (When VCC is reach 0 and panel is completely discharges)
4. Power down VCI / VDDIO
**==> picture [31 x 165] intentionally omitted <==**
**----- Start of picture text -----**
VCC
VCI/VDDIO
VSS/Ground
VCC
VCI/VDDIO
VSS/Ground
**----- End of picture text -----**
Note 9:
- 1) Since an ESD protection circuit is connected between VCI, VDDIO and VCC inside the driver IC, VCC becomes lower than VCI whenever VDD, VDDIO is ON and VCC is OFF.
- 2) VCC should be kept float (disable) when it is OFF.
- 3) Power Pins (VDD, VDDIO, VCC) can never be pulled to ground under any circumstance.
- 4) VCI, VDDIO should not be power down before VCC power down.
When RES# input is low, the chip is initialized with the following status:
1. Display is OFF
2. 480 x 128 Display Mode
3. Normal segment and display data column and row address mapping (SEG0 mapped to column address 00h and COM0 mapped to row address 00h)
4. Display start line is set at display RAM address 0
5. Column address counter is set at 0
6. Normal scan direction of the COM outputs
7. Contrast control register is set at 7Fh
Page 13 of 22
## **A**
Command usage and explanation of an actual example
**==> picture [417 x 482] intentionally omitted <==**
**----- Start of picture text -----**
Set Display Start Line Enhance Driving Scheme Capability
0xA1, 0x00 0xD1, 0x82, 0x20
|
Power up VCI/VDDIO Set Re-Map & Dual COM Line Mode Set Pre-Charge Voltage
(RES# as Low State) 0xA0, 0x14, 0x11 0xBB, 0x1F
ee | ee
Power Stabilized Set GPIO Set Second Pre-Charge Period
(300ms Delay Recommended) 0xB5, 0x00 0xB6, 0x08
| ee|
Set RES# as High Function Selection Set VCOMH Deselect Level
0xAB, 0x01 0xBE, 0x07
ee |
Initialized State Set Segment Low Voltage Set Display Mode
(Parameters as Default) 0xB4, 0xA0, 0xFD 0xA6
ee | ee |
Command Lock Set Contrast Current
0xFD, 0x12 0xC1, 0xFF
|
Set Display Off Master Contrast Current Control Power up VCC & Stabilized
0xAE 0xC7, 0x0F (Delay Recommended)
ee |
Select Gray Scale Table Set Display On
Configuration 0xB8, ee 0xAF
0x00, 0x00, 0x00, 0x03,
0x06, 0x10, 0x1D, 0x2A,
Set Display Clock Divide Ratio/Oscillator Frequency 0x37, 0x46, 0x58, 0x6A, Power Stabilized
0x7F, 0x96, 0xB4, 0x00,
0xB3, 0x91 (200ms Delay Recommended)
So a Pe
Set Multiplex Ratio Enable Gray Scale Table
0xCA, 0x3F 0x00
||
Set Display Offset Set Phase Length
0xA2, 0x00 0xB1, 0xE8
ee ee
**----- End of picture text -----**
If the noise is accidentally occurred at the displaying window during the operation, please reset the display in order to recover the display function.
Page 14 of 22
**==> picture [354 x 64] intentionally omitted <==**
**----- Start of picture text -----**
Function Selection
0xAB, 0x00 Power down VCI/VDDIO
Set Display Off Power down VCC
0xAE (100ms Delay Recommended)
**----- End of picture text -----**
##
**==> picture [427 x 214] intentionally omitted <==**
**----- Start of picture text -----**
Function Selection
0xAB, 0x00
Set Display Off
0xAE Power down VCC
Function Selection Power Stablized
0xAB, 0x01 (200ms Delay Recommended)
Power up VCC & Stabilized Set Display On
(Delay Recommended) 0xAF
**----- End of picture text -----**
Page 15 of 22
|Contents of ReliabilityTests|||
|---|---|---|
||||
|High Temperature Operation
Low Temperature Operation
High Temperature Storage
Low Temperature Storage
High Temperature/Humidity Operation
Thermal Shock|70 C, 240 hrs
-40 C, 240 hrs
85 C, 240 hrs
-40 C, 240 hrs
60 C, 90% RH, 120 hrs
-40 C
85 C, 24 cycles
60 mins dwell|The operational
functions work.|
* The samples used for the above tests do not include polarizer.
* No moisture condensation is observed during tests.
After the completion of the described reliability test, the samples were left at room temperature for 2 hrs prior to conducting the failure test at 23 +.° 5 C; 55 + 15% RH.
Page 16 of 22
Customer’s test & measurement are required to be conducted under the following conditions: Temperature: 23 + 5 fe} C Humidity: 55 + 15% RH Fluorescent Lamp: 30W Distance between the Panel & Lamp: > 50cm Distance between the Panel & Eyes of the Inspector: 30cm Finger glove (or finger cover) must be worn by the inspector. Inspection table or jig must be anti-electrostatic.
Level II, Normal Inspection, Single Sampling, MIL-STD-105E
Major 0.65 Defects in Pattern Check (Display On) Minor 1.0 Defects in Cosmetic Check (Display Off) Cosmetic Check (Display Off) in Non-Active Area ~~| Check item | Classification |[Criteria]~~ X > 6 mm (Along with Edge) Y > 1 mm (Perpendicular to edge) X Y Panel General Chipping Minor X Y ~~mite~~ Page 17 of 22
## Cosmetic Check (Display Off) in Non-Active Area (Continued)
**==> picture [416 x 513] intentionally omitted <==**
**----- Start of picture text -----**
Any crack is not allowable.
Panel Crack Minor
Copper Exposed
Minor Not Allowable by Naked Eye Inspection
(Even Pin or Film)
Film or Trace Damage Minor 4
Terminal Lead Prober Mark Acceptable
fa e
Glue or Contamination on Pin
Minor
(Couldn’t Be Removed by Alcohol) | % x 4 ; “ }
Ink Marking on Back Side of panel
Acceptable Ignore for Any
(Exclude on Film)
**----- End of picture text -----**
Page 18 of 22
Cosmetic Check (Display Off) in Active Area
It is recommended to execute in clear room environment (class 10k) if actual in necessary.
||||
|---|---|---|
|Any Dirt & Scratch on Polarizer’s
Protective Film
Scratches, Fiber, Line-Shape Defect
(On Polarizer)
Dirt, Black Spot, Foreign Material,
(On Polarizer)
Dent, Bubbles, White spot
(Any Transparent Spot on Polarizer)
Fingerprint, Flow Mark
(On Polarizer)|Acceptable
Minor
Minor
Minor
Minor
||Ignore for not Affect the Polarizer
W 0.1
Ignore
W > 0.1
L 2
n 1
L > 2
n = 0
0.1
Ignore
0.25
n 1
n = 0
0.5
Ignore if no Influence on Display
n=0
Not Allowable
<
<
O<
0.1<
0.25 < ©
O<
>
0.5~~<@®~~|
Page 19 of 22
Pattern Check (Display On) in Active Area
|No Display|Major|
|---|---|
|Missing Line|Major|
|Pixel Short|Major|
|Darker Pixel|Major|
|Wrong Display|Major|
|Un-uniform|Major|
Page 20 of 22
- 1) Since the display panel is being made of glass, do not apply mechanical impacts such us dropping from a high position.
- 2) If the display panel is broken by some accident and the internal organic substance leaks out, be careful not to inhale nor lick the organic substance.
- 3) If pressure is applied to the display surface or its neighborhood of the OEL display module, the cell structure may be damaged and be careful not to apply pressure to these sections.
- 4) The polarizer covering the surface of the OEL display module is soft and easily scratched. Please be careful when handling the OEL display module.
- 5) When the surface of the polarizer of the OEL display module has soil, clean the surface. It takes advantage of by using following adhesion tape.
- Scotch Mending Tape No. 810 or an equivalent
Never try to breathe upon the soiled surface nor wipe the surface using cloth containing solvent such as ethyl alcohol, since the surface of the polarizer will become cloudy. Also, pay attention that the following liquid and solvent may spoil the polarizer: * Water
- Ketone
- Aromatic Solvents
- 6) Hold OEL display module very carefully when placing OEL display module into the system housing. Do not apply excessive stress or pressure to OEL display module. And, do not over bend the film with electrode pattern layouts. These stresses will influence the display performance. Also, secure sufficient rigidity for the outer cases.
- 7) Do not apply stress to the driver IC and the surrounding molded sections.
- 8) Do not disassemble nor modify the OEL display module.
- 9) Do not apply input signals while the logic power is off.
- 10) Pay sufficient attention to the working environments when handing OEL display modules to prevent occurrence of element breakage accidents by static electricity.
- Be sure to make human body grounding when handling OEL display modules.
- Be sure to ground tools to use or assembly such as soldering irons.
- To suppress generation of static electricity, avoid carrying out assembly work under dry environments.
- Protective film is being applied to the surface of the display panel of the OEL display module. Be careful since static electricity may be generated when exfoliating the protective film.
- 11) Protection film is being applied to the surface of the display panel and removes the protection film before assembling it. At this time, if the OEL display module has been stored for a long period of time, residue adhesive material of the protection film may remain on the surface of the display panel after removed of the film. In such case, remove the residue material by the method introduced in the above Section 5).
- 12) If electric current is applied when the OEL display module is being dewed or when it is placed under high humidity environments, the electrodes may be corroded and be careful to avoid the above.
- 1) When storing OEL display modules, put them in static electricity preventive bags avoiding exposure to direct sun light nor to lights of fluorescent lamps. and, also, avoiding high temperature and high
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humidity environment or low temperature (less than 0 C) environments. (We recommend you
At that time, be careful not to let water drops adhere to the packages or bags nor let dewing occur with them.
- 2) If electric current is applied when water drops are adhering to the surface of the OEL display module, when the OEL display module is being dewed or when it is placed under high humidity environments, the electrodes may be corroded and be careful about the above.
- 1) The absolute maximum ratings are the ratings which cannot be exceeded for OEL display module, and if these values are exceeded, panel damage may be happen.
- 2) To prevent occurrence of malfunctioning by noise, pay attention to satisfy the VIL and VIH specifications and, at the same time, to make the signal line cable as short as possible.
- 3) We recommend you to install excess current preventive unit (fuses, etc.) to the power circuit (VCI). (Recommend value: 0.5A)
- 4) Pay sufficient attention to avoid occurrence of mutual noise interference with the neighboring devices.
- 5) As for EMI, take necessary measures on the equipment side basically.
- 6) When fastening the OEL display module, fasten the external plastic housing section.
- 7) If power supply to the OEL display module is forcibly shut down by such errors as taking out the main battery while the OEL display panel is in operation, we cannot guarantee the quality of this OEL display module.
- 8) The electric potential to be connected to the rear face of the IC chip should be as follows: SSD1322 * Connection (contact) to any other potential than the above may lead to rupture of the IC.
- 1) Request the qualified companies to handle industrial wastes when disposing of the OEL display modules. Or, when burning them, be sure to observe the environmental and hygienic laws and regulations.
- 1) When an OEL display module is operated for a long of time with fixed pattern may remain as an after image or slight contrast deviation may occur. Nonetheless, if the operation is interrupted and left unused for a while, normal state can be restored. Also, there will be no problem in the reliability of the module.
- 2) To protect OEL display modules from performance drops by static electricity rapture, etc., do not touch the following sections whenever possible while handling the OEL display modules. * Pins and electrodes
- Pattern layouts such as the COF
- 3) With this OEL display module, the OEL driver is being exposed. Generally speaking, semiconductor elements change their characteristics when light is radiated according to the principle of the solar battery. Consequently, if this OEL driver is exposed to light, malfunctioning may occur.
- Design the product and installation method so that the OEL driver may be shielded from light in actual usage.
- Design the product and installation method so that the OEL driver may be shielded from light during the inspection processes.
- 4) Although this OEL display module stores the operation state data by the commands and the indication data, when excessive external noise, etc. enters into the module, the internal status may be changed. It therefore is necessary to take appropriate measures to suppress noise generation or to protect from influences of noise on the system design.
- 5) We recommend you to construct its software to make periodical refreshment of the operation statuses (re-setting of the commands and re-transference of the display data) to cope with catastrophic noise.
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## Links
- [View this product on Novapart](https://novapart.co/products/MCOT256064CY-GM/graphic-oled-256-x-64-pixels-green-on-black-28v)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/midas-displays/mcot256064cy-gm/oled-module-256-x-64-pixel-cot/dp/4685237)
---
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