# Alphanumeric LCD, 20 x 4, White on Blue, 5V, I2C, English, Japanese, Transmissive
**URL**: https://novapart.co/products/MCCOG42005A6W-BNMLWI/alphanumeric-lcd-20-x-4-white-on-blue-5v-i2c
**SKU**: MCCOG42005A6W-BNMLWI
**Manufacturer**: MIDAS DISPLAYS
**Category**: Optoelectronics & Displays || Displays || LCD Displays || Alphanumeric LCD Displays
**Price**: €11.6900
**Stock**: 10+
## Description
Character Count x Line:20 x 4; Display Appearance:White on Blue; Logic Voltage:3V to 5V; Interface Type:I2C; Font Set:English, Japanese; Display Mode:Transmissive; Character Size:4.67
## Specifications
| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| Font Set | English, Japanese |
| Module Size | 74.3mm x 36.4mm |
| Display Mode | Transmissive |
| Logic Voltage | 5V |
| Product Range | MCCOG42005A |
| Character Size | 4.67mm |
| Interface Type | I2C |
| Lcd Display Type | BSTN |
| Display Appearance | White on Blue |
| Backlighting Colour | White |
| Display Construction | COG |
| Character Count X Line | 20 x 4 |
| Operating Temperature Max | 70°C |
| Operating Temperature Min | -20°C |
## Datasheet
📄 [Download PDF](https://novapart.co/datasheet/farnell:2218946/)
Electra House, 32 Southtown Road Great Yarmouth, Norfolk NR31 0DU, England
Telephone +44 (0)1493 602602 Fax +44 (0)1493 665111 Email:sales@midasdisplays.com www.midasdisplays.com
|42005A6W-BNMLWI
~~MCCOG~~
~~P|~~|4 x 20
~~P|~~|4 x 20
~~P|~~|~~5mmCharacter Height~~
~~Po~~|LCD Module
~~Po~~|
|---|---|---|---|---|
|**Specification**
~~MCCOG~~
~~P|~~
~~5mm Character Height~~
~~Po~~|||||
|Version: 1||Date:20/01/2012|||
|**Revision**|||||
||||||
**==> picture [523 x 182] intentionally omitted <==**
**----- Start of picture text -----**
Display Features
Character Count 4 x 20
Appearance White on Blue
Logic Voltage 5V
Interface
Font Set English / Japanese
a Display Mode ew Trans - missive RoHS
Character Height 4.67mm
a ee A a compliant
LC Type STN Blue
Module Size 74.30 x 36.40 x 6.00mm
Operating Temperature -20°C ~ +70°C
COG Construction Box Quantity Weight / Display
LED Backlight White
**----- End of picture text -----**
* - For full design functionality, please use this specification in conjunction with the SSD1803A specification. (Provided Separately)
|**Display Accessories**|||**Optional Variants**|**Optional Variants**||
|---|---|---|---|---|---|
|**Part Number**
**Description**
~~ee~~||**Fonts**||**Appearances**|**Voltage**|
|Fine pitch(1.27mm) COG 12C||||White on Black||
|interfaceboard.Compatible
MCCOG-I2C-I-13|WithbothArduinoandUC32||||Black on White||
## **General Specification**
The Features of the Module is description as follow: Module dimension: 74.3x 36.4 x 6.0 (max.) mm[3] View area: 60.5 x 22.18 mm[2] Active area: 58.5 x 20.18 mm[2] Dot size: 0.45 x0.54 mm2 Dot pitch: 0.5 x 0.59 mm2 Character size: 2.45 x 4.67 Character pitch: 2.95 x 5.17 LCD type: STN Negative, Blue Transmissive, Duty: 1/33DUTY,1/6BIAS View direction: 6 o’clock Backlight Type: LED White
## **Interface Pin Function**
|Pin
No.|Symbol|Description|
|---|---|---|
|1
~~aa~~|/RES
~~aa~~|Reset Pin
~~aa~~|
|2|VOUT|Output of the voltage converter|
|3
~~a~~|V0
~~a~~|Regulated voltage from voltage converter for
LCD driving|
|4
~~Pt~~|V1
~~Pt~~|Bias voltage levels for LCD driving|
|5
~~Pt~~|V2
~~Pt~~||
|6
~~pt~~|V3
~~pt~~||
|7|V4||
|8|VDD|This pin is the power supply for logic circuit (VDD should rise
within 10ms).
In 3V IO application (VDDREG pulled low), this is a power
input pin.
In 5V IO application (VDDREG pulled high), this pin outputs
3V and should be connected with a capacitor to VSS.|
|9
jh|VDDREG
jh|This pin is used to enable VDD regulator in 5V I/O
Application:
Application|
|10|VDDIO|This pin is the power supply for bus IO buffer in both Low
Voltage I/O and 5V I/O application.|
|11
~~a~~|VSS|Ground|
|12|SCL|Thispin is used as clock inputpin in I2C mode.|
|13
~~rr~~|SDA
~~rr~~|This pin is used as data/ acknowledge response output pin in
I2C mode.|
## **Outline Dimension & Block Diagram**
**==> picture [479 x 335] intentionally omitted <==**
**----- Start of picture text -----**
PIN NO SYMBOL
74.3±0.2LB 1 /RES
2 VOUT
1.1 66.1±0.2LCD
6.00±0.3 3 V0
3.9 60.5(VA) 2.80MAX 4 V1
4.9 58.5(AA) 1.10±0.1 5 V2
1.10±0.1 6 V3
7 V4
8 VDD
i j —— t i Tf 9 VDDREG
3.0 10 VDDIO
11 VSS
RECDCEFGHI JELMHOPGRST 1,
RECDEFGHI JELMHOPGEST re 12 SCL13 SDA
RECDEFGHI JELMHOPGRST |
rt RECDCEFGHIJELMHOPRST
y vd 1 13
; 26.53 T t ; P1.27*12=15.24
10.0±0.5
1.15
0.60
0.40
2.45 0.5
0.5
0.45
The non-specified tolerance of dimension is 0.2mm.
L o i
DOT SIZE
SCALE 5/1
1.1 3.86 4.86
2.0
10.7
27.7 K
22.18(VA) 20.18(AA) 15.0
36.4±0.2LB 34.2±0.2LCD A
6.5
3.00±0.2LB
4.67 0.59 0.54
0.5
**----- End of picture text -----**
## **APPLICATION EXAMPLES**
## 1.Application Example I (I2C interface, 3V VDDIO mode)
**==> picture [448 x 145] intentionally omitted <==**
**----- Start of picture text -----**
3V
1
/RES
2
VOUT
3
V0
4
V1
5
V2
6
V3
7
V4
3V 8
VDD
9
VDDREG
10
VDDIO
11
VSS
12
SCL
13
SDA
**----- End of picture text -----**
2.Application Example II (I2C interface, 5V IO mode) . ee 5V 1 /RES 2 (e ~~e~~ VOUT 3 V0 4 V1 5 V2 6 V3 7 V4 8 VDD 9 VDDREG 5V 10 VDDIO 11 VSS e ~~e~~ e 12 ~~e~~ SCL 13 SDA Capacitance =1µF
## **Function Block Descriptions**
## **Busy Flag (BF)**
When BF = "High", it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7. Before executing the next instruction, be sure that BF is not high.
## **Display Data Ram (DDRAM)**
DDRAM stores display data of maximum 80 x 8 bits (80 characters). DDRAM address is set in the address counter (AC) as a hexadecimal number. (Refer to Figure 9-1)
## **Figure -1: DDRAM Address**
## **Display of 5-Dot Font Width Character**
## **5-dot 4-line Display**
In case of 4-line display with 5-dot font, the address range of DDARM is 00H-13H, 20H-33H, 40H-53H, 60H-73H (refer to Figure 9-5).
**Figure -2: 4-line x 20ch. Display (5-dot Font Width)**
## **Timing Generation Circuit**
Timing generation circuit generates clock signals for the internal operations.
## **Address Counter (AC)**
Address Counter (AC) stores DDRAM/ CGRAM/ SEGRAM address, transferred from Instruction Register (IR). After writing into (reading from) DDRAM/ CGRAM/ SEGRAM, AC is automatically increased (decreased) by 1. In parallel and serial mode, when RS = "Low" and R/W = "High", AC can be read through DB0-DB6.
## **Cursor/Blink Control Circuit**
It controls cursor/blink ON/OFF and black/white inversion at cursor position.
## **LCD Driver Circuit**
LCD Driver circuit has 34 common and 100 segment signals for LCD driving. Data from SEGRAM/ CGRAM/ CGROM is transferred to 100-bit segment latch serially, and then it is stored to 100-bit shift latch. When each com is selected by 34-bit common register, segment data also output through segment driver from 100-bit segment latch. In case of 1-line display mode, ICON1/ICON2 and COM1-COM8 have 1/9 duty ratio; and in 4-line mode, ICON1/ICON2 and COM1-COM32 have 1/33 duty ratio.
## **CGROM (Character Generator ROM)**
There is 3 optional CGROMs in SSD1803A in P.66-68 , which is selected by ROM1 and ROM2 pins. CGROM has 5 x 8 dots 256 Character Pattern.
## **CGRAM (Character Generator RAM)**
CGRAM has up to 8 characters of 5 x 8 dots, selectable by OPR2 and OPR1 pins (refer to Table 6-1).
**Table -1: CGRAM and CGROM arrangement with**
By writing font data to CGRAM, user defined character can be used (refer to Table
## 6-2). **Table -2: Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)**
## **5x8 dots Character Pattern**
## **SEGRAM (Segment Icon RAM)**
SEGRAM has segment control data and segment pattern data. During display mode, ICON1 (ICON2) makes the data of SEGRAM enable to display icons. Its higher 2-bit are blinking control data, and lower 6-bits are pattern data (refer to Table 6-3 and Figure 6-3).
**Table -3: Relationship between SEGRAM Address and Display Pattern**
## **Figure -3 Relationship between SEGRAM and Segment Display**
## **System Interface**
This chip has all four kinds of interface type with MPU: I2C, serial, 4-bit bus and 8-bit bus. I2C, Serial and bus (4-bit/8-bit) is selected by IM1 and IM2 inputs, and 4-bit bus and 8-bit bus is selected
by DL bit in the instruction register.
## **I2C interface**
SSD1803A supports I2C interface with a bit rate up to 400 kbits/s. It enables write/ read data or busy flag and supports only the mandatory slave feature showed below.
## **Slaver address could be set to “011 1100” or “011 1101” by SA0 pin.**
The I2C interface send RAM data and executes the commands sent via the I2C Interface. It could send data in to the RAM. The I2C Interface is two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. (Note: SDAin and SDAout are short together and forms SDA in SSD1803A)
## **Bit Transfer**
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Figure 6-4.
## **Start and Stop conditions**
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of
the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Figure 6-5.
## **System Configuration**
The system configuration consists of
- Transmitter: the device, which sends the data to the bus
- Master: the device, which initiates a transfer, generates clock signals and terminates a transfer
- Slave: the device addressed by a master
- Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message
- Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted
- Synchronization: procedure to synchronize the clock signals of two or more devices.
## **Acknowledge**
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C Interface is illustrated in Figure 6-6. **Figure -4: Bit transfer on the I2C-bus**
**Figure -5: START and STOP conditions**
## **Figure -6: Acknowledge on the I2C bus**
## **I2C Interface Protocol**
The SSD1803A supports command, data read/ write addressed slaves on the bus. Before any data is transmitted on the I2C Interface, the device, which should respond, is addressed first. Two 7-bit slave addresses (0111100 to 0111101) are reserved for the SSD1803A. The R/W# is assigned to 0 for Write and 1 for Read. The I2C Interface protocol is illustrated in Figure 6-7 to 6-9.
The sequence is initiated with a START condition (S) from the I2C Interface master, which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C Interface transfer. After acknowledgement, one or more command words follow which define the status of the addressed slaves.
A command word consists of control byte, which defines C0 and D/C#, plus a data byte. The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After the last control byte with a cleared Co bit, only data bytes will follow. The state of the D/C# bit defines whether the data byte is interpreted as a command or as RAM data. All addressed
slaves on the bus also acknowledge the control and data bytes. After the last control byte, depending on the D/C# bit setting; either a series of display data bytes or command data bytes may follow. If the D/C# bit is set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is automatically updated and the data is directed to the intended SSD1803A device. If the D/C# bit of the last control byte is set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the I2C INTERFACE-bus master issues a STOP condition (P).
## **Figure -7: I2C write mode**
**Figure -8: I2C read mode**
**Read busy flag and address/part ID (D/C#=0, R/W#=1)**
**==> picture [158 x 13] intentionally omitted <==**
**----- Start of picture text -----**
Read ram (D/C#=1, R/W#=1)
**----- End of picture text -----**
## **Figure -9: Read Timing**
During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction register (IR). The data register (DR) is used as temporary data storage place for being written into or read from DDRAM/ CGRAM/SEGRAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically.
So to speak, after MPU reads DR data, the data in the next DDRAM/ CGRAM/ SEGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/ CGRAM/ SEGRAM automatically. The Instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use D/C# I2C mode.
## **Table -5: Bus interface operations according to D/C# and R/W# inputs**
## **5V IO regulator**
SSD1803A accepts two power supply range:
## 2.4-3.6V **[Low Voltage I/O Application]** and
## 4.5-5.5V **[5V I/O Application]**
5V IO Regulator is enabled to regulate 5V I/O input to 3V for power supply of internal circuit blocks.
Note: In 5V I/O Application, VOUT should not be lower than VDDIO.
Table 6-6 summarizes the input/ output connection of 5V IO regulator in normal application. **Table -6: 5V IO regulator pin description**
It outputs 3V
## **LCD Driving Voltage Generator and Regulator**
This module generates the LCD voltage required for display driving output. **External VLCD mode**
When on-chip booster is turned off, VLCD can be supplied externally to V0 for display driving. **Figure -10: On-chip voltage converter application set up When booster is off and voltage follower is on (Bon=0; Don=1)**
## **Figure -11: On-chip voltage converter application set up When both booster and voltage follower is off (Bon=0; Don=0)**
## **Internal voltage mode**
## **a) On-chip DC-DC voltage converter**
Voltage converter is available when Bon=1. Figure 6-21 shows the circuits boosting up the electric
potential between VDD – VSS toward positive side and boosted voltage is output at VOUT.
## **Figure -12: On-chip voltage converter application set up When both booster and voltage follower is on (Bon=1; Don=1)**
**Figure -13: On-chip voltage converter application set up When both booster is on and voltage follower is off (Bon=1; Don=0)**
## **b) Voltage regulator circuits (Gain) and Contrast Control**
There is a voltage regulator circuits to determine liquid crystal operating voltage, V0, by adjusting resistors, Ra and Rb, within the range of |V4| < |V0| . The circuits which are turned on with voltage converter consist of an operational-amplifier circuits and a feedback gain control. VOUT is the operating voltage for the op-amp, it is required to supply internally or externally. It consists of a feedback gain control for LCD driving contrast curves, eight settings can be selected through software command (Internal resistor ratio Rab2~0). **Figure -14: Voltage regulator circuit**
Also, software command (C1-5) is used to adjust the 64 contrast voltage levels at each voltage regulator feedback gain. The equation of calculating the LCD driving voltage is given as:
Please refer to Figure 6-24 for the contrast curve with 8 sets of internal resistor network gain.
## **Figure -15: Contrast curve**
## **c) Bias Divider**
If the Don command is enabled, this circuit block will divide the voltage regulator circuit output
(V0) to give the LCD driving levels. External stabilizing capacitors for the divider are optional to reduce the external hardware and pin counts.
## **d) Bias Ratio Selection circuitry**
The software control circuit of 1/4 to 1/7 bias ratio in order to match the characteristic of LCD
panel.
## **e) Self adjust temperature compensation circuitry**
Provide 4 different compensation grade selections to satisfy the various liquid crystal
temperature grades (-0.05%, -0.10%, -0.15%, -0.20%). The grading can be selected by software control. Defaulted temperature coefficient (TC) value is –0.05%/°C.
## **Oscillator Circuit**
This module is an On-Chip low power temperature compensation oscillator circuitry. The oscillator generates the clock for the DC-DC voltage converter and the Display Timing Generator. User may choose to use internal oscillator clock or supply external clock by CLS pin.
## **Optical Characteristics**
|**Item**|**Symbol**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|View Angle|(V)θ|CR
2
≧|20|－|40|deg|
||(H)φ|CR
2
≧|-30|－|30|deg|
|Contrast Ratio|CR|－|－|3|－|－|
|Response Time|T rise|－|－|350|500|ms|
||T fall|－|－|150|200|ms|
## **Definition of Operation Voltage, Vop. Definition of Response Time, Tr and Tf.**
**==> picture [385 x 149] intentionally omitted <==**
**----- Start of picture text -----**
Non-selected Non-selected
Intensity Selected Wave Conition Selected Conition Conition
100％ Non-selected Wave
Intensity
10％
Cr Max
Cr = Lon / Loff 90％
100％
Vop
Driving Voltage(V) Tr Tf
[positive type] [positive type]
**----- End of picture text -----**
## **Conditions:**
Operating Voltage : Vop Viewing Angle(θ ， φ) : 0° ， 0° Frame Frequency: 64 HZ Driving Waveform: 1/N duty, 1/a bias
**==> picture [340 x 190] intentionally omitted <==**
**----- Start of picture text -----**
Definition of viewing angle (CR ≧ 2)
θ b
θ f °
φ= 180
θl
θr
φ= 270° φ= 90°
φ= 0°
**----- End of picture text -----**
**Absolute Maximum Ratings**
**Item Symbol Min Typ Max Unit** Operating Temperature TOP -20 － +70 ℃ － Storage Temperature TST -30 +80 ℃ － Power Supply Voltage VDD -0.3 6.0 V LCD Driver Voltage VLCD -0.3 － 15.0 V Input Voltage VIN -0.3 － VDD+0.3 V ~~me~~
## **Electrical Characteristics**
|**Item**|**Symbol**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Supply Voltage For Logic|VDDIO|Low Voltage
I/O App.|2.4|3.0|VDD|V|
|||5V I/O App.|4.5|5.0|5.5|V|
||VDD|－|2.4|3.0|3.6|V|
|Supply Voltage For LCD|VO-VSS|Ta=-20℃
Ta=25℃
Ta=70℃|－
－
－|－
7.8
－|－
－
－|V
V
V|
|Input High Volt.|VIH|－|0.8 VDDIO|－|VDDIO|V|
|Input Low Volt.|VIL|－|－|－|0.2 VDDIO|V|
|Output High Volt.|VOH|－|0.8 VDDIO|－|VDDIO|V|
|Output Low Volt.|VOL|－|－|－|0.2 VDDIO|V|
|SupplyLCM current|IDD|VDD=5.0V|－|1.0|－|mA|
## **Backlight Information**
## **Specification**
|**PARAMETER**|**SYMBOL MIN**|**SYMBOL MIN**|**TYP**|**MAX**|**UNIT**|**TEST** **CONDITION**|
|---|---|---|---|---|---|---|
|**Supply Current ILED**|**Supply Current ILED**|**43.2**|**48**|**60**|**mA**|**V= 3.5 V**|
|**Supply Voltage V**|**Supply Voltage V**|**3.4**|**3.5**|**3.6**|**V**|－|
|**Reverse Voltage VR**|**Reverse Voltage VR**|－|－|**5**|**V**|－|
|**Luminous**
**Intensity**
**(Without LCD)**|**IV**|**400**|**500**|－|**CD/M2**|**ILED=48 mA**|
|**Chromaticity**|**x**|－|**0.30**|－|－|－|
||**y**|－|**0.29**|－|－|－|
|**LED Life Time**|－||**50K**||**Hr.**|**ILED**
**48**
≦
**mA**|
|**Color**|**White**||||||
**Note: The LED of B/L is drive by current only** ； **driving voltage is only for reference**
**To make driving current in safety area (waste current between minimum and maximum).**
## **Reliability**
## **Content of Reliability Test (wide temperature, -20** ℃ **~70** ℃ **)**
|**Content of Reliability Test (wide temperature, -20y Test (wide temperature, -20 Test (wide temperature, -20(wide temperature, -20wide temperature, -20perature, -20erature, -20**℃**~70**℃**)**|**Content of Reliability Test (wide temperature, -20y Test (wide temperature, -20 Test (wide temperature, -20(wide temperature, -20wide temperature, -20perature, -20erature, -20**℃**~70**℃**)**|**Content of Reliability Test (wide temperature, -20y Test (wide temperature, -20 Test (wide temperature, -20(wide temperature, -20wide temperature, -20perature, -20erature, -20**℃**~70**℃**)**|**Content of Reliability Test (wide temperature, -20y Test (wide temperature, -20 Test (wide temperature, -20(wide temperature, -20wide temperature, -20perature, -20erature, -20**℃**~70**℃**)**|
|---|---|---|---|
|**Environmental Test**||||
|**Test Item**|**Content of Test**|**Condition Note**|**Condition Note**|
|High Temperature storage|Endurance test applying the high storage temperature for a long
time.|Endurance test applying the high storage temperature for a long
80℃
200hrs|2|
|Low Temperature storage|Endurance test applying the high storage temperature for a long
time.|Endurance test applying the high storage temperature for a long
-30℃
200hrs|1,2|
|High Temperature Operation|Endurance test applying the electric stress (Voltage & Current)
and the thermal stress to the element for a long time.|Endurance test applying the electric stress (Voltage & Current)
70℃
200hrs|-|
|Low Temperature Operation|Endurance test applying the electric stress under low
temperature for a long time.|Endurance test applying the electric stress under low
-20℃
200hrs|1|
|High Temperature/
Humidity Operation|The module should be allowed to stand at 60℃,90%RH max
For 96hrs under no-load condition excluding the polarizer,
Then taking it out and drying it at normal temperature.|60℃,90%RH
96hrs|1,2|
|Thermal shock resistance|The sample should be allowed stand the following 10 cycles of
operation
-20℃25℃70℃
30min 5min 30min
1 cycle|-20℃/70℃
10 cycles|-|
|Vibration test|Endurance test applying the vibration during transportation and
using.|Endurance test applying the vibration during transportation and
fixed
amplitude:
15mm
Vibration.
Frequency:
10~55Hz.
One cycle 60
seconds to 3
directions of
X,Y,Z for
Each 15
minutes|3|
|Static electricity test|Endurance test applying the electric stress to the terminal.|VS=800V,RS=
1.5kΩ
CS=100pF
1 time|——|
## **Note1: No dew condensation to be observed.**
**Note2: The function test shall be conducted after 4 hours storage at the normal temperature and humidity after remove from the test chamber.**
**Note3: Vibration test will be conducted to the product itself without putting it in a container.**
**Inspection specification** NO Item Criterion AQL 1.1 Missing vertical, horizontal segment, segment contrast defect. 1.2 Missing character, dot or icon. 1.3 Display malfunction. Electrical 01 1.4 No function or no display. 0.65 Testing 1.5 Current consumption exceeds product specifications. 1.6 LCD viewing angle defect. 1.7 Mixed product types. 1.8 Contrast defect. 2.1 White and black spots on display ≦ 0.25mm, no more Black or than three white or black spots present. white spots 02 2.2 Densely spaced: No more than two spots or lines within 2.5 on LCD 3mm (display only) 3.1 Round type : As following drawing Φ=( x + y ) / 2 ~~Lt |~~ 2.5 LCD black spots, white spots, 03 contaminatio n 3.2 Line type : (As following drawing) (non-display) Length Width Acceptable Q TY --W ≦ 0.02 Accept no 2.5 dense L ≦ 3.0 0.02 ＜ W ≦ 0.03 2 L ≦ 2.5 0.03 ＜ W ≦ 0.05 ~~[ee==~~ --0.05 ＜ W As round type If bubbles are visible, Size Φ Acceptable Q judge using black spot TY specifications, not Φ ≦ 0.20 Accept no Polarizer 04 easy to find, must dense 2.5 bubbles check in specify 0.20 ＜ Φ ≦ 0.50 3 direction. 0.50 ＜ Φ ≦ 1.00 2 1.00 ＜ Φ 0 Total Q TY 3 in ~~m==~~
|NO
~~a~~|Item|Criterion|AQL|
|---|---|---|---|
|05
~~a~~|Scratches
~~ee~~|Follow NO.3 LCD black spots, white spots, contamination
~~ee~~|~~ee~~|
|06
~~a~~|Chipped
glass
~~ee~~|z: Chip thickness
y: Chip width
x: Chip length
Z≦1/2t
Not over viewing
area
x≦1/8a
1/2t＜z≦2t
Not exceed 1/3k
x≦1/8a
☉If there are 2 or more chips, x is the total length of each chip.
Symbols Define:
x: Chip length y: Chip width z: Chip thickness
k: Seal width t: Glass thickness a: LCD side length
L: Electrode pad length:
6.1 General glass chip :
6.1.1 Chip on panel surface and crack between panels:
z: Chip thickness
y: Chip width
x: Chip length
Z≦1/2t
Not over viewing
area
x≦1/8a
1/2t＜z≦2t
Not exceed 1/3k
x≦1/8a
☉If there are 2 or more chips, x is total length of each chip.
6.1.2 Corner crack:
~~ee~~
LEE|2.5
~~ee~~|
|NO
~~a~~|Item|Criterion|AQL|
|---|---|---|---|
|06|Glass
crack|Symbols :
x: Chip length y: Chip width z: Chip thickness
k: Seal width t: Glass thickness a: LCD side length
L: Electrode pad length
6.2 Protrusion over terminal :
6.2.1 Chip on electrode pad :
y: width
x: length
y≦1/3L
x≦a
y: Chip width
x: Chip length
z: Chip thickness
y≦0.5mm
x≦1/8a
0＜z≦t
y≦L
x≦1/8a
0＜z≦t
☉If the chipped area touches the ITO terminal, over 2/3 of the
ITO must remain and be inspected according to electrode
terminal specifications.
☉If the product will be heat sealed by the customer, the
alignment mark not be damaged.
6.2.3 Substrate protuberance and internal crack.
Z
L
Ie
a
‘i
_¥el
si
Z
K
X
MS|2.5|
|NO|Item|Criterion|AQL|
|---|---|---|---|
|07|Cracked
glass|The LCD with extensive crack is not acceptable.|2.5|
|08|Backlight
elements|8.1 Illumination source flickers when lit.
8.2 Spots or scratched that appear when lit must be judged.
Using LCD spot, lines and contamination standards.
8.3 Backlight doesn’t light or color wrong.|0.65
2.5
0.65|
|09|Bezel|9.1 Bezel may not have rust, be deformed or have
fingerprints, stains or other contamination.
9.2 Bezel must comply with job specifications.|2.5
0.65|
|10|PCB、COB|**X**
**X* Y<=2mm2**
10.1 COB seal may not have pinholes larger than 0.2mm or
contamination.
10.2 COB seal surface may not have pinholes through to the
IC.
10.3 The height of the COB should not exceed the height
indicated in the assembly diagram.
10.4 There may not be more than 2mm of sealant outside
the seal area on the PCB. And there should be no more
than three places.
10.5 No oxidation or contamination PCB terminals.
10.6 Parts on PCB must be the same as on the production
characteristic chart. There should be no wrong parts,
missing parts or excess parts.
10.7 The jumper on the PCB should conform to the product
characteristic chart.
10.8 If solder gets on bezel tab pads, LED pad, zebra pad or
screw hold pad, make sure it is smoothed down.
10.9 The Scraping testing standard for Copper Coating of
PCB
**Y**|2.5
2.5
0.65
2.5
2.5
0.65
0.65
2.5
2.5|
|11|Soldering|11.1 No un-melted solder paste may be present on the PCB.
11.2 No cold solder joints, missing solder connections,
oxidation or icicle.
11.3 No residue or solder balls on PCB.
11.4 No short circuits in components on PCB.|2.5
2.5
2.5
0.65|
|NO|Item|Criterion|AQL|
|---|---|---|---|
|12|General
appearance|12.1 No oxidation, contamination, curves or, bends on
interface Pin (OLB) of TCP.
12.2 No cracks on interface pin (OLB) of TCP.
12.3 No contamination, solder residue or solder balls on
product.
12.4 The IC on the TCP may not be damaged, circuits.
12.5 The uppermost edge of the protective strip on the
interface pin must be present or look as if it causes the
interface pin to sever.
12.6 The residual rosin or tin oil of soldering (component or
chip component) is not burned into brown or black color.
12.7 Sealant on top of the ITO circuit has not hardened.
12.8 Pin type must match type in specification sheet.
12.9 LCD pin loose or missing pins.
12.10 Product packaging must the same as specified on
packaging specification sheet.
12.11 Product dimension and structure must conform to
product specification sheet.|2.5
0.65
2.5
2.5
2.5
2.5
2.5
0.65
0.65
0.65
0.65|
## **Precautions in use of LCD Modules**
1. Avoid applying excessive shocks to the module or making any alterations or modifications to it.
2. Don’t make extra holes on the printed circuit board, modify its shape or change the components of LCD module.
3. Don’t disassemble the LCM.
4. Don’t operate it above the absolute maximum rating.
5. Don’t drop, bend or twist LCM.
6. Soldering: only to the I/O terminals.
7. Storage: please storage in anti-static electricity container and clean environment.
8. Midas have the right to change the passive components
- (Resistors,capacitors and other passive components will have different appearance and color caused by the different supplier.)
9. Midas have the right to change the PCB Rev.
## **Material List of Components for RoHs**
1. Midas Components Ltd. hereby declares that all of or part of products, including, but not limited to, the LCM, accessories or packages, manufactured and/or delivered to your company (including your subsidiaries and affiliated company) directly or indirectly by our company (including our subsidiaries or affiliated companies) do not intentionally contain any of the substances listed in all applicable EU directives and regulations, including the following substances.
Exhibit A ： The Harmful Material List
|Material|(Cd)|(Pb)|(Hg)|(Cr6+)|PBBs|PBDEs|
|---|---|---|---|---|---|---|
|Limited
Value|100
ppm|1000
ppm|1000
ppm|1000
ppm|1000
ppm|1000
ppm|
|Above limited value is set upaccordingto RoHS.|||||||
2. Process for RoHS requirement ：
- (1) Use the Sn/Ag/Cu soldering surface ； the surface of Pb-free solder is rougher than we used before.
- (2) Heat-resistance temp. ：
- Reflow ： 250 ℃ , 30 seconds Max. ； Connector soldering wave or hand soldering ： 320 ℃ , 10 seconds max.
- (3) Temp. curve of reflow, max. Temp. ： 235±5 ℃；
Recommended customer’s soldering temp. of connector ： 280 ℃ , 3 seconds.
## **Recommendable storage**
1. Place the panel or module in the temperature 25°C±5°C and the humidity below 65% RH
2. Do not place the module near organics solvents or corrosive gases.
3. Do not crush, shake, or jolt the module
## Links
- [View this product on Novapart](https://novapart.co/products/MCCOG42005A6W-BNMLWI/alphanumeric-lcd-20-x-4-white-on-blue-5v-i2c)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/midas-displays/mccog42005a6w-bnmlwi/lcd-cog-20x4-i2c-bstn-white-on/dp/2218946)
---
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