# Voltage Controlled Oscillator, 1.1 GHz, 4.2 V to 5.5 V, TSSOP-8, -40 °C to 85 °C
**URL**: https://novapart.co/products/MC100EL1648DTR2G/voltage-controlled-oscillator-11-ghz-42-v-to-55
**SKU**: MC100EL1648DTR2G
**Manufacturer**: ONSEMI
**Category**: Semiconductors - ICs || Clock,Timing & Frequency Management || Timers, Oscillators & Pulse Generators
**Price**: €6.2200
**Stock**: 10+
## Specifications
| Parameter | Value |
|---|---|
| Frequency | 1.1GHz |
| No. Of Pins | 8Pins |
| Digital Ic Case | TSSOP |
| Supply Voltage Max | 5.5V |
| Supply Voltage Min | 4.2V |
| Operating Temperature Max | 85°C |
| Operating Temperature Min | -40°C |
## Datasheet
📄 [Download PDF](https://novapart.co/datasheet/farnell:3610844/)
**DATA SHEET www.onsemi.com**
## 5 V ECL Voltage Controlled Oscillator Amplifier MC100EL1648
## **Description**
The MC100EL1648 is a voltage controlled oscillator amplifier that requires an external parallel tank circuit consisting of the inductor (L) and capacitor (C). A varactor diode may be incorporated into the tank circuit to provide a voltage variable input for the oscillator (VCO). This device may also be used in many other applications requiring a fixed frequency clock.
The MC100EL1648 is ideal in applications requiring a local oscillator, systems that include electronic test equipment, and digital high−speed telecommunications.
The MC100EL1648 is based on the VCO circuit topology of the MC1648. The MC100EL1648 uses advanced bipolar process technology which results in a design which can operate at an extended frequency range.
The ECL output circuitry of the MC100EL1648 is not a traditional open emitter output structure and instead has an on−chip termination emitter resistor, RE, with a nominal value of 510 �. This facilitates direct ac−coupling of the output signal into a transmission line. Because of this output configuration, an external pull−down resistor is not required to provide the output with a dc current path. This output is intended to drive one ECL load (3.0 pF). If the user needs to fanout the signal, an ECL buffer such as the EL16 (EL11, EL14) type Line Receiver/Driver should be used.
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8
8
1
1
SOIC−8 NB TSSOP−8
D SUFFIX DT SUFFIX
CASE 751−07 CASE 948R−02
**----- End of picture text -----**
## **MARKING DIAGRAMS***
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8 8
K1648 1648
ALYW ALYW �
�
�
1 1
SOIC−8 NB TSSOP−8
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
� = Pb−Free Package
**----- End of picture text -----**
(Note: Microdot may be in either location)
*For additional marking information, refer to Application Note AND8002/D.
## **ORDERING INFORMATION**
See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.
## **Features**
- Typical Operating Frequency Up to 1100 MHz
- Low−Power 19 mA at 5.0 Vdc Power Supply
- PECL Mode Operating Range: VCC = 4.2 V to 5.5 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.5 V
- Input Capacitance = 6.0 pF (TYP)
- These are Pb−Free Devices
NOTE: The MC100EL1648 is NOT useable as a crystal oscillator.
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VCC VCC
BIAS POINT
EXTERNAL
TANK TANK OUTPUT
CIRCUIT
VEE VEE AGC
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**Figure 1. Logic Diagram**
Publication Order Number: **MC100EL1648/D**
**1**
© Semiconductor Components Industries, LLC, 2008 **October, 2024 − Rev. 10**
**MC100EL1648**
**Table 1. PIN DESCRIPTION**
|Á
**Á**
**Á**
**Á**
**Á**
**Á**
Á|**Pin No.**
|**Symbol**
|**Description**
|
|---|---|---|---|
||ÁÁ
**ÁÁ**
1
|ÁÁ
**ÁÁ**
TANK|ÁÁÁÁÁÁÁÁÁ
**ÁÁÁÁÁÁÁÁÁ**
OSC Input Voltage|
||2, 3
|VCC|Positive Supply|
||**ÁÁ**
4
|**ÁÁ**
OUT|**ÁÁÁÁÁÁÁÁÁ**
ECL Output|
||**ÁÁ**
**ÁÁ**
5
|**ÁÁ**
**ÁÁ**
AGC|**ÁÁÁÁÁÁÁÁÁ**
**ÁÁÁÁÁÁÁÁÁ**
Automatic Gain Control Input|
||6, 7
|VEE|Negative Output|
||**ÁÁ**
8
|**ÁÁ**
BIAS|**ÁÁÁÁÁÁÁÁÁ**
OSC Input Reference Voltage|
||ÁÁ
|ÁÁ||
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BIAS VEE VEE AGC
8 7 6 5
1 2 3 4
TANK VCC VCC OUT
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
**----- End of picture text -----**
## **Figure 2. Pinout Assignments**
**Table 2. ATTRIBUTES**
|**Table 2. ATTRIBUTES**||
|---|---|
|**Characteristic**|**Value**|
|Internal Input Pulldown Resistor|N/A|
|Internal Input Pullup Resistor|N/A|
|ESD Protection
Human Body Model
Machine Model
Charged Device Model|> 1 kV
> 100 V
> 1 kV|
|Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)|Pb−Free Pkg|
|SOIC−8
TSSOP−8|Level 1
Level 3|
|Flammability Rating
Oxygen Index: 23 to 34|UL 94 V−0 @ 0.125 in|
|Transistor Count|11|
|Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test||
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
**Table 3. MAXIMUM RATINGS**
|**Symbol**|**Parameter**|**Condition 1**|**Condition 2**|**Rating**|**Unit**|
|---|---|---|---|---|---|
|VCC|Power Supply PECL Mode|VEE= 0 V||7 to 0|V|
|VEE|Power Supply NECL Mode|VCC= 0 V||−7 to 0|V|
|VI|PECL Mode Input Voltage
NECL Mode Input Voltage|VEE= 0 V
VCC= 0 V|VI ≤VCC
VI ≥VEE|6 to 0
−6 to 0|V
V|
|Iout|Output Current|Continuous
Surge||50
100|MA
mA|
|TA|Operating Temperature Range|||−40 to +85|°C|
|Tstg|Storage Temperature Range|||−65 to +150|°C|
|�JA|Thermal Resistance (Junction−to−Ambient)|0 lfpm
500 lfpm|SOIC−8
SOIC−8|190
130|°C/W
°C/W|
|�JC|Thermal Resistance (Junction−to−Case)|Standard Board|SOIC−8|41 to 44|°C/W|
|�JA|Thermal Resistance (Junction−to−Ambient)|0 lfpm
500 lfpm|TSSOP−8
TSSOP−8|185
140|°C/W
°C/W|
|�JC|Thermal Resistance (Junction−to−Case)|Standard Board|TSSOP−8|41 to 44|°C/W|
|Tsol|Wave Solder|<2 to 3 sec @ 260°C||265|°C|
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
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**2**
**MC100EL1648**
**Table 4. PECL DC CHARACTERISTICS** VCC = 5.0 V; VEE = 0.0 V +0.8 / −0.5 V (Note 2)
|**Symbol**|**Characteristic**||**−40**°**C**|||**25**°**C**|||**85**°**C**||**Unit**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|||**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**||
|IEE|Power Supply Current|13|19|25|13|19|25|13|19|25|mA|
|VOH|Output HIGH Voltage (Note 3)|3950|4170|4610|3950|4170|4610|3950|4170|4610|mV|
|VOL|Output LOW Voltage (Note 3)|3040|3410|3600|3040|3410|3600|3040|3410|3600|mV|
|AGC|Automatic Gain Control Input|1690||1980|1690||1980|1690||1980|mV|
|VBIAS|Bias Voltage (Note 4)|1650||1800|1650||1800|1650||1800|mV|
|VIL||1.5|||1.35|||1.2|||V|
|VIH||||2.0|||1.85|||1.7|V|
|IL|Input Current||−5.0|||−5.0|||−5.0||mA|
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 2. Output parameters vary 1:1 with VCC. 3. 1.0 M � impedance.
4. This measurement guarantees the dc potential at the bias point for purposes of incorporating a varactor tuning diode at this point.
**Table 5. NECL DC CHARACTERISTICS** VCC = 0.0 V; VEE = −5.0 V +0.8 / −0.5 V (Note 5)
|**Symbol**|**Characteristic**||**−40**°**C**|||**25**°**C**|||**85**°**C**||**Unit**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|||**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**||
|IEE|Power Supply Current|13|19|25|13|19|25|13|19|25|mA|
|VOH|Output HIGH Voltage (Note 6)|−1050|−830|−399|−1050|−830|−399|−1050|−830|−399|mV|
|VOL|Output LOW Voltage (Note 6)|−1960|−1590|−1400|−1960|−1590|−1400|−1960|−1590|−1400|mV|
|AGC|Automatic Gain Control Input|−3310||−3020|−3310||−3020|−3310||−3020|mV|
|VBIAS|Bias Voltage (Note 7)|−3350||−3200|−3350||−3200|−3350||−3200|mV|
|VIL||−3.5|||−3.65|||−3.8|||V|
|VIH||||−3.0|||−3.15|||−3.3|V|
|IL|Input Current||−5.0|||−5.0|||−5.0||mA|
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm.
5. Output parameters vary 1:1 with VCC. 6. 1.0 M � impedance.
7. This measurement guarantees the dc potential at the bias point for purposes of incorporating a varactor tuning diode at this point.
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**3**
**MC100EL1648**
## **GENERIC TEST CIRCUITS: BYPASS TO SUPPLY OPPOSITE GND**
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VCC
0.1 � F 0.1 � F
3 2
8
VIN 4 (3) ** FOUT
C L
1 K � * L = Micro Metal torroid #T20−22, 8 turns #30
Tank #1 1 Enameled Copper wire (@ 40 nH)
C = MMBV609
6 7 5
VEE * Use high impedance probe
(>1.0 M � must be used).
100 � F 0.01 � F 0.1 � F 0.1 � F ** The 1200 � resistor and the scope termination
impedance constitute a 25:1 attenuator probe.
Coax shall be CT−070−50 or equivalent.
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Tank Circuit Option #1, Varactor Diode
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VCC
0.1 � F 0.1 � F
8 3 2 L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
4 (3) C = 3.0−35pF Variable Capacitance (@ 10 pF)
0.1 � F L C FOUT
Note 1 Capacitor for tank may be variable type.
(See Tank Circuit #3.)
Test Point Tank #2 1 Note 2 Use high impedance probe (> 1 M � ).
6 7 5
VEE
100 � F 0.01 � F 0.1 � F 0.1 � F
Tank Circuit Option #2, Fixed LC
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**Figure 3. Typical Test Circuit with Alternate Tank Circuits**
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VP-P 50%
ta PRF = 1.0MHz
tb Duty Cycle (Vdc) - [t] tb [a]
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**Figure 4. Output Waveform**
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**4**
**MC100EL1648**
## **OPERATION THEORY**
Figure 5 illustrates the simplified circuit schematic for the MC100EL1648. The oscillator incorporates positive feedback by coupling the base of transistor Q6 to the collector of Q7. An automatic gain control (AGC) is incorporated to limit the current through the emitter−coupled pair of transistors (Q7 and Q6) and allow optimum frequency response of the oscillator. In order to maintain the high quality factor (Q) on the oscillator, and provide high spectral purity at the output, transistor Q4 is used to translate the oscillator signal to the output differential pair Q2 and Q3. Figure 16 indicates the high spectral purity of the oscillator output (pin 4 on 8−pin SOIC). Transistors
Q2 and Q3, in conjunction with output transistor Q1, provide a highly buffered output that produces a square wave. The typical output waveform can be seen in Figure 4. The bias drive for the oscillator and output buffer is provided by Q9 and Q11 transistors. In order to minimize current, the output circuit is realized as an emitter−follower buffer with an on chip pull−down resistor RE.
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VCC 2 VCC 3
800 � 1.36 K � 3.1 K � 660 � 167 �
Q9 Q1
Q3 Q2
1.6 K �
OUTPUT
4
Q4
Q11 Q10 Q7 Q6
D1
330 �
Q5
400 � D2 Q8
16 K � 82 � 400 � 660 � 510 �
VEE BIAS TANK VEE AGC
7 8 1 6 5
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**Figure 5. Circuit Schematic**
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**5**
**MC100EL1648**
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30
Measured Frequency (MHz)
25
Calculated Frequency (MHz)
20
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
15 C = 3.0−35 pF Variable Capacitance (@ 10 pF)
* The 1200 � resistor and the scope termination
10 impedance constitute a 25:1 attenuator probe.
Coax shall be CT−070−50 or equivalent.
5
0
0 300 500 1000 2000 10000 0.1 � F 10 � F
CAPACITANCE (pF) 2 3
8
1200*
0.1 � F L C
4
SIGNAL
1 UNDER
Tank #3 TEST
6 7 5
VEE
100 � F 0.01 � F 0.1 � F 0.1 � F
FREQUENCY (MHz)
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**Figure 6. Low Frequency Plot**
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100
80
60 L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = 3.0−35 pF Variable Capacitance (@ 10 pF)
40
* The 1200 � resistor and the scope termination
impedance constitute a 25:1 attenuator probe.
20 Coax shall be CT−070−50 or equivalent.
Measured Frequency (MHz)
Calculated Frequency (MHz)
0
0 0.2 0.3 300
0.1 � F 10 � F
CAPACITANCE (pF) 2 3
8
1200*
0.1 � F L C
4
SIGNAL
1 UNDER
Tank #3 TEST
6 7 5
VEE
100 � F 0.01 � F 0.1 � F 0.1 � F
FREQUENCY (MHZ)
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**Figure 7. High Frequency Plot**
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**6**
**MC100EL1648**
## **FIXED FREQUENCY MODE**
The MC100EL1648 external tank circuit components are used to determine the desired frequency of operation as shown in Figure 8, tank option #2. The tank circuit components have direct impact on the tuning sensitivity, IEE, and phase noise performance. Fixed frequency of the tank circuit is usually realized by an inductor and capacitor (LC network) that contains a high Quality factor (Q). The plotted curve indicates various fixed frequencies obtained with a single inductor and variable capacitor. The Q of the components in the tank circuit has a direct impact on the resulting phase noise of the oscillator. In general, when the Q is high the oscillator will result in lower phase noise.
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570
470 Measured Frequency (MHz)
Calculated Frequency (MHz)
370
270
170
70
0
−30
0.3 300 500 1000 2000 10000
CAPACITANCE (pF)
VCC
0.1 � F 0.1 � F
3 2
8
4
0.1 � F L C
FOUT
1
Test Tank #2
Point 6 7 5
VEE
100 � F 0.01 � F 0.1 � F 0.1 � F
FREQUENCY (MHz)
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- L = Micro Metal torroid #T20−22, 8 turns #30 Enameled Copper wire (@ 40 nH)
- C = 3.0−35 pF Variable Capacitance (@ 10 pF) Note 1 Capacitor for tank may be variable type. (See Tank Circuit #3.)
Note 2 Use high impedance probe (> 1 M � ).
- QL ≥ 100
**Figure 8. Fixed Frequency LC Tank**
Only high quality surface−mount RF chip capacitors should be used in the tank circuit at high frequencies. These
capacitors should have very low dielectric loss (high−Q). At a minimum, the capacitors selected should be operating at 100 MHz below their series resonance point. As the desired frequency of operation increases, the values of the tank capacitor will decrease since the series resonance point is a function of the capacitance value. Typically, the inductor is realized as a surface−mount chip or a wound coil. In addition, the lead inductance and board inductance and capacitance also have an impact on the final operating point. The following equation will help to choose the appropriate values for your tank circuit design.
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Where LT = Total Inductance
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Figure 9 and Figure 10 represent the ideal curve of inductance/capacitance versus frequency with one known tank component. This helps the designer of the tank circuit to choose desired value of inductor/capacitor component for the wanted frequency. The lead inductance and board inductance and capacitance will also have an impact on the tank component values (inductor and capacitor).
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50
45
40
35
30
25 Inductance vs. Frequency with 5 pF Cap
20
15
10
5
0
400 700 1000 1300 160
FREQUENCY (MHz)
Figure 9. Capacitor Value Known (5 pF)
50
45
40
35
30 Capacitance vs. Frequency with 4 nH Inductance
25
20
15
10
5
0
400 700 1000 1300 160
FREQUENCY (Hz)
INDUCTANCE (nH)
CAPACITANCE (F)
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**Figure 10. Inductor Value Known (4 nH)**
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**7**
**MC100EL1648**
## **VOLTAGE CONTROLLED MODE**
The tank circuit configuration presented in Figure 11, Voltage Controlled Varactor Mode, allows the VCO to be tuned across the full operating voltage of the power supply. Deriving from Figure 6, the tank capacitor, C, is replaced with a varactor diode whose capacitance changes with the voltage applied, thus changing the resonant frequency at which the VCO tank operates as shown in Figure 3, tank option #1. The capacitive component in Equation 1 also needs to include the input capacitance of the device and other circuit and parasitic elements.
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190
170
150
130
110
90
70
50
0 2 4 6 8 10
Vin, INPUT VOLTAGE (V)
FREQUENCY (MHz)
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Figure 12. Plot 1. Dual Varactor MMBV609,
VIN vs. Frequency
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VCC
0.1 � F 0.1 � F
3 (1) 2
8 (10)
VIN 4 (3)
C L *
1 K �
Tank #1 1 (12)
6 (7) 7 (8) 5 (5) **
VEE
100 � F 0.01 � F 0.1 � F 0.1 � F FOUT
**----- End of picture text -----**
- *Use high impedance probe ~~(>1~~ .0 Meg � must be used). **The 1200 � resistor and the scope termination impedance constitute a 25:1 attenuator probe. Coax shall be CT−070−50 or equivalent.
When operating the oscillator in the voltage controlled mode with Tank Circuit #1 (Figure 3), it should be noted that the cathode of the varactor diode (D), pin 8 (for 8 lead package) or pin 10 (for 14 lead package) should be biased at least 1.4 V above VEE.
Typical transfer characteristics employing the capacitance of the varactor diode (plus the input capacitance of the device, about 6.0 pF typical) in the voltage controlled mode is shown in Plot 1, Dual Varactor MMBV609 Vin vs. Frequency. Figure 6, Figure 7, and Figure 8 show the accuracy of the measured frequency with the different variable capacitance values. The 1.0 k� resistor in Figure 11 is used to protect the varactor diode during testing. It is not necessary as long as the dc input voltage does not cause the diode to become forward biased. The tuning range of the oscillator in the voltage controlled mode may be calculated as follows:
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Where
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Where
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Good RF and low−frequency bypassing is necessary on the device power supply pins. Capacitors on the AGC pin and the input varactor trace should be used to bypass the AGC point and the VCO input (varactor diode), guaranteeing only dc levels at these points. For output frequency operation between 1.0 MHz and 50 MHz, a 0.1 �F capacitor is sufficient. At higher frequencies, smaller values of capacitance should be used; at lower frequencies, larger values of capacitance. At high frequencies, the value of bypass capacitors depends directly on the physical layout of the system. All bypassing should be as close to the package pins as possible to minimize unwanted lead inductance. Several different capacitors may be needed to bypass various frequencies.
- L = Micro Metal torroid #T20−22, 8 turns #30 Enameled Copper wire (@ 40 nH)
- C = MMBV609
**Figure 11. Voltage Controlled Varactor Mode**
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**8**
**MC100EL1648**
## **WAVE−FORM CONDITIONING − SINE OR SQUARE WAVE**
The peak−to−peak swing of the tank circuit is set internally by the AGC pin. Since the voltage swing of the tank circuit provides the drive for the output buffer, the AGC potential directly affects the output waveform. If it is desired to have a sine wave at the output of the MC100EL1648, a series resistor is tied from the AGC point to the most negative power potential (ground if positive volt supply is used, −5.2 V if a negative supply is used) as shown in
Figure 13. At frequencies above 100 MHz typical, it may be desirable to increase the tank circuit peak−to−peak voltage in order to shape the signal into a more square waveform at the output of the MC100EL1648. This is accomplished by tying a series resistor (1.0 k� minimum) from the AGC to the most positive power potential (+5.0 V if a positive volt supply is used, ground if a −5.2 V supply is used). Figure 14 illustrates this principle.
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+5.0Vdc
1 14
10
3 Output
12 5
7 8
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+5.0Vdc
1 14
10
3 Output
1.0k min
12 5
7 8
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**Figure 13. Method of Obtaining a Sine−Wave Output**
**Figure 14. Method of Extending the Useful Range of the MC100EL1648** (Square Wave Output)
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**9**
**MC100EL1648**
## **SPECTRAL PURITY**
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99.8 99.9 100.0 100.1 100.2
B.W. = 10 kHz, Center Frequency = 100 MHz
Scan Width = 50 kHz/div, Vertical Scale = 10 dB/div
10 dB / DEC
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**Figure 15. Spectral Purity**
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0.1 � F 10 � F
2 3
8
1200*
0.1 � F L C
4
SIGNAL
1 UNDER L = Micro Metal torroid #T20−22, 8 turns #30
Tank #3 TEST Enameled Copper wire (@ 40 nH)
VEE 6 7 5 C = 3.0−35 pF Variable Capacitance (@ 10 pF)
** The 1200 � resistor and the scope termination
100 � F 0.01 � F 0.1 � F 0.1 � F impedance constitute a 25:1 attenuator probe. Coax shall be CT−070−50 or equivalent.
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Spectral Purity Test Circuit
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**Figure 16. Spectral Purity of Signal Output for 200 MHz Testing**
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Q Zo = 50 � D
Driver Receiver
Device Device
Q Z o = 50 � D
50 � 50 �
VTT
VTT = VCC − 2.0 V
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**Figure 17. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.)**
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**10**
**MC100EL1648**
## **ORDERING INFORMATION**
|**Device**|**Package**|**Shipping**†|
|---|---|---|
|MC100EL1648DG|SOIC−8 NB
(Pb−Free)|2500 / Tape & Reel|
|MC100EL1648DTR2G|TSSOP−8
(Pb−Free)|2500 / Tape & Reel|
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
## **Resource Reference of Application Notes**
**AN1405/D** − ECL Clock Distribution Techniques **AN1406/D** − Designing with PECL (ECL at +5.0 V) **AN1503/D** − ECLinPS � I/O SPiCE Modeling Kit **AN1504/D** − Metastability and the ECLinPS Family
**AN1568/D** − Interfacing Between LVDS and ECL
- **AN1672/D** − The ECL Translator Guide
**AND8001/D**
- Odd Number Counters Design
**AND8002/D** − Marking and Date Codes
- **AND8020/D** − Termination of ECL Logic Devices **AND8066/D** − Interfacing with ECLinPS **AND8090/D** − AC Characteristics of ECL Devices
ECLinPS is a trademark of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries.
**www.onsemi.com**
**11**
MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS**
**==> picture [34 x 28] intentionally omitted <==**
**----- Start of picture text -----**
8
1
**----- End of picture text -----**
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**----- Start of picture text -----**
SCALE 1:1
**----- End of picture text -----**
**SOIC−8 NB** CASE 751−07 ISSUE AK
**==> picture [79 x 7] intentionally omitted <==**
**----- Start of picture text -----**
DATE 16 FEB 2011
**----- End of picture text -----**
**==> picture [471 x 425] intentionally omitted <==**
**----- Start of picture text -----**
NOTES:
−X− 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
C N X 45 � B 3.80 4.00 0.150 0.157
SEATING C 1.35 1.75 0.053 0.069
PLANE D 0.33 0.51 0.013 0.020
−Z− G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
0.10 (0.004) J 0.19 0.25 0.007 0.010
H D M J MK 0.400 � 1.278 � 0.0160 � 0.0508 �
N 0.25 0.50 0.010 0.020
0.25 (0.010) M Z Y S X S S 5.80 6.20 0.228 0.244
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8 8 8 8
XXXXX XXXXX XXXXXX XXXXXX
1.52 ALYWX ALYWX � AYWW AYWW �
0.060
1 1 1 1
IC IC Discrete Discrete
(Pb−Free) (Pb−Free)
7.0 4.0
XXXXX = Specific Device Code XXXXXX = Specific Device Code
0.275 0.155
A = Assembly Location A = Assembly Location
L = Wafer Lot Y = Year
Y = Year WW = Work Week
W = Work Week � = Pb−Free Package
� = Pb−Free Package
0.6 1.270 *This information is generic. Please refer to
0.024 0.050 device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ � ”, may
or may not be present. Some products may
SCALE 6:1
� inches [mm] � not follow the Generic Marking.
**----- End of picture text -----**
- *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ � ”, may or may not be present. Some products may not follow the Generic Marking.
*For additional information on our Pb−Free strategy and soldering details, please download the **onsemi** Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
## **STYLES ON PAGE 2**
Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42564B** Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **DESCRIPTION: SOIC−8 NB PAGE 1 OF 2**
**onsemi** and are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others.
www.onsemi.com
© Semiconductor Components Industries, LLC, 2019
**SOIC−8 NB** CASE 751−07 ISSUE AK
**==> picture [79 x 7] intentionally omitted <==**
**----- Start of picture text -----**
DATE 16 FEB 2011
**----- End of picture text -----**
|STYLE 1:|STYLE 1:|STYLE 2:||STYLE 3:|STYLE 3:||STYLE 4:|STYLE 4:|
|---|---|---|---|---|---|---|---|---|
|PIN 1.|EMITTER|PIN 1.|COLLECTOR, DIE, #1|PIN 1.||DRAIN, DIE #1|PIN 1.|ANODE|
|2.|COLLECTOR|2.|COLLECTOR, #1|2.||DRAIN, #1|2.|ANODE|
|3.|COLLECTOR|3.|COLLECTOR, #2|3.||DRAIN, #2|3.|ANODE|
|4.|EMITTER|4.|COLLECTOR, #2|4.||DRAIN, #2|4.|ANODE|
|5.|EMITTER|5.|BASE, #2|5.||GATE, #2|5.|ANODE|
|6.|BASE|6.|EMITTER, #2|6.||SOURCE, #2|6.|ANODE|
|7.|BASE|7.|BASE, #1|7.||GATE, #1|7.|ANODE|
|8.|EMITTER|8.|EMITTER, #1|8.||SOURCE, #1|8.|COMMON CATHODE|
|STYLE 5:||STYLE 6:||STYLE 7:|||STYLE 8:||
|PIN 1.|DRAIN|PIN 1.|SOURCE|PIN 1.||INPUT|PIN 1.|COLLECTOR, DIE #1|
|2.|DRAIN|2.|DRAIN|2.||EXTERNAL BYPASS|2.|BASE, #1|
|3.|DRAIN|3.|DRAIN|3.||THIRD STAGE SOURCE|3.|BASE, #2|
|4.|DRAIN|4.|SOURCE|4.||GROUND|4.|COLLECTOR, #2|
|5.|GATE|5.|SOURCE|5.||DRAIN|5.|COLLECTOR, #2|
|6.|GATE|6.|GATE|6.||GATE 3|6.|EMITTER, #2|
|7.|SOURCE|7.|GATE|7.||SECOND STAGE Vd|7.|EMITTER, #1|
|8.|SOURCE|8.|SOURCE|8.||FIRST STAGE Vd|8.|COLLECTOR, #1|
|STYLE 9:||STYLE 10:||STYLE 11:|||STYLE 12:||
|PIN 1.|EMITTER, COMMON|PIN 1.|GROUND|PIN 1.||SOURCE 1|PIN 1.|SOURCE|
|2.|COLLECTOR, DIE #1|2.|BIAS 1|2.||GATE 1|2.|SOURCE|
|3.|COLLECTOR, DIE #2|3.|OUTPUT|3.||SOURCE 2|3.|SOURCE|
|4.|EMITTER, COMMON|4.|GROUND|4.||GATE 2|4.|GATE|
|5.|EMITTER, COMMON|5.|GROUND|5.||DRAIN 2|5.|DRAIN|
|6.|BASE, DIE #2|6.|BIAS 2|6.||DRAIN 2|6.|DRAIN|
|7.|BASE, DIE #1|7.|INPUT|7.||DRAIN 1|7.|DRAIN|
|8.|EMITTER, COMMON|8.|GROUND|8.||DRAIN 1|8.|DRAIN|
|STYLE 13:||STYLE 14:||STYLE 15:|||STYLE 16:||
|PIN 1.|N.C.|PIN 1.|N−SOURCE|PIN 1.|ANODE 1||PIN 1.|EMITTER, DIE #1|
|2.|SOURCE|2.|N−GATE|2.|ANODE 1||2.|BASE, DIE #1|
|3.|SOURCE|3.|P−SOURCE|3.|ANODE 1||3.|EMITTER, DIE #2|
|4.|GATE|4.|P−GATE|4.|ANODE 1||4.|BASE, DIE #2|
|5.|DRAIN|5.|P−DRAIN|5.|CATHODE, COMMON||5.|COLLECTOR, DIE #2|
|6.|DRAIN|6.|P−DRAIN|6.|CATHODE, COMMON||6.|COLLECTOR, DIE #2|
|7.|DRAIN|7.|N−DRAIN|7.|CATHODE, COMMON||7.|COLLECTOR, DIE #1|
|8.|DRAIN|8.|N−DRAIN|8.|CATHODE, COMMON||8.|COLLECTOR, DIE #1|
|STYLE 17:||STYLE 18:||STYLE 19:|||STYLE 20:||
|PIN 1.|VCC|PIN 1.|ANODE|PIN 1.||SOURCE 1|PIN 1.|SOURCE (N)|
|2.|V2OUT|2.|ANODE|2.||GATE 1|2.|GATE (N)|
|3.|V1OUT|3.|SOURCE|3.||SOURCE 2|3.|SOURCE (P)|
|4.|TXE|4.|GATE|4.||GATE 2|4.|GATE (P)|
|5.|RXE|5.|DRAIN|5.||DRAIN 2|5.|DRAIN|
|6.|VEE|6.|DRAIN|6.||MIRROR 2|6.|DRAIN|
|7.|GND|7.|CATHODE|7.||DRAIN 1|7.|DRAIN|
|8.|ACC|8.|CATHODE|8.||MIRROR 1|8.|DRAIN|
|STYLE 21:||STYLE 22:||STYLE 23:|||STYLE 24:||
|PIN 1.|CATHODE 1|PIN 1.|I/O LINE 1|PIN 1.||LINE 1 IN|PIN 1.|BASE|
|2.|CATHODE 2|2.|COMMON CATHODE/VCC|2.||COMMON ANODE/GND|2.|EMITTER|
|3.|CATHODE 3|3.|COMMON CATHODE/VCC|3.||COMMON ANODE/GND|3.|COLLECTOR/ANODE|
|4.|CATHODE 4|4.|I/O LINE 3|4.||LINE 2 IN|4.|COLLECTOR/ANODE|
|5.|CATHODE 5|5.|COMMON ANODE/GND|5.||LINE 2 OUT|5.|CATHODE|
|6.|COMMON ANODE|6.|I/O LINE 4|6.||COMMON ANODE/GND|6.|CATHODE|
|7.|COMMON ANODE|7.|I/O LINE 5|7.||COMMON ANODE/GND|7.|COLLECTOR/ANODE|
|8.|CATHODE 6|8.|COMMON ANODE/GND|8.||LINE 1 OUT|8.|COLLECTOR/ANODE|
|STYLE 25:||STYLE 26:||STYLE|27:||STYLE 28:||
|PIN 1.|VIN|PIN 1.|GND|PIN 1.||ILIMIT|PIN 1.|SW_TO_GND|
|2.|N/C|2.|dv/dt|2.||OVLO|2.|DASIC_OFF|
|3.|REXT|3.|ENABLE|3.||UVLO|3.|DASIC_SW_DET|
|4.|GND|4.|ILIMIT|4.||INPUT+|4.|GND|
|5.|IOUT|5.|SOURCE|5.||SOURCE|5.|V_MON|
|6.|IOUT|6.|SOURCE|6.||SOURCE|6.|VBULK|
|7.|IOUT|7.|SOURCE|7.||SOURCE|7.|VBULK|
|8.|IOUT|8.|VCC|8.||DRAIN|8.|VIN|
|STYLE 29:||STYLE 30:|||||||
|PIN 1.|BASE, DIE #1|PIN 1.|DRAIN 1||||||
|2.|EMITTER, #1|2.|DRAIN 1||||||
|3.|BASE, #2|3.|GATE 2||||||
|4.|EMITTER, #2|4.|SOURCE 2||||||
|5.|COLLECTOR, #2|5.|SOURCE 1/DRAIN 2||||||
|6.|COLLECTOR, #2|6.|SOURCE 1/DRAIN 2||||||
|7.|COLLECTOR, #1|7.|SOURCE 1/DRAIN 2||||||
|8.|COLLECTOR, #1|8.|GATE 1||||||
Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42564B** Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **DESCRIPTION: SOIC−8 NB PAGE 2 OF 2**
**onsemi** and are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others.
**www.onsemi.com**
~~**2**~~
www.onsemi.com
© Semiconductor Components Industries, LLC, 2019
MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS**
**TSSOP−8 3.00x3.00x0.95** CASE 948R−02 ISSUE A
**SCALE 2:1**
DATE 07 APR 2000
**==> picture [459 x 195] intentionally omitted <==**
**----- Start of picture text -----**
8x REFK NOTES:
0.15 (0.006) T U S 0.10 (0.004) M T U S V S 1. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
2X L/2 8 5 PROTRUSIONS OR GATE BURRS. MOLD FLASH
B 0.25 (0.010) OR GATE BURRS SHALL NOT EXCEED 0.15
L −U− 4. (0.006) PER SIDE.DIMENSION B DOES NOT INCLUDE INTERLEAD
1 4 M FLASH OR PROTRUSION. INTERLEAD FLASH OR
PIN 1IDENT PROTRUSION SHALL NOT EXCEED 0.25 (0.010)PER SIDE.
0.15 (0.006) T U S A 5. TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.
−V− F 6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
DETAIL E
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 2.90 3.10 0.114 0.122
C B 2.90 3.10 0.114 0.122
C 0.80 1.10 0.031 0.043
−T− 0.10 (0.004) SEATINGPLANE D G −W− GDF 0.050.400.65 BSC0.150.700.400.65 BSC0.150.700.65 BSC0.150.70 0.0020.0160.026 BSC0.0060.0280.0160.026 BSC0.0060.0280.026 BSC0.0060.028
K 0.25 0.40 0.010 0.016
DETAIL E L 4.90 BSC 0.193 BSC
**----- End of picture text -----**
2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
**==> picture [119 x 101] intentionally omitted <==**
**----- Start of picture text -----**
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 2.90 3.10 0.114 0.122
B 2.90 3.10 0.114 0.122
C 0.80 1.10 0.031 0.043
DFF 0.150.700.70 0.0060.0280.028
GDF 0.050.400.65 BSC0.150.700.400.65 BSC0.150.700.65 BSC0.150.70 0.0020.0160.026 BSC0.0060.0280.0160.026 BSC0.0060.0280.026 BSC0.0060.028
K 0.25 0.40 0.010 0.016
L 4.90 BSC 0.193 BSC
M 0 � 6 � 0 � 6 �
**----- End of picture text -----**
**==> picture [493 x 37] intentionally omitted <==**
**----- Start of picture text -----**
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON00236D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: TSSOP−8 3.00x3.00x0.95 PAGE 1 OF 1
**----- End of picture text -----**
**onsemi** and are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others.
www.onsemi.com
© Semiconductor Components Industries, LLC, 2019
**onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** ’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
## **ADDITIONAL INFORMATION**
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**==> picture [232 x 43] intentionally omitted <==**
## Links
- [View this product on Novapart](https://novapart.co/products/MC100EL1648DTR2G/voltage-controlled-oscillator-11-ghz-42-v-to-55)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/en-ES/on-semiconductor/mc100el1648dtr2g/voltage-controlled-oscillator/dp/3610844)
---
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