LTM4652IY#PBF

DC/DC Converter, Buck, Micro Module, 0.6 to 18 V in, 0.6 to 7.5 V/25 A out, BGA-144

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Manufacturer: ANALOG DEVICES
Product type: DC / DC Non Isolated Board Mount Converters - Adjustable Output
SVHC: No SVHC (04-Feb-2026)
Depth: 16mm
Width: 16mm
Height: 4.92mm
Topology: Buck (Step Down)
No. of Pins: 144Pins
Product Range: LTM4652 Series
No. of Outputs: 2 Output
Output Current: 25A
Output Power Max: -
Input Voltage Max: 18V
Input Voltage Min: 4.5V
Output Current Max: 50A
Output Voltage Max: 7.5V
Output Voltage Min: 600mV
Switching Frequency: 780kHz
Input Voltage DC Max: 18V
Input Voltage DC Min: 4.5V
DC / DC Converter Type: BGA-144, Micro Module
DC / DC Converter IC Case: BGA
Operating Temperature Max: 125°C
Power Supply Applications: ITE & Industrial
DC / DC Converter Output Type: Adjustable
Delivery and price
Units per pack	180
Price	80.92 €
Current stock	50+
Lead time	30 days
Datasheet
LTM4652 

## Source/Sink Dual ±25A or Single ±50A µModule Regulator with Input Overvoltage Protection 

## **FEATURES** 

## **DESCRIPTION** 

- n **Dual ±25A or Single ±50A Output Source/Sink** 

- n **Input Voltage Range: 4.5V to 18V (20V Abs Max)** 

- n **Output Voltage Range: 0.6V to 7.5V (8V Abs Max)** 

- n **±1.5% Maximum Total DC Output Error Over Line, Load and Temperature** 

- n **Adjustable Control Loop Compensation** 

- n **Differential Remote Sense Amplifier** 

- n **Current Mode Control/Fast Transient Response** 

- n **Multiphase Parallel Current Sharing Up to ±300A** 

- n **Internal Temperature Monitor** 

- n Adjustable Switching Frequency or Synchronization 

- n Overcurrent Foldback Protection 

- n Selectable Pulse-Skipping Mode Operation 

- n Soft-Start/Voltage Tracking 

- n Input and Output Overvoltage Protection 

- n 16mm × 16mm × 4.92mm BGA Package 

## **APPLICATIONS** 

- n Test and Measurement Instrumentation 

- n Telecom and Networking Equipment 

The LTM[®] 4652 is a source/sink dual ±25A or single ±50A output switching mode step-down DC/DC µModule[®] (micromodule) regulator with ±1.5% total DC output error. Included in the package are the switching controllers, power MOSFETs, inductors and all supporting components. Operating from an input voltage range of 4.5V to 18V, the LTM4652 supports two outputs with an output voltage range of 0.6V to 7.5V, each set by a single external resistor. Its high efficiency design delivers up to ±25A continuous current for each output. Only a few input and output capacitors are needed. Adjustable control loop compensation allows for fast transient response to minimize output capacitance when powering FPGAs, ASICs, and processors. 

Fault protection features include input and output overvoltage and bidirectional overcurrent protection. The LTM4652 is offered in a 16mm × 16mm × 4.92mm BGA package. 

All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066 and 6580258. Other patents pending. 

- n Industrial Equipment 

## **TYPICAL APPLICATION** 

**±50A, 3.3V Bidirectional Output DC/DC µModule Regulator with Input Overvoltage Protection** 

**3.3VOUT Efficiency vs IOUT** 

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100<br>10k<br>INTVCC PGOOD 98<br>4.7µF<br>4.5V TO 18VVIN 22µF25V 845k VIN INTVCC PGOOD1 PGOOD2VVOUTS1OUT1 100µF + 470µF V3.3V±50AOUT 9694<br>6.3V 6.3V 92<br>×4 VINOVP DIFFOUT<br>TRACK1 VFB1 90<br>TRACK2<br>0.1µF fSET LTM4652 VFB2 13.3k 88<br>86<br>140k COMP1<br>RTH COMP2 84<br>PINS UNUSED IN  CTH RUN1RUN2 VDIFFPOUT2 100µF6.3V + 470µF6.3V 8280 5V12V IN IN<br>PHASMD DIFFN –50 –40 –30 –20 –10 0 10 20 30 40 50<br>THIS APPLICATION:<br>CLKOUT, EXTVCC,  SGND GND MODE_PLLIN OUTPUT CURRENT (A) 4652 TA01b<br>SW1, SW2, VOUTS2,   4652 TA01a<br>TEMP [+] , TEMP [–]<br>EFFICIENCY (%)<br>**----- End of picture text -----**<br>


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Rev. A<br>**----- End of picture text -----**<br>


1 

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Document Feedback 

## LTM4652 

## **ABSOLUTE MAXIMUM RATINGS** 

## **PIN CONFIGURATION** 

## **(Note 1)** 

VIN ............................................................. –0.3V to 20V PGOOD1, PGOOD2, RUN1, RUN2, INTVCC, EXTVCC........................................... –0.3V to 6V MODE_PLLIN, fSET, TRACK1, TRACK2, DIFFOUT, PHASMD ...............................–0.3V to INTVCC VOUT1, VOUT2, VOUTS1, VOUTS2 (Note 5) ........ –0.3V to 8V DIFFP, DIFFN, VINOVP ...........................–0.3V to INTVCC COMP1, COMP2, VFB1, VFB2 (Note 5) ........ –0.3V to 2.7V INTVCC Peak Output Current ..................................50mA Internal Operating Temperature Range (Note 2) .................................................. –40°C to 125°C Storage Temperature Range .................. –55°C to 125°C Peak Package Body Temperature .......................... 245°C 

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TOP VIEW<br>M<br>VIN<br>L<br>VIN VIN<br>K GND<br>TEMP [+] EXTVCC<br>J<br>VINOVP TEMP [–] INTVCC<br>H<br>SW1 PHASMD CLKOUT PGOOD2 PGOOD1 SW2<br>G<br>MODE_ SGND<br>PLLIN RUN1 DIFFOUT RUN2<br>F<br>GND TRACK1 COMP1 COMP2 DIFFP DIFFN<br>E<br>VFB1 SGND VFB2 TRACK2 GND<br>D<br>VOUTS1 fSET SGND VOUTS2<br>C<br>B<br>VOUT1 GND VOUT2<br>A<br>1 2 3 4 5 6 7 8 9 10 11 12<br>BGA PACKAGE<br>144-LEAD (16mm × 16mm × 4.92mm)<br>TJMAX = 125°C, θJA = 7°C/W, θJCtop = 5.8°C/W, θJCbot = 1.7°C/W, WEIGHT = 3.8 GRAMS<br>NOTES: 1) θ VALUES ARE DETERMINED BY SIMULATION PER JESD51 CONDITIONS.<br>2) θJA VALUE IS OBTAINED WITH DEMO BOARD.<br>3) REFER TO APPLICATION INFORMATION SECTION FOR LAB MEASUREMENT<br>AND DERATING INFORMATION.<br>**----- End of picture text -----**<br>


## **ORDER INFORMATION** 

|**PART NUMBER**|**PAD OR BALL FINISH**|**PART MARKING**|**PART MARKING**|**PACKAGE TYPE**|**MSL RATING**|**TEMPERATURE**<br>**RANGE (NOTE 2)**|
|---|---|---|---|---|---|---|
|||**DEVICE**|**FINISH CODE**||||
|LTM4652EY#PBF|SAC305 (RoHS)|LTM4652Y|e1|BGA|4|–40°C to 125°C|
|LTM4652IY#PBF|||||||



- Contact the factory for parts specified with wider operating temperature ranges. Pad or ball finish code is per IPC/JEDEC J-STD-609. 

- Recommended LGA and BGA PCB Assembly and Manufacturing Procedures 

- LGA and BGA Package and Tray Drawings 

Rev. A 

2 

For more information www.analog.com 

LTM4652 

## **ELECTRICAL CHARACTERISTICS** 

**The** l **denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel (Note 3). TA = 25°C (Note 2), VIN = 12V, VRUN1, VRUN2 at 5V and IOUT1, IOUT2 at 0A unless otherwise noted. Per the typical application in Figure 31.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|VIN|Input DC Voltage||l|4.5<br>18|V|
|VOUT|Output Voltage||l|0.6<br>7.5|V|
|VOUT1(DC), VOUT2(DC)|Output Voltage, Total DC Variation<br>with Line and Load (Note 7)|CIN= 22µF ×3, COUT= 100µF ×1 Ceramic,<br>470µF POSCAP, VIN= 4.5V to 18V,<br>VOUT= 1.2V, IOUT= 0A to ±25A|l|1.182<br>1.2<br>1.218|V|
|**Input Specifications**||||||
|VRUN1, VRUN2|RUN Pin Off Threshold|RUN Rising||1.1<br>1.22<br>1.4|V|
|VRUN1HYS, VRUN2HYS|RUN Pin On Hysteresis|||135|mV|
|VVINOVP|VINOVP Pin OVP Inception Threshold|VINOVP Rising||1.1<br>1.22<br>1.4|V|
|VOVP_HYS|VINOVP Pin OVP Inception Hysteresis|||10|mV|
|IINRUSH(VIN)|Input Inrush Current at Start-Up|IOUT= 0A, CIN= 22µF ×3, CSS= 0.01µF,<br>COUT= 100µF ×3, VOUT1= 1.2V, VOUT2= 1.2V,<br>VIN= 12V||1|A|
|IQ(VIN)|Input Supply Bias Current (Both<br>Channels On)|VIN= 12V, VOUT= 1.2V, Pulse-Skipping Mode<br>VIN= 12V, VOUT= 1.2V, Switching Continuous<br>Shutdown, RUN = 0, VIN= 12V||22<br>135<br>35|mA<br>mA<br>µA|
|IS(VIN)|Input Supply Current|VIN= 4.5V, VOUT= 1.2V, IOUT= 25A<br>VIN= 12V, VOUT= 1.2V, IOUT= 25A<br>VIN= 4.5V, VOUT= 1.2V, IOUT= –25A<br>VIN= 12V, VOUT= 1.2V, IOUT= –25A||8.0<br>3.0<br>–5.2<br>–1.9|A<br>A<br>A<br>A|
|**Output Specifications**||||||
|IOUT1(DC), IOUT2(DC)|Output Continuous Current Range|VIN= 12V, VOUT= 1.2V(Note 6)||–25<br>25|A|
|ΔVOUT1(LINE)/VOUT1<br>ΔVOUT2(LINE)/VOUT2|Line Regulation Accuracy|For Each Output, VOUT= 1.2V, IOUT= 0A,<br>VINfrom 4.5V to 18V|l|0.02<br>0.1|%/V|
|ΔVOUT1/VOUT1<br>ΔVOUT2/VOUT2|Load Regulation Accuracy|For Each Output, VIN= 12V, VOUT= 1.2V,<br>IOUTfrom 0A to ±25A|l|0.2<br>0.75|%|
|VOUT1(AC), VOUT2(AC)|Output Ripple Voltage|For Each Output, VIN= 12V, VOUT= 1.2V,<br>Frequency = 450kHz, IOUT= 0A, COUT=<br>100µF ×3 Ceramic, 470µF POSCAP||15|mVP-P|
|fSW (Each Channel)|Output Ripple Voltage Frequency|VIN= 12V, VOUT= 1.2V, fSET= 1.2V(Note 4)||500|kHz|
|fSYNC(Each Channel)|Phase-Locked Loop Synchronization<br>Capture Range|(Note 4)||400<br>750|kHz|
|ΔVOUTSTART<br>(Each Channel)|Turn-On Overshoot|COUT= 100µF ×3 Ceramic, 470µF POSCAP,<br>VIN= 12V , VOUT= 1.2V, IOUT= 0A||10|mV|
|tSTART<br>(Each Channel)|Turn-On Time|COUT= 100µF ×4 Ceramic,<br>VIN= 12V, No Load, TRACK with 0.01µF to GND||5|ms|
|ΔVOUT(LS)<br>(Each Channel)|Peak Deviation for Dynamic Load|Load: 0% to 50% to 0% of Full Load,<br>COUT= 100µF ×3 Ceramic, 470µF POSCAP,<br>VIN= 12V, VOUT= 1.2V(Note 8)||30|mV|
|tSETTLE<br>(Each Channel)|Settling Time for Dynamic Load Step|Load: 0% to 50% to 0% of Full Load,<br>VIN= 12V, COUT= 100µF ×3 Ceramic,<br>470µF POSCAP(Note 8)||20|µs|
|IOUT(PK) (Each Channel)|Output Current Limit|VIN= 12V, VOUT= 1.2V||35|A|



Rev. A 

3 

For more information www.analog.com 

## LTM4652 

## **ELECTRICAL CHARACTERISTICS** 

**The** l **denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel (Note 3). TA = 25°C (Note 2), VIN = 12V, VRUN1, VRUN2 at 5V and IOUT1, IOUT2 at 0A unless otherwise noted. Per the typical application in Figure 31.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|**Control Section**||||||
|VFB1, VFB2|Voltage at VFBPins|IOUT= 0A, VOUT= 1.2V|l|0.594<br>0.600<br>0.606|V|
|IFB||(Note 5)||–5<br>–30|nA|
|VOVL|Feedback Overvoltage Lockout||l|0.64<br>0.66<br>0.68|V|
|ITRACK1, ITRACK2|Track Pin Soft-Start Pull-Up Current|TRACK1, TRACK2 Start at 0V||1<br>1.25<br>1.5|µA|
|UVLO|Undervoltage Lockout(Falling)|||3.4|V|
|UVLO Hysteresis||||0.6|V|
|tON(MIN)|Minimum On-Time|(Note 5)||90|ns|
|RFBHI1, RFBHI2|Resistor Between VOUTS1, VOUTS2and<br>VFB1, VFB2Pins for Each Output|||60.05<br>60.4<br>60.75|kΩ|
|VPGOOD1, VPGOOD2Low|PGOOD Voltage Low|IPGOOD= 2mA||0.1<br>0.3|V|
|IPGOOD|PGOOD Leakage Current|VPGOOD= 5V||±5|µA|
|VPGOOD|PGOOD Trip Level|VFBwith Respect to Set Output Voltage<br>VFBRamping Negative<br>VFBRamping Positive||–10<br>10|%<br>%|
|**INTVCC Linear Regulator**||||||
|VINTVCC|Internal VCCVoltage|6V < VIN< 18V||4.75<br>5<br>5.2|V|
|VINTVCCLoad Regulation|INTVCCLoad Regulation|ICC= 0mA to 50mA||0.5<br>2|%|
|VEXTVCC|EXTVCCSwitchover Voltage|EXTVCCRamping Positive||4.5<br>4.7|V|
|VEXTVCC(DROP)|EXTVCCDropout|ICC= 20mA, VEXTVCC= 5V||50<br>100|mV|
|VEXTVCC(HYST)|EXTVCCHysteresis|||220|mV|
|**Oscillator**||||||
|Frequency Nominal|Nominal Frequency|fSET= 1.2V||450<br>500<br>550|kHz|
|Frequency Low|Lowest Frequency|fSET= 0.93V<br>fSET= 0V(Note 5)||400<br>250|kHz<br>kHz|
|Frequency High|Highest Frequency|fSET> 2.4V, Up to INTVCC||780|kHz|
|fSET|Frequency Set Current|||8.5<br>9.5<br>11|µA|
|RMODE_PLLIN|MODE_PLLIN Input Resistance|||250|kΩ|
|CLKOUT|Phase (Relative to VOUT1)|PHASMD = GND<br>PHASMD = Float<br>PHASMD = INTVCC||60<br>90<br>120|Deg<br>Deg<br>Deg|
|CLK High<br>CLK Low|Clock High Output Voltage<br>Clock Low Output Voltage|||2<br>0.4|V<br>V|
|**Differential Amplifier**||||||
|AVDifferential Amp|Gain|||1|V/V|
|RIN|Input Resistance|Measured at DIFFP Input||80|kΩ|
|VOS|Input Offset Voltage|VDIFFP= VDIFFOUT= 1.5V, IDIFFOUT= 100µA||3|mV|
|PSRR Differential Amp|Power Supply Rejection Ratio|4.5V < VIN< 18V||90|dB|
|ICL|Maximum Output Current|||3|mA|



Rev. A 

4 

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LTM4652 

**ELECTRICAL CHARACTERISTICS The** l **denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel (Note 3). TA = 25°C (Note 2), VIN = 12V, VRUN1, VRUN2 at 5V and IOUT1, IOUT2 at 0A unless otherwise noted. Per the typical application in Figure 31.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|VOUT(MAX)|Maximum Output Voltage|IDIFFOUT= 300µA||INTVCC– 1.4|V|
|GBW|Gain Bandwidth Product|||3|MHz|
|�VTEMP|Diode Connected PNP|ITEMP+= 100µA, ITEMP–= –100µA||0.6|V|
|TC|Temperature Coefficient||l|–2.2|mV/C|
|η|Ideality Factor|||1.004||



**Note 1:** Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 

**Note 2:** The LTM4652 is tested under pulsed-load conditions such that TJ ≈ TA. The LTM4652E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4652I is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. 

**Note 3:** Two outputs are tested separately and the same testing condition is applied to each output. 

**Note 4:** The LTM4652 device is designed to operate best from 400kHz to 780kHz. For some applications such as 1VOUT, operation at 300kHz is acceptable—but not ATE-tested in production. 

**Note 5:** These parameters are tested at wafer sort. 

**Note 6:** See output current derating curve for different ambient temperature. 

**Note 7:** Total DC output voltage error includes all errors over temperature—reference, line and load regulation as well as the tolerance of the integrated top feedback resistor. 

**Note 8:** Transient response and load step performance are layout dependent and thus application-specific. Typical values are reported from lab Demo Board evaluation. Evaluation in application demonstrates capability. 

Rev. A 

5 

For more information www.analog.com 

LTM4652 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

## **TA = 25°C, unless otherwise noted.** 

**Pulse-Skipping Mode Efficiency VIN = 12V, VOUT = 1.2V,  IN = 12V, VOUT = 1.2V,  = 12V, VOUT = 1.2V,  OUT = 1.2V,  = 1.2V, fS = 400kHz, Outputs ParalleledS = 400kHz, Outputs Paralleled = 400kHz, Outputs Paralleled** 

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Efficiency vs Output Current,   Efficiency vs Output Current,   VIN = 12V, VOUT = 1.2V,  IN = 12V, VOUT = 1.2V,  = 12V, VOUT = 1.2V,  OUT = 1.2V,  = 1.2V,<br>VIN = 5V, Outputs Paralleled VIN = 12V, Outputs Paralleled fS = 400kHz, Outputs ParalleledS = 400kHz, Outputs Paralleled = 400kHz, Outputs Paralleled<br>100 100 100<br>98 Pt tT ET Tt TY 98 Pt Tt tT ty yy 90 SU TMTTT<br>96 | | TT ey 96 Pt tT tT Ty tt 80 A<br>94 perme 94 70 A el<br>92 pd beast | feeste]tet 92 p ertt | | | oy 60 CTILUTE CUTTT AT A ATT UTil<br>90 Nl a 90 a ee 50 CUT TTVATA<br>88 C7Zee\:\: 88 40 UT<br>86 Yi | | ag) | aN| IN 86 aiCAIN ee|  a| TNS 30 CTT TUTETI AUTVA TTEA T HiUT<br>84 eee | ines 84 Z| Ng gt | 20 CUTITI TZA LAI ETN TTT<br>8280 SER)SREei ine| ine 8280 SeeP| | Ma 1 inne| 100 UNCON LL et ATI an ETN<br>–50 –40 –30 –20 –10 0 10 20 30 40 50 –50 –40 –30 –20 –10 0 10 20 30 40 50 0.001 0.01 0.1 1 10 100<br>LOAD CURRENT (A) LOAD CURRENT (A) MAGNITUDE OF OUTPUT CURRENT (A)<br>4652 G01 4652 G02 4652 G03<br>1.0VOUT, 300kHz 1.8VOUT, 500kHz 1.0VOUT, 300kHz 2.5VOUT, 500kHz PULSE-SKIPPING MODE, SOURCING CURRENT<br>1.2VOUT, 400kHz 2.5VOUT, 500kHz 1.2VOUT, 400kHz 3.3VOUT, 600kHz FORCED CONTINUOUS MODE, SOURCING CURRENT<br>1.5VOUT, 400kHz 3.3VOUT, 600kHz 1.5VOUT, 400kHz 5.0VOUT, 750kHz FORCED CONTINUOUS MODE, SINKING CURRENT<br>1.8VOUT, 500kHz<br>1V Dual Phase Single Output  1.2V Dual Phase Single Output  1.5V Dual Phase Single Output<br>Load Transient Response  Load Transient Response  Load Transient Response<br>(Ceramic Output Capacitor Only) (Ceramic Output Capacitor Only) (Ceramic Output Capacitor Only)<br>VOUT (AC) VOUT (AC) VOUT (AC)<br>50mV/DIV 50mV/DIV 50mV/DIV<br>LOAD STEP LOAD STEP LOAD STEP<br>10A/DIV 10A/DIV 10A/DIV<br>100µs/DIV 4652 G04 100µs/DIV 4652 G05 100µs/DIV 4652 G06<br>12VIN, 1VOUT, 300kHz  12VIN, 1.2VOUT, 400kHz  12VIN, 1.5VOUT, 400kHz<br>25%, 12.5A LOAD STEP-UP AND  25%, 12.5A LOAD STEP-UP AND  25%, 12.5A LOAD STEP-UP AND<br>STEP-DOWN, 10A/μs SLEW RATE STEP-DOWN, 10A/μs SLEW RATE STEP-DOWN, 10A/μs SLEW RATE<br>COUT = 220μF ×8 CERAMIC CAP COUT = 220μF ×8 CERAMIC CAP COUT = 220μF ×8 CERAMIC CAP<br>RTH = 3.32k, CTH = 6800pF, CFF = 68pF RTH = 3.32k, CTH = 6800pF, CFF = 68pF RTH = 3.32k, CTH = 6800pF, CFF = 68pF<br>EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%)<br>**----- End of picture text -----**<br>


Rev. A 

6 

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LTM4652 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**TA = 25°C, unless otherwise noted.** 

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1.8V Dual Phase Single Output  2.5V Dual Phase Single Output  3.3V Dual Phase Single Output<br>Load Transient Response  Load Transient Response  Load Transient Response<br>(Ceramic Output Capacitor Only) (Ceramic Output Capacitor Only) (Ceramic Output Capacitor Only)<br>VOUT (AC) VOUT (AC) VOUT (AC)<br>50mV/DIV 50mV/DIV 50mV/DIV<br>LOAD STEP LOAD STEP LOAD STEP<br>10A/DIV 10A/DIV 10A/DIV<br>100µs/DIV 4652 G07 100µs/DIV 4652 G08 100µs/DIV 4652 G09<br>12VIN, 1.8VOUT, 500kHz  12VIN, 2.5VOUT, 500kHz  12VIN, 3.3VOUT, 600kHz<br>25%, 12.5A LOAD STEP-UP AND  25%, 12.5A LOAD STEP-UP AND  25%, 12.5A LOAD STEP-UP AND<br>STEP-DOWN, 10A/μs SLEW RATE So STEP-DOWN, 10A/μs SLEW RATE Ee STEP-DOWN, 10A/μs SLEW RATE<br>COUT = 220μF ×8 CERAMIC CAP COUT = 220μF ×8 CERAMIC CAP COUT = 220μF ×8 CERAMIC CAP<br>RTH = 3.32k, CTH = 6800pF, CFF = 68pF RTH = 3.32k, CTH = 6800pF, CFF = 68pF RTH = 3.32k, CTH = 6800pF, CFF = 68pF<br>**----- End of picture text -----**<br>


**1.2V Dual Phase Single Output Load Transient Response** 

**1.5V Dual Phase Single Output Load Transient Response** 

**1V Dual Phase Single Output 1.2V Dual Phase Single Output 1.5V Dual Phase Single Output Load Transient Response Load Transient Response Load Transient Response (Bulk Output Capacitor) (Bulk Output Capacitor) (Bulk Output Capacitor)** VOUT (AC) VOUT (AC) VOUT (AC) 50mV/DIV 50mV/DIV 50mV/DIV LOAD STEP LOAD STEP LOAD STEP 10A/DIV 10A/DIV 10A/DIV ~~ee~~ 100µs/DIV 4652 G10 100µs/DIV 4652 G11 100µs/DIV 4652 G12 12VIN, 1VOUT, 300kHz 12VIN, 1.2VOUT, 400kHz 12VIN, 1.5VOUT, 400kHz 25%, 12.5A LOAD STEP-UP AND 25%, 12.5A LOAD STEP-UP AND 25%, 12.5A LOAD STEP-UP AND STEP-DOWN, 10A/μs SLEW RATE STEP-DOWN, 10A/μs SLEW RATE STEP-DOWN, 10A/μs SLEW RATE COUT = 220μF ×4 CERAMIC CAP COUT = 220μF ×4 CERAMIC CAP COUT = 220μF ×4 CERAMIC CAP + 470μF ×2, 2.5V SPCAP + 470μF ×2, 2.5V SPCAP + 470μF ×2, 2.5V SPCAP CTHP = 10pF, RTH = 4.65k CTHP = 10pF, RTH = 4.65k CTHP = 10pF, RTH = 4.65k CTH = 4700pF, CFF = 10pF CTH = 4700pF, CFF = 10pF CTH = 4700pF, CFF = 10pF Rev. A 

7 

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## LTM4652 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

## **TA = 25°C, unless otherwise noted.** 

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1.8V Dual Phase Single Output  2.5V Dual Phase Single Output  3.3V Dual Phase Single Output<br>Load Transient Response  Load Transient Response  Load Transient Response<br>(Bulk Output Capacitor) (Bulk Output Capacitor) (Bulk Output Capacitor)<br>VOUT (AC) VOUT (AC) VOUT (AC)<br>50mV/DIV 50mV/DIV 50mV/DIV<br>LOAD STEP LOAD STEP LOAD STEP<br>10A/DIV 10A/DIV 10A/DIV<br>So<br>100µs/DIV 4652 G13 100µs/DIV 4652 G14 100µs/DIV 4652 G15<br>12VIN, 1.8VOUT, 500kHz  12VIN, 2.5VOUT, 500kHz  12VIN, 3.3VOUT, 600kHz<br>25%, 12.5A LOAD STEP-UP AND  25%, 12.5A LOAD STEP-UP AND  25%, 12.5A LOAD STEP-UP AND<br>STEP-DOWN, 10A/μs SLEW RATE STEP-DOWN, 10A/μs SLEW RATE STEP-DOWN, 10A/μs SLEW RATE ee<br>COUT = 220μF ×4 CERAMIC CAP COUT = 220μF ×4 CERAMIC CAP COUT = 220μF ×4 CERAMIC CAP<br>+ 470μF ×2, 2.5V SPCAP + 470μF ×2, 2.5V SPCAP + 470μF ×2, 6.3V POSCAP<br>CTHP = 10pF, RTH = 4.65k  CTHP = 10pF, RTH = 4.65k  CTHP = 10pF, RTH = 9.09k<br>CTH = 4700pF, CFF = 10pF CTH = 4700pF, CFF = 10pF CTH = 4700pF, CFF = NONE<br>5V Dual Phase Single Output<br>Load Transient Response  Single Phase Start-Up with<br>(Bulk Output Capacitor) No Load<br>SW<br>VOUT (AC) 10V/DIV<br>50mV/DIV<br>VOUT<br>0.5V/DIV<br>LOAD STEP INPUT<br>10A/DIV CURRENT<br>0.2A/DIV<br>=<br>100µs/DIV 4652 G16 20ms/DIV 4652 G17<br>12VIN, 5VOUT, 750kHz  12VIN, 1.2VOUT, 400kHz<br>25%, 12.5A LOAD STEP-UP/ STEP-DOWN,  COUT = 470μF ×2<br>10A/μs SLEW RATE, COUT = 220μF ×4 CERAMIC SPCAP + 100µF ×4 CERAMIC CAP<br>CAP + 470μF ×2, 6.3V POSCAP CSS = 0.1µF<br>CTHP = 10pF, RTH = 9.09k<br>CTH = 4700pF, CFF = NONE<br>Single Phase Start-Up with  Single Phase Short-Circuit  Single Phase Short-Circuit<br>25A Load Protection with No Load Protection with 25A Load<br>SW SW<br>10V/DIV 10V/DIV<br>SW<br>10V/DIV<br>VOUT VOUT<br>0.5V/DIV 0.5V/DIV<br>VOUT<br>0.5V/DIV<br>INPUT INPUT<br>INPUT CURRENT CURRENT<br>CURRENT 5A/DIV 2A/DIV<br>2A/DIV<br>Fa<br>20ms/DIV 4652 G18 100μs/DIV 4652 G19 100μs/DIV 4652 G20<br>12VIN, 1.2VOUT, 400kHz 12VIN, 1.2VOUT, 400kHz 12VIN, 1.2VOUT, 400kHz<br>COUT = 470μF ×2  COUT = 470μF ×2  COUT = 470μF ×2<br>SPCAP + 100µF ×4 CERAMIC CAP, CSS = 0.1µF SPCAP + 100µF ×4 CERAMIC CAP CS SPCAP + 100µF ×4 CERAMIC CAP ES<br>Rev. A<br>8 For more information www.analog.com<br>**----- End of picture text -----**<br>


8 

LTM4652 

## **PIN FUNCTIONS (Recommended to use test points to monitor signal pin connections.)** 

## **PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY.** 

**==> picture [34 x 31] intentionally omitted <==**

**VOUT1 (Pins A1–A5, B1–B5, C1–C4):** Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. Review Table 6. 

**GND (Pins A6–A7, B6–B7, D1–D4, D9–D12, E1–E4, E10– E12, F1–F3, F10–F12, G1, G3, G10, G12, H1–H4, H7, H9– H12, J1, J5, J8, J12, K1, K5–K8, K12, L1, L12, M1, M12):** Power Ground Pins for Both Input and Output Returns. 

**VOUT2 (Pins A8–A12, B8–B12, C9–C12):** Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. Review Table 6. 

**VOUTS1, VOUTS2 (Pins C5, C8):** This pin is connected to the top of the internal top feedback resistor for each output. The pin can be directly connected to its specific output, or connected to DIFFOUT when the remote sense amplifier is used. In paralleling modules, one of the VOUTS pins is connected to the DIFFOUT pin in remote sensing or - directly to VOUT with no remote sensing. It is very import ant to connect these pins to either the DIFFOUT or VOUT since this is the feedback path, and cannot be left open. See the Applications Information section. 

**fSET (Pin C6):** Frequency Set Pin. A 9.5µA current is sourced from this pin. A resistor from this pin to ground sets a voltage that in turn programs the operating frequency. Alternatively, this pin can be driven with a DC voltage that can set the operating frequency. See the Applications Information section. 

**SGND (Pins C7, D6, G6–G7, F6–F7):** Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the application. See layout guidelines in Figure 30. 

**VFB1, VFB2 (Pins D5, D7):** The Negative Input of the Error Amplifier for Each Channel. Internally, this pin is connected to VOUTS1 or VOUTS2 with a 60.4k precision resistor. Different output voltages can be programmed with an additional resistor between VFB and GND pins. In 

PolyPhase[®] operation, tying the VFB pins together allows for parallel operation. See the Applications Information section for details. Do not drive this pin. 

**TRACK1, TRACK2 (Pins E5, D8):** Output Voltage Tracking Pin and Soft-Start Inputs. Each channel has a 1.25µA pull-up current source. When one channel is configured to be the main of the two channels, then a capacitor from this pin to ground will set a soft-start ramp rate. The remaining channel can be set up as the subordinate, and have the main’s output applied through a voltage divider to the subordinate output’s TRACK pin. This voltage divider is equal to the subordinate output’s feedback divider for coincidental tracking. See the Applications Information section. 

**COMP1, COMP2 (Pins E6, E7):** Current control threshold and error amplifier compensation point for each channel. The current comparator threshold increases with this control voltage. COMP pin internal has 10pF filter cap to SGND. An external RC filter circuit is required for control loop compensation. See Applications Information section. Tie the COMP pins together for parallel operation. Do not drive this pin. 

**DIFFP (Pin E8):** Positive input of the remote sense amplifier. This pin is connected to the remote sense point of the output voltage. Diffamp can be used for ≤3.3V outputs. See the Applications Information section. 

**DIFFN (Pin E9):** Negative input of the remote sense amplifier. This pin is connected to the remote sense point of the output GND. Diffamp can be used for ≤3.3V outputs. See the Applications Information section. 

**MODE_PLLIN (Pin F4):** Forced Continuous Mode or PulseSkipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to SGND to force both channels into forced continuous mode of operation. Connect to INTVCC to enable pulse-skipping mode of operation. A clock on the pin will force both channels into continuous mode of operation and synchronized to the external clock applied to this pin. 

Note that this module is designed to conduct bidirectional output current. When pulse-skipping mode is selected, there is no way for the control loop to command 

Rev. A 

9 

For more information www.analog.com 

LTM4652 

## **PIN FUNCTIONS** 

## **(Recommended to use test points to monitor signal pin connections.)** 

instantaneous inductor current below 0A except by deliberately allowing the output voltage to rise high enough (~10% above nominal regulation) to induce an output overvoltage response. Transient and sustained operation in this manner is strongly not recommended. 

from VIN to VINOVP to set VIN(OVP), the VIN overvoltage inception threshold. VIN(OVP) is given by Equation 1. 

**==> picture [240 x 27] intentionally omitted <==**

See Figure 1 and the Applications Information section. 

Thus, in applications where transient and/or sustained negative (sinking) output current is expected, the LTM4652 must be operated in forced continuous mode. 

When VINOVP is detected (VVINOVP > 1.22V), all power MOSFETs in both channels are turned off and remain off until the module is restarted. The module can be restarted by either cycling the RUN pins below their RUN thresholds or cycling the TRACK pins to SGND. Leave VINOVP open circuit or connect to SGND when this feature is not used. 

**RUN1, RUN2 (Pins F5, F9):** Run Control Pin. A voltage above 1.22V will turn on each channel in the module. A voltage below 1.085V (135mV hysteresis, typ.) on the RUN pin will turn off the related channel. Each RUN pin has a 1µA pull-up current, once the RUN pin reaches 1.22V an additional 4.5µA pull-up current is added to this pin. 

**TEMP[–] (Pin H6):** Temperature Monitor, Negative Terminal. See TEMP[+] . 

**INTVCC (Pin H8):** Internal 5V Regulator Output. The control circuits and internal gate drivers are powered from this voltage. Decouple this pin to PGND with a 4.7µF low ESR tantalum or ceramic. INTVCC is activated when either RUN1 or RUN2 is activated. 

**DIFFOUT (Pin F8):** Internal Remote Sense Amplifier Output. Connect this pin to VOUTS1 or VOUTS2 depending on which output is using remote sense. In parallel operation connect one of the VOUTS pin to DIFFOUT for remote sensing. 

**TEMP[+] (Pin J6):** Temperature Monitor, Positive Terminal. An internal diode-configured PNP transistor connected between TEMP[+] and TEMP[–] pins. See the Applications Information section. 

**SW1, SW2 (Pins G2, G11):** Switching node of each channel that is used for testing purposes. Also an R-C snubber network can be applied to reduce or eliminate switch node ringing, or otherwise leave floating. See the Applications Information section. 

**EXTVCC (Pin J7):** External power input that is enabled through a switch to INTVCC whenever EXTVCC is greater than 4.7V. Do not exceed 6V on this input, and connect this pin to VIN when operating VIN on 5V. An efficiency increase will occur, corresponding to a power loss reduction of (VIN – INTVCC) multiplied by power MOSFET driver current. Typical current requirement is 30mA. VIN must be applied before EXTVCC, and EXTVCC must be removed before VIN. 

**PHASMD (Pin G4):** Connect this pin to SGND, INTVCC, or floating this pin to select the phase of CLKOUT to 60 degrees, 120 degrees, and 90 degrees respectively. 

**CLKOUT (Pin G5):** Clock output with phase control using the PHASMD pin to enable multiphase operation between devices. See the Applications Information section. 

**PGOOD1, PGOOD2 (Pins G9, G8):** Output Voltage Power Good Indicator. Open drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point. 

**VIN (Pins M2–M11, L2–L11, J2–J4, J9–J11, K2–K4, K9–K11):** Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between VIN pins and GND pins. 

**VINOVP (Pin H5):** VIN Overvoltage Protection (OVP) Comparator Input. Internally, this pin connects to SGND through a 60.4k resistor. If desired, apply resistor RVINOVP 

**Heat Sink (Top Exposed Metal):** The top exposed metal is electrically unconnected. 

Rev. A 

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LTM4652 

## **SIMPLIFIED BLOCK DIAGRAM** 

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PGOOD1<br>TRACK1 PGOOD1 VIN VIN<br>4.5V TO<br>SS CAP 18V<br>DIODE-CONNECTED PNP CIN1 CIN2<br>TEMP [+] TEMPERATURE SENSOR 1µF 22µF 22µF<br>25V 25V<br>TEMP [–]<br>GND<br>CLKOUT<br>MTOP1<br>SW1<br>RUN1<br>+<br>MODE_PLLIN 1.22 V – 0.22µH VOUT1 V1.5VOUT1<br>+ ±25A<br>PHASMD MBOT1 1µF COUT1<br>GND<br>COMP1<br>VOUTS1<br>RTH1<br>CTHP1 10pF<br>CTH1 60.4k<br>SGND VFB1<br>TRACK2 RFB1<br>POWER PGOOD2 40.2k<br>SS CAP CONTROL<br>INTVCC<br>VIN<br>4.7µF<br>VIN EXTVCC 1µF CIN3 CIN4<br>22µF 22µF<br>RVINOVP GND 25V 25V<br>VINOVP<br>+ MTOP2<br>60.4k 470pF 1.22V – SW2<br>RUN2 0.22µH VOUT2 VOUT2<br>+ 3.3V<br>+ ±25A<br>1.22V – MBOT2 1µF COUT2<br>COMP2 GND<br>VOUTS2<br>RTH2 CTHP2 fSET 10pF + – 60.4k VFB2<br>CTH2 INTERNAL RFB2<br>RFSET FILTER 13.3k<br>SGND<br>DIFFOUT 4652 BD<br>DIFFN<br>DIFFP<br>**----- End of picture text -----**<br>


**Figure 1. Simplified LTM4652 Block Diagram** 

## **DECOUPLING REQUIREMENTS TA = 25°C. Use Figure 1 configuration.** 

|**DECO**|**UPLING REQUIREMENTS**|**TA = 25°C. Use Figure 1 configuration.**|||
|---|---|---|---|---|
|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|CIN1,CIN2<br>CIN3, CIN4|External Input Capacitor Requirement<br>(VIN1= 4.5V to 18V, VOUT1= 1.2V)<br> (VIN2= 4.5V to 18V, VOUT2= 3.3V)|IOUT1= ±25A<br>IOUT2= ±25A|22<br>22<br>66<br>66|µF<br>µF|
|COUT1<br>COUT2|External Output Capacitor Requirement<br>(VIN1= 4.5V to 18V, VOUT1= 1.2V)<br> (VIN2= 4.5V to 18V, VOUT2= 3.3V)|IOUT1= ±25A<br>IOUT2= ±25A|300<br>300<br>600<br>600|µF<br>µF|



Rev. A 

11 

For more information www.analog.com 

LTM4652 

## **OPERATION** 

## **Power Module Description** 

The LTM4652 is a bidirectional dual-output standalone nonisolated switching mode DC/DC power supply with ±1.5% total DC output error over line, load and temperature variation. It can provide two ±25A outputs or single ±50A output with few external input and output capacitors and setup components. This module provides precisely regulated output voltages programmable via external resistors from 0.6VDC to 7.5VDC over 4.5V to 18V input voltages. The typical application schematic is shown in Figure 31. 

The LTM4652 has dual integrated constant-frequency current mode regulators and built-in power MOSFET devices with fast switching speed. The typical switching frequency is 300kHz* to 780kHz depending on different input and output conditions. For switching-noise sensitive applications, it can be externally synchronized from 300kHz[*] to 780kHz. A resistor can be used to program a free run frequency on the fSET pin. See the Applications Information section. 

With current mode control, multiple LTM4652s can be easily paralleled to provide up to ±300A current with excellent current sharing. Also, with current mode control, the LTM4652 module is able to achieve sufficient stability margins and a very fast ±3% output transient response with a minimum number of output capacitors, even with all ceramic output capacitors. This makes LTM4652 the best candidate when powering FPGAs, ASICs and processors in terms of DC accuracy, AC transient response, high output current and accuracy current sharing. See Applications Information section. 

Current mode control provides cycle-by-cycle fast current limit and foldback current limit in an overcurrent condition. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD outputs low if the output feedback voltage exits a ±10% window around the regulation point. As the output voltage exceeds 10% above regulation, the bottom MOSFET will turn on to clamp the output voltage. The top MOSFET will be turned off. This overvoltage protection is feedback voltage referred. 

If desired, latch-off input overvoltage protection can be implemented by connecting an appropriate resistor, 

> *Note that synchronization below 400kHz is not tested in ATE. 

RVINOVP, from VIN to VINOVP. When the VINOVP pin exceeds 1.22V, switching action ceases, i.e., both the top MOSFET and bottom MOSFET are latched off. The module can be restarted by cycling the RUN pins below their RUN thresholds, or by cycling the TRACK pins to SGND or by cycling VIN altogether. 

Pulling the RUN pins below 1.1V forces the regulators into a shutdown state, by turning off both MOSFETs. The TRACK pins are used for programming the output voltage ramp and voltage tracking during start-up or used for soft-starting the regulator. See the Applications Information section. 

The LTM4652 has a built-in 10pF high frequency filter cap from COMP to SGND for each channel. An external RC filtering circuit is required to achieve fast Type II control loop compensation. Table 6 provides a guide line for input, output capacitances and R-C values on COMP pin for several operating conditions. The Analog Devices µModule Power Design Tool (LTpowerCAD[®] ) provides for transient and stability analysis. The VFB pin is used to program the output voltage with a single external resistor to ground. A differential remote sense amplifier is available for sensing the output voltage accurately on one of the outputs at the load point, or in parallel operation sensing the output voltage at the load point. 

High efficiency at light loads can be accomplished with selectable pulse-skipping operation using the MODE_ PLLIN pin. This light load feature will accommodate battery operation. Efficiency graphs are provided for light load operation in the Typical Performance Characteristics section. See the Applications Information section for details. 

A general purpose diode-configured PNP temperature sensor is included inside the module to monitor the temperature of the module. See the Applications Information section for details. 

The switch pins, SW1 and SW2, are available for functional operation monitoring and a resistor-capacitor snubber circuit can be careful placed on the switch pin to ground to dampen any high frequency ringing on the transition edges. See the Applications Information section for details. 

Rev. A 

12 

For more information www.analog.com 

LTM4652 

## **APPLICATIONS INFORMATION** 

The typical LTM4652 application circuit is shown in Figure 31. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 6 for specific external capacitor requirements for a 25% or a 50% load step application. 

## **Output Total DC Accuracy and AC Transient Performance** 

In modern ASIC and FPGA power supply designs, a tight total voltage regulation window, ±3% for example, is required of the supply powering the core and periphery. To meet this requirement, the supply’s DC voltage variance plus any AC voltage variation which may occur during any load step transient must fall within this allowed window. The DC voltage variance is determined by the accuracies of the supply’s reference voltage, resistor divider, load regulation and line regulation over the operating temperature range. The AC voltage variance is determined by the supply’s output voltage overshoot and undershoots in response to a load transient condition for a given output capacitor network. 

Figure 2 shows a typical load step transient response waveform together with DC voltage accuracy variance. For a given allowable voltage regulation window, a tighter DC voltage accuracy allows more margin for the AC variation due to a load transient response. This increased margin for AC variation allows for a reduction in the total output capacitance required to meet the regulation window requirement. This allows for a reduced total solution cost and footprint area. 

**==> picture [253 x 104] intentionally omitted <==**

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LOAD STEP<br>AC OVERSHOOT<br>ALLOWABLE<br>REGULATION  DC ACCURACY<br>WINDOW<br>AC UNDERSHOOT<br>**----- End of picture text -----**<br>


**==> picture [16 x 4] intentionally omitted <==**

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4652 F02<br>**----- End of picture text -----**<br>


**Figure 2. Typical Load Step Transient Response with DC Voltage Accuracy Variance** 

For example, in an FPGA core voltage application, for a 12V input, 1.0V output at 100A design, a total overall ±3% total voltage regulation window is required in responding to a 25% load step transient. Figure 3 illustrates the benefit of overall output capacitor reduction versus improved total DC accuracy by using 100µF ceramic output capacitors. 

**==> picture [161 x 160] intentionally omitted <==**

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9000<br>8000<br>8000<br>7000<br>6000<br>5400<br>5000 4500<br>4000<br>4000 3700<br>3000<br>2000<br>1000<br>0<br>0.8 1.0 1.2 1.5 2.0<br>TOTAL DC ACCURACY (%)<br>4652 F03<br>REQUIRED OUTPUT CAPACITANCE (µF)<br>**----- End of picture text -----**<br>


**Figure 3. Overall Output Capacitor vs Total DC Accuracy** 

## **VIN to VOUT Step-Down Ratios** 

There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage. Each output of the LTM4652 is capable of 98% duty cycle, but the VIN to VOUT minimum dropout is still shown as a function of its load current and will limit output current capability related to high duty cycle on the top side switch. Minimum on-time t is another consideration in ON(MIN) operating at a specified duty cycle while operating at a certain frequency due to the fact that tON(MIN) < D/fSW, where D is duty cycle and fSW is the switching frequency. tON(MIN) is specified in the electrical parameters as 90ns. 

## **Output Voltage Programming** 

The PWM controller has an internal 0.6V reference voltage. As shown in the Figure 1 (Simplified Block Diagram), a 60.4k internal feedback resistor connects between the VOUTS1 to VFB1 and VOUTS2 to VFB2. It is very important that these pins be connected to their respective outputs for proper feedback regulation. Overvoltage can occur if these VOUTS1 and VOUTS2 pins are left floating when used as individual regulators, or at least one of them is used 

Rev. A 

13 

For more information www.analog.com 

LTM4652 

## **APPLICATIONS INFORMATION** 

in paralleled regulators. The output voltage will default to 0.6V with no feedback resistor on either VFB1 or VFB2. Adding a resistor RFB from VFB pin to GND programs the output voltage given by Equation 2. (See Table 1.) 

**==> picture [239 x 29] intentionally omitted <==**

**Table 1. VFB Resistor Table vs Various Output Voltages** 

|**VOUT**|0.6V|1.0V|1.2V|1.5V|1.8V|2.5V|3.3V|5V|
|---|---|---|---|---|---|---|---|---|
|**RFB**|Open|90.9k|60.4k|40.2k|30.2k|19.1k|13.3k|8.25k|



For parallel operation of multiple channels the same feedback setting resistor can be used for the parallel design. This is done by connecting the VOUTS1 to the output as shown in Figure 4, thus tying one of the internal 60.4k resistors to the output. All of the VFB pins tie together with one programming resistor as shown in Figure 4. 

In parallel operation, the VFB pins have an IFB current of 30nA per channel, maximum. To reduce output voltage error due to this current, an additional VOUTS pin can be tied to VOUT, and an additional RFB resistor can be used to lower the total Thevenin equivalent resistance seen by this current. For example in Figure 4, the total Thevenin equivalent resistance of the VFB pin is (60.4k//RFB), which is 30.2k where RFB is equal to 60.4k for a 1.2V output. Four phases connected in parallel equates to a worse case feedback current of 4 • IFB = 120nA maximum. The voltage error is 120nA • 30.2k = 3.6mV. If VOUTS2 is connected, as shown in Figure 4, to VOUT, and another 60.4k resistor is connected from VFB2 to ground, then the voltage error is reduced to 1.8mV. If the voltage error is acceptable then no additional connections are necessary. The onboard 60.4k resistor is 0.5% accurate and the VFB resistor can be chosen by the user to be as accurate as needed. All COMP pins are tied together for current sharing between the phases. The TRACK pins can be tied together and a single soft-start capacitor can be used to soft-start the regulator. Equation 6 in the Soft-Start And Output Voltage Tracking section will need to have the soft-start current parameter increased by the number of paralleled channels. 

**==> picture [251 x 245] intentionally omitted <==**

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COMP1 LTM4652 VOUT1 4 PARALLELED OUTPUTS FOR 1.2V AT 100A<br>2.5k COMP2 VOUT2<br>6800pF 60.4k VOUTS1<br>VOUTS2<br>OPTIONAL CONNECTION<br>VFB1<br>60.4k<br>TRACK1<br>VFB2<br>T RACK2<br>OPTIONAL<br>RFB<br>COMP1 LTM4652 VOUT1 60.4k<br>COMP2 VOUT2<br>60.4k VOUTS1 USE TO LOWERTOTAL EQUIVALENT<br>VOUTS2 RESISTANCE TO LOWER<br>IFB VOLTAGE ERROR<br>VFB1<br>60.4k<br>TRACK1<br>VFB2<br>0.1µF TRACK2<br>RFB<br>4652 F04 60.4k<br>**----- End of picture text -----**<br>


**Figure 4. 4-Phase Parallel Configurations** 

## **Input Capacitors** 

The LTM4652 module should be connected to a low AC-impedance DC source. For each channel input, two 22µF input ceramic capacitors are used for RMS ripple current. A 47µF to 100µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this bulk capacitor is not needed. 

For a buck converter, the switching duty-cycle can be estimated using Equation 3. 

**==> picture [240 x 30] intentionally omitted <==**

Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated using Equation 4. 

**==> picture [241 x 30] intentionally omitted <==**

Rev. A 

14 

For more information www.analog.com 

LTM4652 

## **APPLICATIONS INFORMATION** 

In Equation 4, η % is the estimated efficiency of the power module. The bulk capacitor can be a switcher-rated electrolytic aluminum capacitor, Polymer capacitor. 

## **Output Capacitors** 

The LTM4652 is designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, the low ESR polymer capacitor or ceramic capacitor. The typical output capacitance range for each output is from 300µF to 800µF per output channel. Additional output filtering may be required by the system designer, if further reduction of output ripples or dynamic transient spikes is required. Table 6 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 25% load step. In multi LTM4652 paralleling applications, Table 6 RC compensation value is still valid in terms of having one set of RC filters on each of the paralleling modules while connecting all the COMP, FB and VOUT pins together. See Figure 34 and Multiphase Operation section. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 6 matrix, and the Analog Devices LTpowerCAD Design Tool provides for stability analysis. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The Analog Devices µModule Power Design Tool can calculate the output ripple reduction as the number of implemented phases increases by N times. A small value 10Ω to 50Ω resistor can be placed in series from VOUT to the VOUTS pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. The same resistor could be placed in series from VOUT to DIFFP and a bode plot analyzer could inject a signal into the control loop and validate the regulator stability. 

## **Pulse-Skipping Mode Operation** 

In applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the LTM4652 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE_PLLIN pin to INTVCC enables pulse-skipping operation. At light loads the internal current comparator may remain tripped for several cycles and force the top MOSFET to stay off for several cycles, thus skipping cycles. The inductor current does not reverse in this mode. 

Applications with transient and/or sustained negative (sinking) output current should operate the LTM4652 in forced continuous mode, since there is no way for the control loop to command reverse (negative) inductor current in pulse-skipping operation except by deliberately allowing the output voltage to rise high enough (~10% above nominal regulation) to activate an output overvoltage response. 

## **Forced Continuous Operation** 

In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE_PLLIN pin to SGND. In this mode, inductor current is allowed to reverse during low output loads, the COMP voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4652’s output voltage is in regulation. Either regulator can be configured for forced continuous mode. 

## **Multiphase Operation** 

For output loads that demand more than ±25A of current, two outputs in LTM4652 or even multiple LTM4652s can be paralleled to run out of phase to provide more output current without increasing input and output voltage ripples. The MODE_PLLIN pin allows the LTM4652 to synchronize to an external clock (between 300kHz* and 780kHz) and the internal phase-locked-loop allows the LTM4652 to lock 

*Note that synchronization below 400kHz is not tested in ATE. 

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LTM4652 

## **APPLICATIONS INFORMATION** 

onto incoming clock phase as well. The CLKOUT signal can be connected to the MODE_PLLIN pin of the following stage to line up both the frequency and the phase of the entire system. Tying the PHASMD pin to INTVCC, SGND, or (floating) generates a phase difference (between MODE_PLLIN and CLKOUT) of 120 degrees, 60 degrees, or 90 degrees respectively. A total of 12 phases can be cascaded to run simultaneously with respect to each other by programming the PHASMD pin of each LTM4652 channel to different levels. Figure 5 shows a 2-phase design, 4-phase design and a 6-phase design example for clock phasing with the PHASMD table. 

A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design. 

In multi LTM4652s parallel applications, CTH and RTH values in Table 6 are still valid to achieve transient response in a 25% load step. Connect one set of RC (RTH and CTH) network to the COMP pin of each paralleling module like a dual phase single output setup. Then connect the COMP pins, FB pins, TRACK pins and VOUT pins from different modules together. See Figure 32, Figure 34 and Figure 35 for examples of parallel operation. LTpowerCAD Power Design Tool can also be used to optimize loop compensation and transient performance if only one set of RC (RTH and CTH) network is to be added to the common COMP pins. 

The LTM4652 device is an inherently current mode controlled device, so parallel modules will have very good current sharing. This will balance the thermals on the design. 

## **Input RMS Ripple Current Cancellation** 

Application Note 77 provides a detailed explanation of multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved phases. Figure 6 shows this graph. 

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**----- Start of picture text -----**<br>
2-PHASE DESIGN<br>PHASMD SGND FLOAT INTVCC<br>FLOAT<br>CONTROLLER1 0 0 0<br>CLKOUT<br>CONTROLLER2 180 180 240<br>MODE_PLLIN<br>0-PHASE 180-PHASE CLKOUT 60 90 120<br>VOUT1 VO UT2<br>PHA SMD<br>4-PHASE DESIGN<br>90-DEGREE<br>CLKOUT CLKOUT<br>MODE_PLLIN MODE_PLLIN<br>0-PHASE 180-PHASE 90-PHASE 270-PHASE<br>VOUT1 VO UT2 VOUT1 VO UT2<br>FLOAT FLOAT<br>PHA SMD PHA SMD<br>6-PHASE DESIGN<br>60-DEGREE 60-DEGREE<br>CLKOUT CLKOUT CLKOUT<br>MODE_PLLIN MODE_PLLIN MODE_PLLIN<br>0-PHASE 180-PHASE 60-PHASE 240-PHASE 120-PHASE 300-PHASE<br>VOUT1 VO UT2 VOUT1 VO UT2 VOUT1 VO UT2<br>SGND SGND FLOAT<br>PHA SMD PHA SMD PHA SMD<br>4652 F05<br>**----- End of picture text -----**<br>


**Figure 5. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table** 

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LTM4652 

## **APPLICATIONS INFORMATION** 

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**----- Start of picture text -----**<br>
0.60<br>1-PHASE<br>2-PHASE<br>0.55 3-PHASE<br>4-PHASE<br>6-PHASE<br>0.50<br>0.45<br>0.40<br>0.35<br>0.30<br>0.25<br>0.20<br>0.15<br>0.10<br>0.05<br>0<br>0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9<br>DUTY FACTOR (VOUT/VIN) 4652 F06<br>DC LOAD CURRENT<br>RMS INPUT RIPPLE CURRENT<br>**----- End of picture text -----**<br>


**Figure 6. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle** 

## **Frequency Selection and Phase-Lock Loop (MODE_PLLIN and fSET Pins)** 

The LTM4652 device is operated over a range of frequencies to improve power conversion efficiency. It is recommended to operate the module at 300kHz* to 780kHz over different input and output range for the best efficiency and inductor current ripple. 

The LTM4652 switching frequency can be set with an external resistor from the fSET pin to SGND. An accurate 9.5µA current source into the resistor will set a voltage that programs the frequency or a DC voltage can be applied. Figure 7 shows a graph of frequency setting verses programming voltage. An external clock can be applied to the MODE_PLLIN pin from 0V to INTVCC over a frequency range of 300kHz* to 780kHz. The clock input 

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900<br>800<br>700<br>600<br>500<br>400<br>300<br>200<br>100<br>0<br>0 0.5 1 1.5 2 2.5<br>fSET PIN VOLTAGE (V)<br>4652 F07<br>FREQUENCY (kHz)<br>**----- End of picture text -----**<br>


**Figure 7. Operating Frequency vs fSET Pin Voltage** 

> *Note that synchronization below 400kHz is not tested in ATE. 

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LTM4652 

## **APPLICATIONS INFORMATION** 

high threshold is 1.6V and the clock input low threshold is 1V. The LTM4652 has the PLL loop filter components on board. The frequency setting resistor should always be present to set the initial switching frequency before locking to an external clock. Both regulators will operate in forced continuous mode while being externally clocked. 

The output of the PLL phase detector has a pair of complementary current sources that charge and discharge the internal filter network. When the external clock is applied then the fSET frequency resistor is disconnected with an internal switch, and the current sources control the frequency adjustment to lock to the incoming external clock. When no external clock is applied, then the internal switch is on, thus connecting the external fSET frequency set resistor for free run operation. 

take over the internal 0.6V reference voltage to control the output voltage. The total soft-start time can be calculated using Equation 6. 

**==> picture [241 x 29] intentionally omitted <==**

where CSS is the capacitance on the TRACK pin. Current foldback and forced continuous mode are disabled during the soft-start process. 

Output voltage tracking can also be programmed externally using the TRACK pin. The output can be tracked up and down with another regulator. Figure 8 shows an example waveform where the subordinate regulator’s output slew rate is proportional to the main’s. 

## **Minimum On-Time** 

Minimum on-time tON is the smallest time duration that the LTM4652 is capable of turning on the top MOSFET on either channel. It is determined by internal timing delays, and the gate charge required turning on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure Equation 5. 

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**----- Start of picture text -----**<br>
MAIN OUTPUT<br>SUBORDINATE OUTPUT<br>TIME<br>4652 F08<br>OUTPUT VOLTAGE<br>**----- End of picture text -----**<br>


**Figure 8. Output Ratiometric Tracking Waveform** 

If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the output ripple and current will increase. The on-time can be increased by lowering the switching frequency. A good rule of thumb is to keep on-time longer than 110ns. 

## **Soft-Start And Output Voltage Tracking** 

The TRACK pin provides a means to either soft-start the regulator or track it to a different power supply. A capacitor on the TRACK pin will program the ramp rate of the output voltage. An internal 1.25µA current source will charge up the external soft-start capacitor towards INTVCC voltage. When the TRACK voltage is below 0.6V, it will 

Since the subordinate regulator’s TRACK is connected to the main’s output through a RTR(TOP)/RTR(BOT) resistor divider and its voltage used to regulate the subordinate output voltage when TRACK voltage is below 0.6V, the subordinate output voltage and the main output voltage should satisfy Equation 7 during start-up: 

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LTM4652 

## **APPLICATIONS INFORMATION** 

The R is the feedback resistor and the R / FB(SL) TR(TOP) RTR(BOT) is the resistor divider on the TRACK pin of the subordinate regulator, as shown in Figure 9. 

Following Equation 7, the ratio of the main’s output slew rate (MR) to the subordinate’s output slew rate (SR) is determined by Equation 8. 

**==> picture [239 x 69] intentionally omitted <==**

For example, VOUT(MA)=1.5V, MR = 1.5V/1ms and VOUT(SL) = 3.3V, SR = 3.3V/1ms. From Equation 8, we could solve that RTR(TOP) = 60.4k and RTR(BOT) = 40.2k are a good combination for the ratiometric tracking. 

The TRACK pin will have the 1.25µA current source on when a resistive divider is used to implement tracking 

on the subordinate regulator. This will impose an offset on the TRACK pin input. Smaller value resistors with the same ratios as the resistor values calculated from the Equation 8 can be used. For example, where the 60.4k is used then a 6.04k can be used to reduce the TRACK pin offset to a negligible value. 

Coincident output tracking can be recognized as a special ratiometric output tracking in which the main’s output slew rate (MR) is the same as the subordinate’s output slew rate (SR), waveform as shown in Figure 10. 

From Equation 8, we could easily find that, in coincident tracking, the subordinate regulator’s TRACK pin resistor divider is always the same as its feedback divider given by Equation 9. 

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**----- Start of picture text -----**<br>
INTVCC<br>C10 R2<br>4.7µF 10k<br>PGOOD1<br>4.5V TO 18V INTERMEDIATE BUS MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1 VOUT1<br>C4 C3 C2 C1 VIN VOUT1 C6 C8 (MAIN) 1.5V<br>22µF 22µF 22µF 22µF R6845k VINOVP VOUTS1 100µF6.3V 470µF ±25A<br>25V 25V 25V 25V SW1 ×3 6.3V<br>RUN1<br>RUN2 VFB1<br>TRACK1 VFB2<br>TRACK2 LTM4652 COMP1 RFB(SL) 40.2k<br>13.3k<br>CSS RTR(TOP) RTR(BOT) fSET COMP2<br>60.4k 40.2k<br>10k 10k<br>TEMP [+]<br>VOUT1 TEMP [–] 4.7nF 3.3nF<br>(MAIN)<br>1.5V PHASMD VOUTS2 VOUT2<br>R4 VOUT2SW2 SUBORDINATEPGOOD2 C5100µF C7 (SUB) 3.3V±25A<br>140k 6.3V 470µF<br>PGOO D2 ×3 6.3V<br>SGND GND DIFFP DIFFN DIFFOUT INTVCC<br>4652 F09 R9<br>10k<br>RAMP TIME<br>tSOFTSTART = (CSS/1.25µA) • 0.6V<br>**----- End of picture text -----**<br>


**Figure 9. Example of Output Tracking Application Circuit** 

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## LTM4652 

## **APPLICATIONS INFORMATION** 

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**----- Start of picture text -----**<br>
MAIN OUTPUT<br>SUBORDINATE OUTPUT<br>TIME<br>4652 F10<br>OUTPUT VOLTAGE<br>**----- End of picture text -----**<br>


**Figure 10. Output Coincident Tracking Waveform** 

For example, RTR(TOP) = 60.4k and RTR(BOT) = 13.3k is a good combination for coincident tracking for a VOUT(MA) = 1.5V and VOUT(SL) = 3.3V application. 

## **Power Good** 

The PGOOD pins are open drain pins that can be used to monitor valid output voltage regulation. This pin monitors a 10% window around the regulation point. A resistor can be pulled up to a particular supply voltage no greater than 6V maximum for monitoring. 

## **Stability Compensation** 

The LTM4652 has a built-in 10pF high frequency filter capacitor from COMP to SGND on each output channel. An external R-C filtering circuit is required to add from COMP to SGND to achieve fast Type II control loop compensation. Table 6 is provided for most application requirements. The Analog Devices µModule Power Design Tool (LTpowerCAD) provides for other control loop optimization. 

## **Run Enable** 

The RUN pins have an enable threshold of 1.4V maximum, typically 1.22V with 135mV of hysteresis. They control the turn on of each of the channels and INTVCC. These pins can be pulled up to VIN for 5V operation, or a 5V Zener diode can be placed on the pins and a 10k to 100k resistor 

can be placed up to higher than 5V input for enabling the channels. There is 1µA pull-up current for each RUN pin. The LTM4652 will turn on with RUN floating. Please note RUN has a 6V Abs Max voltage rating. The RUN pins can also be used for output voltage sequencing. In parallel operation the RUN pins can be tied together and controlled from a single control. See the Typical Application circuits in Figure 31. 

## **INTVCC and EXTVCC** 

The LTM4652 module has an internal 5V low dropout regulator that is derived from the input voltage. This regulator is used to power the control circuitry and the power MOSFET drivers. This regulator can source up to 50mA, and typically uses ~30mA for powering the device at the maximum frequency. This internal 5V supply is enabled by either RUN1 or RUN2. 

EXTVCC allows an external 5V supply to power the LTM4652 and reduce power dissipation from the internal low dropout 5V regulator. The power loss savings can be calculated using Equation 10. 

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EXTVCC has a threshold of 4.7V for activation, and a maximum rating of 6V. When using a 5V input, connect this 5V input to EXTVCC also to maintain a 5V gate drive level. EXTVCC must sequence on after VIN, and EXTVCC must sequence off before VIN. 

## **Differential Remote Sense Amplifier** 

An accurate differential remote sense amplifier is provided to sense low output voltages accurately at the remote load points. This is especially true for high current loads. The amplifier can be used on one of the two channels, or on a single parallel output. It is very important that the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to either VOUTS1 or VOUTS2. In parallel operation, the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to one of the VOUTS pins. Review the parallel schematics in Figure 32 and Figure 34 and review Figure 4. Please note the differential amplifier can be used for ≤3.3V outputs. 

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LTM4652 

## **APPLICATIONS INFORMATION** 

## **SW Pins** 

The SW pins are generally for testing purposes by monitoring these pins. These pins can also be used to dampen out switch node ringing caused by LC parasitic in the switched current paths. Usually a series R-C combination is used called a snubber circuit. The resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor. If the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond wire inductance. 

First the SW pin can be monitored with a wide bandwidth scope with a high frequency scope probe. The ring frequency can be measured for its value. The impedance Z can be calculated using Equation 11. 

**==> picture [253 x 15] intentionally omitted <==**

where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to Z, then the ringing should be dampened. The snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. Calculated by: Z(C) = 1/(2πfC). These values are a good place to start with. Modification to these components should be made to attenuate the ringing with the least amount of power loss. 

## **Temperature Monitoring** 

A diode connected PNP transistor is used for the TEMP[+] / TEMP[–] monitor function by monitoring its voltage over temperature. The temperature dependence of this diode voltage can be understood in Equation 12. 

**==> picture [239 x 35] intentionally omitted <==**

where VT is the thermal voltage (kT/q), and n, the ideality factor, is 1 for the diode connected PNP transistor being 

used in the LTM4652. IS is expressed by the typical empirical Equation 13. 

**==> picture [240 x 33] intentionally omitted <==**

where I0 is a process and geometry dependent current, (I0 is typically around 20k orders of magnitude larger than IS at room temperature) and VG0 is the band gap voltage of 1.2V extrapolated to absolute zero or –273°C. 

If we take the IS Equation 13 and substitute into the Equation 14, then we get: 

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**----- Start of picture text -----**<br>
⎛ ⎞ ⎛ ⎞<br>VD = VG0 – [kT] [I][0] [V][T][ =] [kT] (14)<br>⎝ [⎜] q ⎠ [⎟] [ln] ⎝ [⎜] ID ⎠ [⎟] [,] q<br>0.8<br>ID = 100µA<br>0.7<br>0.6<br>0.5<br>0.4<br>0.3<br>–50 –25 0 25 50 75 100 125<br>TEMPERATURE (°C) 4652 F11<br>DIODE VOLTAGE (V)<br>**----- End of picture text -----**<br>


**Figure 11. Diode Voltage VD vs Temperature T(K) for Different Bias Currents** 

The expression shows that the diode voltage decreases (linearly if I0 were constant) with increasing temperature and constant diode current. Figure 11 shows a plot of VD vs Temperature over the operating temperature range of the LTM4652. 

If we take Equation 14 and differentiate it with respect to temperature T, then Equation 15 gives: 

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This dVD/dT term is the temperature coefficient equal to about –2mV/K or –2mV/°C. Equation 15 is simplified for the first order derivation. 

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LTM4652 

## **APPLICATIONS INFORMATION** 

Solving for T, T = –(VG0 – VD)/(dVD/dT) provides the temperature. 

1st Example: Figure 11 for 27°C, or 300K the diode voltage is 0.598V, thus, 300K = –(1200mV – 598mV)/ –2.0mV/K). 

2nd Example: Figure 11 for 75°C, or 350K the diode voltage is 0.50V, thus, 350K = –(1200mV – 500mV)/ –2.0mV/K). 

Converting the Kelvin scale to Celsius is simply taking the Kelvin temp and subtracting 273 from it. 

A typical forward voltage is given in the electrical characteristics section of the data sheet, and Figure 11 is the plot of this forward voltage. Measure this forward voltage at 27°C to establish a reference point. Then using the above expression while measuring the forward voltage over temperature will provide a general temperature monitor. A bias current on the order of 100µA is appropriate for generating a typical forward voltage. If preferred, LTC2997 and similar temperature-monitoring ICs can be used, instead (see Figure 33). 

## **Thermal Considerations and Output Current Derating** 

The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those parameters defined by JESD51-9 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board— also defined by JESD51-9 (Test Boards for Area Array Surface Mount Package Thermal Measurements). The motivation for providing these thermal coefficients is found in JESD51-12 (Guidelines for Reporting and Using Electronic Package Thermal Information). 

Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the µModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the 

Pin Configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. 

The Pin Configuration section typically gives three thermal coefficients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below: 

1. θ JA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a Demo Board. 

2. θ JCbot, the thermal resistance from junction to the bottom of the product case, is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. In the typical µModule, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 

3. θ JCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbot, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 

A graphical representation of the aforementioned thermal resistances is given in Figure 12; blue resistances are contained within the µModule regulator, whereas green resistances are external to the µModule. 

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## **APPLICATIONS INFORMATION** 

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**----- Start of picture text -----**<br>
CASE (TOP)-TO-AMBIENT<br>RESISTANCE<br>JUNCTION-TO-CASE (TOP)<br>RESISTANCE<br>JUNCTION AMBIENT<br>JUNCTION-TO-CASE<br>(BOTTOM) RESISTANCE<br>BOARD-TO-AMBIENT<br>µModule DEVICE RESISTANCE<br>4652 F12<br>**----- End of picture text -----**<br>


**Figure 12. Graphical Representation of JESD51-12 Thermal Coefficients** 

As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a µModule. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the µModule—as the standard defines for θ JCtop and θ JCbot, respectively. In practice, power loss is thermally dissipated in both directions away from the package— granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. 

Within a SIP (system-in-package) module, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also, not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the µModule and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JESD51-9 to predict power loss heat flow and temperature 

readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the µModule with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields the set of derating curves provided in later sections of this data sheet, along with well-correlated JESD51-12-defined θ values provided in the Pin Configuration section of this data sheet. Each system has its own thermal characteristics, therefore thermal analysis must be performed by the user in a particular system. 

The LTM4652 module has been designed to effectively remove heat from both the top and bottom of the package. The bottom substrate material has very low thermal resistance to the printed circuit board. An external heat sink can be applied to the top of the device for excellent heat sinking with airflow. 

Figure 13 shows the thermal image of the LTM4652, without airflow, without heat sink, running paralleled from 12V to 1V at 50A with around 85.3% efficiency and 8.6W power loss. Figure 14 shows the thermal image of the LTM4652, with 200LFM airflow, without heat sink, running paralleled from 12V to 3.3V at 50A with around 92.2% efficiency and 14W power loss. 

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## LTM4652 

## **APPLICATIONS INFORMATION** 

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**----- Start of picture text -----**<br>
4652 F13<br>**----- End of picture text -----**<br>


**Figure 13. Thermal Image 12V to 1.0V, 50A with No Airflow without Heat Sink** 

## **Safety Considerations** 

The LTM4652 modules do not provide isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. The device does support over current protection. A temperature diode is provided for monitoring internal temperature, and can be used to detect the need for thermal shutdown that can be done by controlling the RUN pin. 

## **Power Derating** 

The 1.0V, 1.8V, 3.3V and 5V power loss curves in Figure 15 to Figure 17 can be used in coordination with the load current derating curves in Figure 18 to Figure 29 for calculating an approximate θ JA thermal resistance for the LTM4652 with various heat sinking and airflow conditions. The power loss curves are taken at room temperature, and are increased with a 1.2 multiplicative factor at 125°C. 

The derating curves are plotted with CH1 and CH2 in parallel single output operation starting at ±50A of load with low ambient temperature. The output voltages are 1V to 3.3V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. 

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4652 F14<br>**----- End of picture text -----**<br>


**Figure 14. Thermal Image 12V to 3.3V, 50A with 200LFM Airflow without Heat Sink** 

The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at ~120°C maximum while lowering output current or power while increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased. 

The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example in Figure 26, the load current is derated to ~36A at ~50°C with no air or heat sink and the power loss for the 12V to 3.3V at 36A output is a ~8.8W loss. The 8.8W loss is calculated with the ~8.4W room temperature loss from the 12V to 3.3V power loss curve at 36A, and applying a 1.05 multiplying factor at 50°C ambient (see Figure 17). If the 50°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 70°C divided by 8.8W yields a 7.95°C/W θ JA thermal resistance. Table 2 specifies a 7.9°C/W value which is pretty close. The airflow graphs are more accurate due to the fact that the ambient temperature environment is controlled better with airflow. Table 2 to Table 4 provide equivalent thermal resistances for 1.0V to 3.3V outputs with and without airflow and heat sinking. 

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LTM4652 

## **APPLICATIONS INFORMATION** 

## **Switching frequency set per Table 6.** 

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10 12 16<br>9 V V ININ = 12V = 5V 11 VVININ = 12V = 5V 14 V V IN IN  = 12V, V  = 12V, V OUT OUT  = 5V  = 3.3V<br>8 10 VIN = 5V, VOUT = 3.3V<br>9 12<br>7<br>8<br>10<br>6 7<br>5 6 8<br>4 5<br>6<br>4<br>3<br>3 4<br>2<br>2<br>2<br>1 1<br>0 0 0<br>–50 –40 –30 –20 –10 0 10 20 30 40 50 –50 –40 –30 –20 –10 0 10 20 30 40 50 –50 –40 –30 –20 –10 0 10 20 30 40 50<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>4652 F15 4652 F16 4652 F17<br>Figure 15. 1.0VOUT Power Loss Curve Figure 16. 1.8VOUT Power Loss Curve Figure 17. 3.3VOUT and 5VOUT<br>Power Loss Curves<br>50 50 50<br>40 40 40<br>30 30 30<br>20 20 20<br>10 10 10<br>0LFM 0LFM<br>0 200LFM 0 200LFM 0<br>400LFM 400LFM 0LFM<br>–10 –10 –10 200LFM<br>400LFM<br>–20 –20 –20<br>–30 –30 –30<br>–40 –40 –40<br>–50 –50 –50<br>40 50 60 70 80 90 100 110 120 40 50 60 70 80 90 100 110 120 40 50 60 70 80 90 100 110 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4652 F18 4652 F19 4652 F20<br>Figure 18. 12V to 1V Derating  Figure 19. 5V to 1V Derating  Figure 20. 12V to 1V Derating<br>Curve, No Heat Sink Curve, No Heat Sink Curve, BGA Heat Sink<br>50 50 50<br>40 40 40<br>30 30 30<br>20 20 20<br>10 10 10<br>0LFM 0LFM 0LFM<br>0 200LFM 0 200LFM 0 200LFM<br>400LFM 400LFM 400LFM<br>–10 –10 –10<br>–20 –20 –20<br>–30 –30 –30<br>–40 –40 –40<br>–50 –50 –50<br>40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120 40 50 60 70 80 90 100 110 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4652 F21 4652 F22 4652 F23<br>Figure 21. 5V to 1V Derating  Figure 22. 12V to 1.8V Derating  Figure 23. 5V to 1.8V Derating<br>Curve, BGA Heat Sink Curve, No Heat Sink Curve, No Heat Sink<br>Rev. A<br>POWER LOSS (W) POWER LOSS (W) POWER LOSS (W)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


25 

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LTM4652 

## **APPLICATIONS INFORMATION** 

## **Switching frequency set per Table 6.** 

**==> picture [523 x 635] intentionally omitted <==**

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50 50 50<br>40 40 40<br>30 30 30<br>20 20 20<br>10 10 10<br>0LFM 0LFM 0LFM<br>0 200LFM 0 200LFM 0 200LFM<br>400LFM 400LFM 400LFM<br>–10 –10 –10<br>–20 –20 –20<br>–30 –30 –30<br>–40 –40 –40<br>–50 –50 –50<br>30 40 50 60 70 80 90 100 110 120 40 50 60 70 80 90 100 110 120 20 30 40 50 60 70 80 90 100 110<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4652 F24 4652 F25 4652 F26<br>Figure 24. 12V to 1.8V Derating  Figure 25. 5V to 1.8V Derating  Figure 26. 12V to 3.3V Derating<br>Curve, BGA Heat Sink Curve, BGA Heat Sink Curve, No Heat Sink<br>50 50 50<br>40 40 40<br>30 30 30<br>20 20 20<br>10 10 10<br>0LFM 0LFM 0LFM<br>0 200LFM 0 200LFM 0 200LFM<br>400LFM 400LFM 400LFM<br>–10 –10 –10<br>–20 –20 –20<br>–30 –30 –30<br>–40 –40 –40<br>–50 –50 –50<br>30 40 50 60 70 80 90 100 110 120 20 30 40 50 60 70 80 90 100 110 30 40 50 60 70 80 90 100 110 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4652 F27 4652 F28 4652 F29<br>Figure 27. 5V to 3.3V Derating  Figure 28. 12V to 3.3V Derating  Figure 29. 5V to 3.3V Derating<br>Curve, No Heat Sink Curve, BGA Heat Sink Curve, BGA Heat Sink<br>Rev. A<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


26 

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LTM4652 

## **APPLICATIONS INFORMATION** 

The derived thermal resistances in Table 2 to Table 4 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves and adjusted with the above ambient temperature multiplicative factors. The printed circuit board is a 1.6mm thick four layer board - with two ounce copper for all four layers. The PCB dimen sions are 101mm × 114mm. The BGA heat sinks are listed in Table 5. 

## **Layout Checklist/Example** 

The high integration of LTM4652 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. 

- Use large PCB copper areas for high current paths, including VIN, GND, VOUT1 and VOUT2. It helps to minimize the PCB conduction loss and thermal stress. 

- Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize high frequency noise. 

- Place a dedicated power ground layer underneath the unit. 

- To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. 

- Do not put via directly on the pad, unless they are capped or plated over. 

- Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to GND underneath the unit. 

- For parallel modules, tie the VOUT, VFB, and COMP pins together. Use an internal layer to closely connect these pins together. The TRACK pin can be tied a common capacitor for regulator soft-start. 

- Bring out test points on the signal pins for monitoring. 

- Figure 30 gives a good example of the recommended layout. 

**==> picture [273 x 265] intentionally omitted <==**

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CIN1 CIN2<br>VIN<br>M<br>L<br>GND GND<br>K<br>J<br>H<br>G<br>SGND<br>F<br>COUT1 E COUT2<br>D<br>C<br>B<br>A<br>1 2 3 4 5 6 7 8 9 10 11 12<br>GND<br>VOUT1 VOUT2<br>CNTRL 4652 F30<br>**----- End of picture text -----**<br>


**Figure 30. Recommended PCB Layout** 

Rev. A 

27 

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LTM4652 

## **APPLICATIONS INFORMATION** 

**Table 2. 1.0V Output** 

|**Table 2. 1.0V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW (LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figure 18, Figure 19|5, 12|Figure 15|0|None|8.0|
|Figure 18, Figure 19|5, 12|Figure 15|200|None|6.6|
|Figure 18, Figure 19|5, 12|Figure 15|400|None|5.6|
|Figure 20, Figure 21|5, 12|Figure 15|0|BGA Heat Sink|7.6|
|Figure 20, Figure 21|5, 12|Figure 15|200|BGA Heat Sink|5.9|
|Figure 20, Figure 21|5, 12|Figure 15|400|BGA Heat Sink|5.0|



## **Table 3. 1.8V Output** 

|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW (LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|---|---|---|---|---|---|
|Figure 22, Figure 23|5, 12|Figure 16|0|None|8.0|
|Figure 22, Figure 23|5, 12|Figure 16|200|None|6.3|
|Figure 22, Figure 23|5, 12|Figure 16|400|None|5.3|
|Figure 24, Figure 25|5, 12|Figure 16|0|BGA Heat Sink|7.6|
|Figure 24, Figure 25|5, 12|Figure 16|200|BGA Heat Sink|5.5|
|Figure 24, Figure 25|5, 12|Figure 16|400|BGA Heat Sink|4.6|



## **Table 4. 3.3V Output** 

|**Table 4. 3.3V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW (LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figure 26, Figure 27|5, 12|Figure 17|0|None|7.9|
|Figure 26, Figure 27|5, 12|Figure 17|200|None|6.0|
|Figure 26, Figure 27|5, 12|Figure 17|400|None|5.1|
|Figure 28, Figure 29|5, 12|Figure 17|0|BGA Heat Sink|7.6|
|Figure 28, Figure 29|5, 12|Figure 17|200|BGA Heat Sink|5.4|
|Figure 28, Figure 29|5, 12|Figure 17|400|BGA Heat Sink|4.2|



**Table 5. Heat Sink and Thermally Conductive Adhesive Tape Part Numbers** 

|**MANUFACTURER**|**DEVICE**|**PART NUMBER**|**WEBSITE**|
|---|---|---|---|
|Boyd Corp.|Heat Sink|375424B00034G|www.boydcorp.com|
|Chomerics|Tape|T411|www.chomerics.com|



Rev. A 

28 

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LTM4652 

## **APPLICATIONS INFORMATION** 

**Table 6. Output Voltage Response vs Component Matrix (Refer to Figure 31) Load Step Typical Measured Values (2-Phase Single Output Solution)** 

|<br>**(2-Phase Single Output Solution)**|<br>**(2-Phase Single Output Solution)**|<br>**(2-Phase Single Output Solution)**|||||||
|---|---|---|---|---|---|---|---|---|
|**CIN(CERAMIC)**|||**COUT (CERAMIC)**|||**COUT (BULK)**|||
|**VENDOR **|**VALUE**|**PART NUMBER**|**VENDOR**|**VALUE**|**PART NUMBER**|**VENDOR**|**VALUE**|**PART NUMBER**|
|Murata|22μF, 16V, X5R, 1210|GRM32ER61C226KE20L|Murata|100μF,<br>6.3V,<br>X5R,<br>1210|GRM32ER60J107ME20L|Panasonic|470μF,<br>2.5V,<br>3mΩ|EEFGX0E4TIR|
|Murata|22μF, 16V, X5R, 1206|GRM31CR61C226KE15K|Murata|220μF,<br>4V, X5R,<br>1206|GRM31CR60G227M|Panasonic|470μF,<br>6.3V,<br>10mΩ|6TPF470MAH|
|TDK|22μF, 16V, X5R, 1210|C3225X5R1C226M250AA|Taiyo Yuden|100μF,<br>6.3V,<br>X5R,<br>1210|JMK325BJ107MM-T||||
||||Taiyo Yuden|220µF,<br>4V, X5R,<br>1210|AMK325ABJ227MM-T||||



## **25% Load Step (0A to 12.5A) Ceramic Output Capacitor Only Solutions** 

|**VIN**<br>**(V)**|**VOUT**<br>**(V)**|**CIN****<br>**BULK**<br>**(μF)**|**CIN**<br>**CERAMIC**<br>**(μF)**|**COUT**<br>**(BULK)**|**COUT**<br>**CERAMIC**<br>**(μF)**|**COMP PIN**<br>**RESISTOR**<br>**RTH**<br>**(kΩ)**|**COMP PIN**<br>**CAPACITOR**<br>**CTH**<br>**(pF)**|**COMP PIN**<br>**PARALLELING**<br>**CAPACITOR**<br>**CTHP**<br>**(pF)**|**FEED-**<br>**FORWARD**<br>**CAPACITOR**<br>**CFF (pF)**|**PEAK-**<br>**PEAK**<br>**DEVIATION**<br>**(mV)**|**SETTLING**<br>**TIME**<br>**tSETTLE**<br>**(μs)**|**LOAD**<br>**STEP**<br>**(A)**|**LOAD STEP**<br>**SLEW**<br>**RATE**<br>**(A/μs)**|**RFB**<br>**(kΩ)**|**FREQ**<br>**(kHz)**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|12|1|150|22 ×4|None|220 ×8|3.32|6800|None|68|62|40|12.5|10|90.9|300|
|12|1.2|150|22 ×4|None|220 ×8|3.32|6800|None|68|51|40|12.5|10|60.4|400|
|12|1.5|150|22 ×4|None|220 ×8|3.32|6800|None|68|61|40|12.5|10|40.2|400|
|12|1.8|150|22 ×4|None|220 ×8|3.32|6800|None|68|58|40|12.5|10|30.2|500|
|12|2.5|150|22 ×4|None|220 ×8|3.32|6800|None|68|70|50|12.5|10|19.1|500|
|12|3.3|150|22 ×4|None|220 ×8|3.32|6800|None|68|70|60|12.5|10|13.3|600|
|12|5|Suggest to Use POSCAP + Ceramic Cap||||||||||||||



## **25% Load Step (0A to 12.5A) Bulk + Ceramic Output Capacitor Solutions** 

|**VIN**<br>**(V)**|**VOUT**<br>**(V)**|**CIN****<br>**BULK**<br>**(μF)**|**CIN**<br>**CERAMIC**<br>**(μF)**|**COUT**<br>**(BULK)**|**COUT**<br>**CERAMIC**<br>**(μF)**|**COMP PIN**<br>**RESISTOR**<br>**RTH**<br>**(kΩ)**|**COMP PIN**<br>**CAPACITOR**<br>**CTH**<br>**(pF)**|**COMP PIN**<br>**PARALLELING**<br>**CAPACITOR**<br>**CTHP**<br>**(pF)**|**FEED-**<br>**FORWARD**<br>**CAPACITOR**<br>**CFF (pF)**|**PEAK-**<br>**PEAK**<br>**DEVIATION**<br>**(mV)**|**SETTLING**<br>**TIME**<br>**tSETTLE**<br>**(μs)**|**LOAD**<br>**STEP**<br>**(A)**|**LOAD STEP**<br>**SLEW**<br>**RATE**<br>**(A/μs)**|**RFB**<br>**(kΩ)**|**FREQ**<br>**(kHz)**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|12|1|150|22 ×4|470 ×2|100 ×4|4.64|4700|10|68|54|30|12.5|10|90.9|300|
|12|1.2|150|22 ×4|470 ×2|100 ×4|4.64|4700|10|68|50|30|12.5|10|60.4|400|
|12|1.5|150|22 ×4|470 ×2|100 ×4|4.64|4700|10|68|57|30|12.5|10|40.2|400|
|12|1.8|150|22 ×4|470 ×2|100 ×4|4.64|4700|10|68|57|40|12.5|10|30.2|500|
|12|2.5|150|22 ×4|470 ×2|100 ×4|4.64|4700|10|68|72|50|12.5|10|19.1|500|
|12|3.3|150|22 ×4|470 ×2|100 ×4|9.09|4700|10|None|89|60|12.5|10|13.3|600|
|12|5|150|22 ×4|470 ×2|100 ×4|9.09|4700|10|None|90|60|12.5|10|8.25|750|



*Different Bulk COUT1 used. See Part Number above. 

- **CIN (BULK) may be required with long PCB traces. 

Rev. A 

29 

For more information www.analog.com 

LTM4652 

## **TYPICAL APPLICATION** 

**==> picture [428 x 267] intentionally omitted <==**

**----- Start of picture text -----**<br>
INTVCC<br>C10 R2<br>4.7µF 10k<br>PGOOD1<br>4.5V TO 18VVIN + 4.5V TO 18V INTERMEDIATE BUSC(OPT)IN C22µF25VIN R7845k VINMODE_PLLIN INTVCC PGOOD1VVOUTS1OUT1 CFF1* 220µF4VCOUT1 V1.5V AT±25AOUT1<br>×4 VINOVP 68pF ×4<br>TRACK1 V FB1<br>TRACK1<br>C5 TRACK2 VFB2 RFB1<br>0.1µF TRACK2 RFB2 40.2k<br>C90.1µF COMP1 LTM4652 60.4k<br>R6.65kTH COMP2 CFF2*<br>CTH R6.65kTH VOUTS2 68pF<br>3300pF CTH DIFFOUT 1.2V AT ±25AVOUT2<br>3300pF<br>PINS NOT USED IN  fSET VOUT2<br>THIS CIRCUIT: INTVCC COUT1<br>CLKOUT, EXTVCC,  PHASMD R3 220µF<br>SW1, SW2, R4 10k 4V<br>RUN1, RUN2, 120k PGOOD2 PGOOD2 ×4<br>TEMP [+] , TEMP [–] SGND GND DIFFP DIFFN<br>4652 F31<br>*SEE TABLE 6.<br>**----- End of picture text -----**<br>


**Figure 31. Typical 4.5VIN to 18VIN, 1.5V and 1.2V at ±25A Outputs** 

Rev. A 

30 

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LTM4652 

## **TYPICAL APPLICATION** 

**==> picture [396 x 240] intentionally omitted <==**

**----- Start of picture text -----**<br>
INTVCC<br>INTVCC<br>C10 R2<br>Lf 4.7µF 10k PGOOD<br>MODE_PLLIN INTVCC PGOOD1<br>4.5V TO 18VVIN C22µFIN VIN VVOUT1OUT2 _ COUT1 V1V±50AOUT<br>r 25V RUN1 VOUTS1 220µF<br>×4 RUN — RUN2 CFF 4V<br>68pF ×8<br>TRACK1 VFB1<br>— LTM4652<br>T RACK2 VFB2 R5 LOAD<br>C9 COMP1 90.9k 1V AT ±50A<br>o s 0.1µF | COM P2 F Ty<br>RTH<br>3.32k<br>PINS NOT USED IN  CTH<br>THIS CIRCUIT: = 6800pF =<br>CLKOUT, EXTVCC,  fSET PGOO D2 PGOOD<br>SW1, SW2, VOUTS2,<br>TEMP [+] , TEMP [–] ,  PHASMD<br>VINOVP R4<br>75k<br>SGND GND DIFFN DIFFP DIFFOUT 4652 F32a<br>TL<br>**----- End of picture text -----**<br>


**==> picture [169 x 83] intentionally omitted <==**

**----- Start of picture text -----**<br>
VOUT (AC)<br>50mV/DIV<br>LOAD STEP<br>10A/DIV<br>100µs/DIV 4652 F32b<br>**----- End of picture text -----**<br>


**==> picture [219 x 22] intentionally omitted <==**

**----- Start of picture text -----**<br>
(b) 25% Load Step Transient Response; 12VIN, 1.0VOUT,<br>50A per Above Circuit<br>**----- End of picture text -----**<br>


**==> picture [327 x 98] intentionally omitted <==**

**----- Start of picture text -----**<br>
— | | Py sd | TINE 36.000<br>sono | | Ea ty te OTA coo<br>saan | Mav SS | | | te | AMY 35.000<br>ao000 bl a (| Seon Seen NUM +> o00<br>-64.000 I | | | | il | | | | | | SSS -144.000<br>6000 le deleted lledellAtcoedentetatoma -'**°°°<br>100 1k 10k 100 k 1M<br>FREQUENCY (Hz)<br>(c) 12VIN, 1.0VOUT, 50A Bode Plot per Above Circuit<br>GAIN (dB)  PHASE (Deg)<br>**----- End of picture text -----**<br>


**Figure 32. LTM4652 2-Phase, 1V at 50A** 

Rev. A 

31 

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LTM4652 

## **TYPICAL APPLICATION** 

**==> picture [504 x 356] intentionally omitted <==**

**----- Start of picture text -----**<br>
INTVCC<br>C10 R2<br>4.7µF 10k<br>PGOOD1<br>4.5V TO 18VVIN C422µF25V C322µF25V C222µF25V C122µF25V R6845k VIN MODE_PLLIN INTVCC PGOOD1VVOUTS1OUT1 C220µF4VOUT1 + 470µF4V V2.5V±25AOUT1<br>VINOVP ×2 LOAD<br>TRACK1 VFB1 R5 2.5V AT ±25A<br>C5 TRACK2 LTM4652 VOUTS2 19.1k<br>0.1µF R9 R7 COMP1 DIFFOUT<br>V2.5VOUT160.4k 13.3k R9.31kTHCTH 18.2kRTH COMP2 VOUT2 C220µF4VOUT1 + 470µF4V ±25A3.3V ATVOUT2<br>2200pF CTH VFB2 ×2<br>2200pF 13.3k LOAD<br>fSET 4652 F36 3.3V AT ±25A<br>R4 PHASMD DIFFP<br>140k SGND GND TEMP [–] TEMP [+] PGOOD2 DIFFN 4652 F33<br>PGOOD2<br>10k<br>PINS NOT USED IN  INTVCC 10Ω<br>THIS CIRCUIT:<br>CLKOUT, EXTVCC,  0.1µF<br>SW1, SW2, RUN<br>D [+] VCC VREF<br>470pF LTC2997*<br>D [–] GND VPTAT 4mV/K >1k VPTAT(FILTER)<br>CFILTER<br>*PLACE 470pF DIRECTLY ACROSS THE LTC2997’S D [+] /D [–]  PINS. OPTIONAL ANALOG OUTPUT<br>  ROUTE TEMP [+] /TEMP [–]  DIFFERENTIALLY TO D [+] /D [–]  AND PROTECT FROM NOISE WITH GROUND SHIELDING. TEMPERATURE INDICATOR<br>  TERMINATE (CONNECT) THE D [+] /D [–]  GROUND SHIELD AT THE LTC2997 GND PIN, ONLY.<br>  FOR BEST VPTAT PERFORMANCE, THE VCC PIN OF THE LTC2997 MUST BE LOCALLY BYPASSED AND QUIET.<br>  SEE LTC2997 DATA SHEET AND APRIL 2017 LT JOURNAL TECHNICAL ARTICLES.<br>**----- End of picture text -----**<br>


## **Figure 33. LTM4652 2.5V and 3.3V Output with Tracking Function** 

Rev. A 

32 

For more information www.analog.com 

LTM4652 

## **TYPICAL APPLICATION** 

**==> picture [441 x 453] intentionally omitted <==**

**----- Start of picture text -----**<br>
INTVCC<br>C10 R2<br>4.7µF 5k<br>CLK1<br>PGOOD<br>MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1<br>VIN<br>4.5V TO 18V C222µF R6845k VV INOVP IN V VOUTS1OUT1 C220µFOUT1<br>25V RUN1 SW1 68pF 4V<br>×4 RUN RUN2 VFB1 VFB ×8<br>TRACK TRACK1 VFB2 R5<br>LTM4652 60.4k<br>TRACK2<br>COMP1<br>COMP COMP2<br>RTH<br>3.32k<br>CTH VOUTS2<br>6800pF VOUT2<br>fSET S W2<br>R4 PHASMD PGOO D2 PGOOD<br>75k SGND GND DIFFP DIFFN DIFFOUT<br>VOUT<br>1.2V<br>±100A<br>C16<br>4.7µF<br>CLK1 PGOOD<br>MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1<br>VIN VOUT1<br>C1522µF R9845k VINOVP VOUTS1 C220µFOUT1<br>25V RUN RUN1 SW1 4V<br>×4 ×8<br>RUN2 VFB1 VFB<br>TRACK TRACK1 VFB2<br>LTM4652<br>TRACK2<br>COMP COMP1 VOUTS2<br>C19 RTH COMP2 VOUT2<br>0.22µF 3.32kCTH fSET S W2<br>6800pF PHASMD PGOO D2 PGOOD<br>R10<br>SGND GND DIFFP DIFFN DIFFOUT<br>PINS NOT USED IN  75k 4652 F34<br>THIS CIRCUIT:<br>TEMP [+] , TEMP [–] INTVCC<br>**----- End of picture text -----**<br>


**Figure 34. LTM4652 4-Phase, 1.2V at 100A** 

Rev. A 

33 

For more information www.analog.com 

LTM4652 

## **TYPICAL APPLICATION** 

**==> picture [473 x 248] intentionally omitted <==**

**----- Start of picture text -----**<br>
INTVCC<br>INTVCC<br>C10 R2<br>VOUT [–] 4.7µF 10k<br>VOUT [–] PGOOD<br>MODE_PLLIN INTVCC PGOOD1<br>4.5V TO 13VVIN C22µFIN C22µFINOUT VIN EXTVVOUT1CC<br>16V×8 25V×2 RUN1 VOUT1<br>VOUT [–] RUN RUN2 VOUTS1 C220µFOUT1<br>TRACK1 6.3V<br>T RACK2 LTM4652 VFB1 ×8<br>C90.1µF COM COMP1P2 VFB2 R5 LOAD<br>RTH 8.25k<br>2k CTHP VOUT [–]<br>CTH 330pF –5V<br>47nF (UP TO ±32A, 9VIN)<br>INTVCC fSET PGOO D2 PGOOD<br>PHASMD<br>SGND GND DIFFN DIFFP DIFFOUT 4652 F35<br>**----- End of picture text -----**<br>


PINS NOT USED IN THIS CIRCUIT: 

CLKOUT,  SW1, SW2, VOUTS2, TEMP[+] , TEMP[–] , VINOVP 

**Figure 35. LTM4652 Regulating –5V at Up to ±32A (at 9VIN); See Demo Boards DC3230A and DC3195A for More Details (Including Performance of PolyPhase and Multimodule Parallel Applications)** 

Rev. A 

34 

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LTM4652 

## **PACKAGE DESCRIPTION** 

## **LTM4652 Component BGA Pinout** 

|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|A1|VOUT1|B1|VOUT1|C1|VOUT1|D1|GND|E1|GND|F1|GND|
|A2|VOUT1|B2|VOUT1|C2|VOUT1|D2|GND|E2|GND|F2|GND|
|A3|VOUT1|B3|VOUT1|C3|VOUT1|D3|GND|E3|GND|F3|GND|
|A4|VOUT1|B4|VOUT1|C4|VOUT1|D4|GND|E4|GND|F4|MODE_PLLIN|
|A5|VOUT1|B5|VOUT1|C5|VOUTS1|D5|VFB1|E5|TRACK1|F5|RUN1|
|A6|GND|B6|GND|C6|fSET|D6|SGND|E6|COMP1|F6|SGND|
|A7|GND|B7|GND|C7|SGND|D7|VFB2|E7|COMP2|F7|SGND|
|A8|VOUT2|B8|VOUT2|C8|VOUTS2|D8|TRACK2|E8|DIFFP|F8|DIFFOUT|
|A9|VOUT2|B9|VOUT2|C9|VOUT2|D9|GND|E9|DIFFN|F9|RUN2|
|A10|VOUT2|B10|VOUT2|C10|VOUT2|D10|GND|E10|GND|F10|GND|
|A11|VOUT2|B11|VOUT2|C11|VOUT2|D11|GND|E11|GND|F11|GND|
|A12|VOUT2|B12|VOUT2|C12|VOUT2|D12|GND|E12|GND|F12|GND|
|||||||||||||
|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|
|G1|GND|H1|GND|J1|GND|K1|GND|L1|GND|M1|GND|
|G2|SW1|H2|GND|J2|VIN|K2|VIN|L2|VIN|M2|VIN|
|G3|GND|H3|GND|J3|VIN|K3|VIN|L3|VIN|M3|VIN|
|G4|PHASMD|H4|GND|J4|VIN|K4|VIN|L4|VIN|M4|VIN|
|G5|CLKOUT|H5|VINOVP|J5|GND|K5|GND|L5|VIN|M5|VIN|
|G6|SGND|H6|TEMP–|J6|TEMP+|K6|GND|L6|VIN|M6|VIN|
|G7|SGND|H7|GND|J7|EXTVCC|K7|GND|L7|VIN|M7|VIN|
|G8|PGOOD2|H8|INTVCC|J8|GND|K8|GND|L8|VIN|M8|VIN|
|G9|PGOOD1|H9|GND|J9|VIN|K9|VIN|L9|VIN|M9|VIN|
|G10|GND|H10|GND|J10|VIN|K10|VIN|L10|VIN|M10|VIN|
|G11|SW2|H11|GND|J11|VIN|K11|VIN|L11|VIN|M11|VIN|
|G12|GND|H12|GND|J12|GND|K12|GND|L12|GND|M12|GND|



Rev. A 

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LTM4652 

## **PACKAGE DESCRIPTION** 

**==> picture [463 x 612] intentionally omitted <==**

**----- Start of picture text -----**<br>
ddd M Z X Y<br>eee M Z<br>6<br>3<br>SEE NOTES<br>PIN 1 Øb (144 PLACES) SEE NOTES<br>1 2 3 4 5 6 7 8 9 10 11 12<br>A<br>B<br>C<br>D<br>e<br>E<br>F<br>G<br>G<br>H<br>J PACKAGE BOTTOM VIEW<br>K PACKAGE ROW AND COLUMN LABELING MAY VARY  AMONG µModule PRODUCTS. REVIEW EACH PACKAGE  LAYOUT CAREFULLY<br>!<br>L b DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER MAY BE EITHER A MOLD OR  MARKED FEATURE<br>M NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3        BALL DESIGNATION PER JEP95 4 5. PRIMARY DATUM -Z- IS SEATING PLANE 6<br>b e<br>F<br>NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT<br>A A2<br>DETAIL A MAX 5.12 0.70 4.42 0.90 0.66 0.15 0.10 0.20 0.30 0.15<br>PACKAGE SIDE VIEW<br>DIMENSIONS NOM 4.92 0.60 4.32 0.75 0.63 16.00 16.00 1.27 13.97 13.97<br>0.32 REF 4.00 REF<br>H1<br>A1 SUBSTRATE MIN 4.72 0.50 4.22 0.60 0.60<br>16mm × 16mm × 4.92mm TOTAL NUMBER OF BALLS: 144<br>(Reference DWG # 05-08-7064) b1<br>ccc Z MOLD CAP H2 DETAIL A A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee<br>SYMBOL<br>aaa Z<br>144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 2× D X Y 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850<br>E<br>TOP VIEW<br>PACKAGE TOP VIEW<br>SUGGESTED PCB LAYOUT<br>4<br>PIN 1<br>CORNER<br>0.630 REF Ø 144x<br>10-19-2022-B<br>Z<br>Z<br>// bbb Z<br>6.9850<br>5.7150<br>4.4450<br>3.1750<br>1.9050<br>0.6350<br>0.0000<br>0.6350<br>1.9050<br>3.1750<br>4.4450<br>5.7150<br>6.9850<br>aaa Z ×2<br>**----- End of picture text -----**<br>


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LTM4652 

## **REVISION HISTORY** 

|**REV**|**DATE**|**DESCRIPTION**|**PAGE NUMBER**|
|---|---|---|---|
|A|3/23|Changed master to main and slave to subordinate.<br>Updated Electrical Characteristics (fSYNC, Each Channel)<br>Corrected pin function names for PHASMD, VOUTS1and VOUTS2in Figure 1 (Block Diagram) and Pinout table.<br>Updated package drawing.|All<br>3<br>11, 35<br>36|



Rev. A 

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implicatiFor more informati **on** or otherwise under any patent or patent rights of Analog Devices.www.analog.com 

37 

LTM4652 

## **PACKAGE PHOTOS** 

**Part marking is either ink mark or laser mark** 

## **DESIGN RESOURCES** 

|**DESIGN RESOURCES**|||
|---|---|---|
|**SUBJECT**|**DESCRIPTION**||
|µModule Design and Manufacturing Resources|Design:<br>• Selector Guides<br>• Demo Boards and Gerber Files<br>• Free Simulation Tools|Manufacturing:<br>• Quick Start Guide<br>• PCB Design, Assembly and Manufacturing Guidelines<br>• Package and Board Level Reliability|
|µModule Regulator Products Search|1.  Sort table of products by parameters and download the result as a spread sheet.<br>2. Search using the Quick Power Search parametric table.<br>INPUT |<br>Vin(Min)<br>Vv<br>Vin(Max)<br>Vv<br>OUTPUT |<br>Vout<br>Vv<br>Jout<br>A<br>FEATURES |<br>Low EMI<br>Ultrathin<br>Internal Heat Sink<br>(Multiple Outputs}<br>Outputs||
|Digital Power System Management|Analog Devices’ family of digital power supply management ICs are highly integrated solutions that<br>offer essential functions, including power supply monitoring, supervision, margining and sequencing,<br>and feature EEPROM for storing user configurations and fault logging.||



## **RELATED PARTS** 

|**PART NUMBER**|**DESCRIPTION**|**COMMENTS**|
|---|---|---|
|LTM8064|58VIN, ±6A, CVCCµModule Regulator|6V ≤ VIN≤ 58V, 1.2V ≤ VOUT≤ 36V; 16mm × 11.9mm × 4.92mm(BGA)|
|LTM8052|36VIN, ±5A, CVCCµModule Regulator|6V ≤ VIN≤ 36V, 1.2V ≤ VOUT≤ 24V; 15mm × 11.25mm × 2.82mm (LGA) and<br>15mm × 11.25mm × 3.42mm(BGA)|
|LTM4650|Dual 25A or Single 50A µModule Regulator|4.5V ≤ VIN≤ 15V, 0.6V ≤ VOUT≤ 1.8V; 16mm × 16mm × 5.01mm(BGA)|
|LTM4650A|Dual 25A or Single 50A µModule Regulator,<br>Up to 5.5VOUT|4.5V ≤ VIN≤ 16V, 0.6V ≤ VOUT≤ 5.5V; 16mm × 16mm × 5.01mm (BGA)|
|LTM4650A-1|Dual 25A or Single 50A µModule Regulator,<br>Up to 5.5VOUTand External Compensation|4.5V ≤ VIN≤ 16V, 0.6V ≤ VOUT≤ 5.5V; 16mm × 16mm × 5.01mm (BGA)|
|LTM4630A|Lower Current and Higher VOUTthan LTM4650,<br>Up to 5.3VOUT, Dual 18A or Single 36A|Pin Compatible with LTM4650; 4.5V ≤ VIN≤ 18V, 0.6V ≤ VOUT≤ 8V,<br>16mm × 16mm × 4.41mm(LGA), 16mm × 16mm × 5.01mm(BGA)|
|LTM4620A|Lower Current and Higher VOUTthan LTM4650,<br>Up to 5.3VOUT, Dual 13A or Single 26A|Pin Compatible with LTM4650; 4.5V ≤ VIN≤ 16V, 0.6V ≤ VOUT≤ 5.3V,<br>15mm 15mm × 4.41mm(LGA)and 15mm × 15mm × 5.01mm(BGA)|



Rev. A 

2/22 www.analog.com 

38 

 ANALOG DEVICES, INC. 2023 

For more information www.analog.com
Updated at April 10, 2026
Since its inception in 1965, Analog Devices has established itself as a global leader in the design and manufacturing of high-performance analog, mixed-signal, and digital signal processing (DSP) integrated circuits. The company is renowned for solving complex engineering challenges by providing critical technologies that seamlessly convert real-world phenomena into precise electrical signals for the industrial, automotive, communications, and consumer markets. Within its extensive portfolio, Analog Devices provides highly reliable clock, timing, and frequency management solutions, featuring a comprehensive array of precision timers, oscillators, and pulse generators. Complementing this core lineup is a robust offering of driver and interface ICs, particularly high-performance I/O expanders that enable seamless connectivity and streamline complex electronic system architectures. Beyond these foundational integrated circuits, Analog Devices leads the industry in sensor innovation, delivering advanced MEMS accelerometers and integrated MEMS modules designed for exceptional precision in motion sensing. To support complete hardware designs, the company's specialized offerings also encompass discrete bipolar transistors, sub-2.4GHz RF transceivers, temperature-compensated oscillators, and dedicated power management components such as DC/DC converters and LED driver ICs.
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