LTC6995IS6-1#TRMPBF

- - LTC6995 1/LTC6995 2 

## TimerBlox: Long Timer, Low Frequency Oscillator 

## **FEATURES** 

## **DESCRIPTION** 

- n **Period Range: 1ms to 9.5 Hours** 

- n **Timing Reset by Power-On or Reset Input** 

- n Configured with 1 to 3 Resistors 

- n <1.5% Maximum Frequency Error 

- n Programmable Output Polarity 

- n 2.25V to 5.5V Single Supply Operation 

- n 55µA to 80µA Supply Current 

- (2ms to 9.5hr Clock Period) 

- n 500µs Start-Up Time 

- n CMOS Output Driver Sources/Sinks 20mA 

- n –55°C to 125°C Operating Temperature Range 

- n Available in Low Profile (1mm) SOT-23 (ThinSOT™) and 2mm × 3mm DFN Packages 

- n AEC-Q100 Qualified for Automotive Applications 

## **APPLICATIONS** 

- n Power-On Reset Timer 

- n Long Time One Shot 

- n “Heartbeat” Timers 

- n Watchdog Timers 

- n Periodic “Wake-Up” Call 

- n High Vibration, High Acceleration Environments 

All registered trademarks and trademarks are the property of their respective owners. 

The LTC[®] 6995 is a silicon oscillator with a programmable period range of 1.024ms to 9.54 hours (29.1µHz to 977Hz), specifically intended for long duration timing events. The LTC6995 is part of the TimerBlox[®] family of versatile silicon timing devices. 

A single resistor, RSET , programs the LTC6995’s internal master oscillator frequency. The output clock period is determined by this master oscillator and an internal frequency divider, NDIV , programmable to eight settings from 1 to 2[21] . 

**==> picture [228 x 26] intentionally omitted <==**

When oscillating, the LTC6995 generates a 50% duty cycle square wave output. A reset function is provided to stop the master oscillator and clear internal dividers. Removing reset initiates a full output clock cycle which is useful for programmable power-on reset and watchdog timer applications. 

The LTC6995 has two versions of reset functionality. The reset input is active high for the LTC6995-1 and active low for the LTC6995-2. The polarity of the output when reset is selectable for both versions. 

|||**OUTPUT(OSCILLATOR START STATE)**|**OUTPUT(OSCILLATOR START STATE)**|
|---|---|---|---|
|**RST/RST**|**POLARITY**|**LTC6995-1**|**LTC6995-2**|
|0|0|Oscillating (Low)|0(Reset)|
|1|0|0(Reset)|Oscillating (Low)|
|0|1|Oscillating (High)|1(Reset)|
|1|1|1(Reset)|Oscillating (High)|



## **TYPICAL APPLICATION** 

## **Active Low Power-On Reset Timer** 

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RST OUT V [+]<br>LTC6995-1<br>GND V [+] V [+]<br>5 SECONDS<br>1M 0.1µF OUT 1/2 tOUT TIMER STOPPED<br>SET DIV POWER-ON RESET<br>118k 392k (1ms TO 4.8 HOURS)<br>699512 TA01<br>**----- End of picture text -----**<br>


Rev. B 

1 

For more information www.analog.com 

Document Feedback 

## - - LTC6995 1/LTC6995 2 

## **ABSOLUTE MAXIMUM RATINGS** 

## **(Note 1)** 

Supply Voltage (V[+] ) to GND ........................................6V Maximum Voltage 

Specified Temperature Range (Note 3) LTC6995C ................................................ 0°C to 70°C LTC6995I .............................................–40°C to 85°C LTC6995H .......................................... –40°C to 125°C LTC6995MP ....................................... –55°C to 125°C Junction Temperature ........................................... 150°C Storage Temperature Range ..................–65°C to 150°C Lead Temperature (Soldering, 10 sec) S6 Package ...........................................................300°C 

on Any Pin ................(GND – 0.3V) ≤ VPIN ≤ (V[+] + 0.3V) Operating Temperature Range (Note 2) LTC6995C ............................................–40°C to 85°C LTC6995I .............................................–40°C to 85°C LTC6995H .......................................... –40°C to 125°C LTC6995MP ....................................... –55°C to 125°C 

## **PIN CONFIGURATION** 

**==> picture [524 x 131] intentionally omitted <==**

**----- Start of picture text -----**<br>
LTC6995-1/LTC6995-2 LTC6995-1/LTC6995-2<br>TOP VIEW<br>TOP VIEW<br>V [+] 1 6 OUT<br>7 RST/RST 1 6 OUT<br>DIV 2 5 GND<br>GND<br>GND 2 5 V [+]<br>SET 3 4 RST/RST<br>SET 3 4 DIV<br>DCB PACKAGE S6 PACKAGE<br>6-LEAD (2mm × 3mm) PLASTIC DFN 6-LEAD PLASTIC TSOT-23<br>TJMAX = 150°C, θJA = 64°C/W, θJC = 9.6°C/W  TJMAX = 150°C, θJA = 192°C/W, θJC = 51°C/W<br>EXPOSED PAD (PIN 7) CONNECTED TO GND,<br>PCB CONNECTION OPTIONAL<br>**----- End of picture text -----**<br>


## **ORDER INFORMATION** 

## **Lead Free Finish** 

|**Lead Free Finish**|||||
|---|---|---|---|---|
|**TAPE AND REEL (MINI)**|**TAPE AND REEL**|**PART MARKING**|**PACKAGE DESCRIPTION**|**SPECIFIED TEMPERATURE RANGE**|
|LTC6995CDCB-1#TRMPBF|LTC6995CDCB-1#TRPBF|LGJM|6-Lead(2mm x 3mm)Plastic DFN|0°C to 70°C|
|LTC6995IDCB-1#TRMPBF|LTC6995IDCB-1#TRPBF|LGJM|6-Lead(2mm x 3mm)Plastic DFN|–40°C to 85°C|
|LTC6995HDCB-1#TRMPBF|LTC6995HDCB-1#TRPBF|LGJM|6-Lead(2mm x 3mm)Plastic DFN|–40°C to 125°C|
|LTC6995CS6-1#TRMPBF|LTC6995CS6-1#TRPBF|LTGJN|6-Lead Plastic TSOT-23|0°C to 70°C|
|LTC6995IS6-1#TRMPBF|LTC6995IS6-1#TRPBF|LTGJN|6-Lead Plastic TSOT-23|–40°C to 85°C|
|LTC6995HS6-1#TRMPBF|LTC6995HS6-1#TRPBF|LTGJN|6-Lead Plastic TSOT-23|–40°C to 125°C|
|LTC6995CDCB-2#TRMPBF|LTC6995CDCB-2#TRPBF|LGJP|6-Lead(2mm x 3mm)Plastic DFN|0°C to 70°C|
|LTC6995IDCB-2#TRMPBF|LTC6995IDCB-2#TRPBF|LGJP|6-Lead(2mm x 3mm)Plastic DFN|–40°C to 85°C|
|LTC6995HDCB-2#TRMPBF|LTC6995HDCB-2#TRPBF|LGJP|6-Lead(2mm x 3mm)Plastic DFN|–40°C to 125°C|
|LTC6995CS6-2#TRMPBF|LTC6995CS6-2#TRPBF|LTGJQ|6-Lead Plastic TSOT-23|0°C to 70°C|
|LTC6995IS6-2#TRMPBF|LTC6995IS6-2#TRPBF|LTGJQ|6-Lead Plastic TSOT-23|–40°C to 85°C|
|LTC6995HS6-2#TRMPBF|LTC6995HS6-2#TRPBF|LTGJQ|6-Lead Plastic TSOT-23|–40°C to 125°C|
|LTC6995MPS6-1#TRMPBF|LTC6995MPS6-1#TRPBF|LTGJN|6-Lead Plastic TSOT-23|–55°C to 125°C|
|LTC6995MPS6-2#TRMPBF|LTC6995MPS6-2#TRPBF|LTGJQ|6-Lead Plastic TSOT-23|–55°C to 125°C|



Rev. B 

2 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **ORDER INFORMATION** 

## **Lead Free Finish** 

## **AUTOMOTIVE PRODUCTS**** 

|**TAPE AND REEL (MINI)**|**TAPE AND REEL**|**PART MARKING**|**PACKAGE DESCRIPTION**|**SPECIFIED TEMPERATURE RANGE**|
|---|---|---|---|---|
|LTC6995IS6-1#WTRMPBF|LTC6995IS6-1#WTRPBF|LTGJN|6-Lead Plastic TSOT-23|–40°C to 85°C|
|LTC6995HS6-1#WTRMPBF|LTC6995HS6-1#WTRPBF|LTGJN|6-Lead Plastic TSOT-23|–40°C to 125°C|
|LTC6995IS6-2#WTRMPBF|LTC6995IS6-2#WTRPBF|LTGJQ|6-Lead Plastic TSOT-23|–40°C to 85°C|
|LTC6995HS6-2#WTRMPBF|LTC6995HS6-2#WTRPBF|LTGJQ|6-Lead Plastic TSOT-23|–40°C to 125°C|



Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 

****** Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. 

**ELECTRICAL CHARACTERISTICS The** l **denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Test conditions are V[+] = 2.25V to 5.5V, RST = 0V for LTC6995-1, RST = V[+] for LTC6995-2, DIVCODE = 0 to 15 (NDIV = 1 to 2[21] ), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|tOUT|Output Clock Period|||1.024m<br>34,360|Seconds|
|fOUT|Output Frequency|||29.1µ<br>977|Hz|
|∆fOUT|Frequency Accuracy (Note 4)|29.1µHz ≤ fOUT≤ 977Hz|l|±0.8<br>±1.5<br>±2.2|%<br>%|
|∆fOUT/∆T|FrequencyDrift Over Temperature||l|±0.005|%/°C|
|∆fOUT/∆V+|Frequency Drift Over Supply|V+= 4.5V to 5.5V<br>V+= 2.25V to 4.5V|l<br>l|0.23<br>0.06<br>0.55<br>0.16|%/V<br>%/V|
||Long-Term FrequencyStability|(Note 11)||90|ppm/√kHr|
||Period Jitter (Note 10)|NDIV= 1<br>NDIV= 8||15<br>7|ppmRMS<br>ppmRMS|
|BW|FrequencyModulation Bandwidth|||0.4 • fOUT|Hz|
|tS|FrequencyChange SettlingTime(Note 9)|||1|Cycle|
|**Analog Inputs**||||||
|VSET|Voltage at SET Pin||l|0.97<br>1.00<br>1.03|V|
|∆VSET/∆T|VSETDrift Over Temperature||l|±75|µV/°C|
|RSET|Frequency-SettingResistor||l|50<br>800|kΩ|
|VDIV|DIV Pin Voltage||l|0<br>V+|V|
|∆VDIV/∆V+|DIV Pin Valid Code Range (Note 5)|Deviation from Ideal<br>VDIV/V+=(DIVCODE + 0.5)/16|l|±1.5|%|
||DIV Pin Input Current||l|±10|nA|
|**Power Supply**||||||
|V+|OperatingSupplyVoltage Range||l|2.25<br>5.5|V|
||Power-On Reset Voltage||l|1.95|V|
|IS|Supply Current|RL= ∞, RSET= 50k<br>V+= 5.5V<br>V+= 2.25V|l<br>l|135<br>105<br>170<br>135|µA<br>µA|
|||RL= ∞, RSET= 100k<br>V+= 5.5V<br>V+= 2.25V|l<br>l|100<br>80<br>130<br>105|µA<br>µA|
|||RL= ∞, RSET= 800k<br>V+= 5.5V<br>V+= 2.25V|l<br>l|65<br>55<br>100<br>85|µA<br>µA|
|||RL= ∞, ISET= 0µA<br>V+= 5.5V<br>V+= 2.25V||60<br>52|µA<br>µA|
|||Rev. B||||



3 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

**ELECTRICAL CHARACTERISTICS The** l **denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Test conditions are V[+] = 2.25V to 5.5V, RST = 0V for LTC6995-1, RST = V[+] for LTC6995-2, DIVCODE = 0 to 15 (NDIV = 1 to 2[21] ), RSET = 50k to 800k, RLOAD =** ∞ **, CLOAD = 5pF unless otherwise noted.** 

|**RST = V+ for**|**LTC6995-2, DIVCODE = 0 to 15 (NDIV =**|**1 to 2), RSET = 50k to 800k, RLOAD =**∞**, CL**|**1 to 2), RSET = 50k to 800k, RLOAD =**∞**, CL**|**OAD = 5pF unless otherwise n**|**oted.**|
|---|---|---|---|---|---|
|**SYMBOL**|**PARAMETER**|**CONDITIONS**||**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|**Digital I/O**||||||
||RST Pin Input Capacitance|||2.5|pF|
||RST Pin Input Current|RST = 0V to V+||±10|nA|
|VIH|High Level RST Pin Input Voltage|(Note 6)|l|0.7 • V+|V|
|VIL|Low Level RST Pin Input Voltage|(Note 6)|l|0.3 • V+|V|
|IOUT(MAX)|Output Current|V+= 2.7V to 5.5V||±20|mA|
|VOH|High Level Output Voltage (Note 7)|V+= 5.5V<br>IOUT= –1mA<br>IOUT= –16mA|l<br>l|5.45<br>4.84<br>5.48<br>5.15|V<br>V|
|||V+= 3.3V<br>IOUT= –1mA<br>IOUT= –10mA|l<br>l|3.24<br>2.75<br>3.27<br>2.99|V<br>V|
|||V+= 2.25V<br>IOUT= –1mA<br>IOUT= –8mA|l<br>l|2.17<br>1.58<br>2.21<br>1.88|V<br>V|
|VOL|Low Level Output Voltage (Note 7)|V+= 5.5V<br>IOUT= 1mA<br>IOUT= 16mA|l<br>l|0.02<br>0.26<br>0.04<br>0.54|V<br>V|
|||V+= 3.3V<br>IOUT= 1mA<br>IOUT= 10mA|l<br>l|0.03<br>0.22<br>0.05<br>0.46|V<br>V|
|||V+= 2.25V<br>IOUT= 1mA<br>IOUT= 8mA|l<br>l|0.03<br>0.26<br>0.07<br>0.54|V<br>V|
|tRST|Reset Propagation Delay|V+= 5.5V<br>V+= 3.3V<br>V+= 2.25V||16<br>24<br>40|ns<br>ns<br>ns|
|tWIDTH|Minimum Input Pulse Width|V+= 3.3V||5|ns|
|tr|Output Rise Time (Note 8)|V+= 5.5V<br>V+= 3.3V<br>V+= 2.25V||1.1<br>1.7<br>2.7|ns<br>ns<br>ns|
|tf|Output Fall Time (Note 8)|V+= 5.5V<br>V+= 3.3V<br>V+= 2.25V||1.0<br>1.6<br>2.4|ns<br>ns<br>ns|



**Note 1:** Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 

**Note 2:** The LTC6995C is guaranteed functional over the operating temperature range of –40°C to 85°C. 

**Note 3:** The LTC6995C is guaranteed to meet specified performance from 0°C to 70°C. The LTC6995C is designed, characterized and expected to meet specified performance from –40°C to 85°C but it is not tested or QA sampled at these temperatures. The LTC6995I is guaranteed to meet specified performance from –40°C to 85°C. The LTC6995H is guaranteed to meet specified performance from –40°C to 125°C. The LTC6995MP is guaranteed to meet specified performance from –55°C to 125°C. 

**Note 4:** Frequency accuracy is defined as the deviation from the fOUT equation, assuming RSET is used to program the frequency. 

**Note 5:** See Operation section, Table 1 and Figure 2 for a full explanation of how the DIV pin voltage selects the value of DIVCODE. 

**Note 6:** The RST pin has hysteresis to accommodate slow rising or falling signals. The threshold voltages are proportional to V[+] . Typical values can be estimated at any supply voltage using VRST(RISING) ≈ 0.55 • V[+] + 185mV and V ≈ 0.48 • V[+] – 155mV. RST(FALLING) 

**Note 7:** To conform to the Logic IC Standard, current out of a pin is arbitrarily given a negative value. 

**Note 8:** Output rise and fall times are measured between the 10% and the 90% power supply levels with 5pF output load. These specifications are based on characterization. 

**Note 9:** Settling time is the amount of time required for the output to settle within ±1% of the final frequency after a 0.5× or 2× change in ISET . **Note 10:** Jitter is the ratio of the deviation of the period to the mean of the period. This specification is based on characterization and is not 100% tested. 

**Note 11:** Long-term drift of silicon oscillators is primarily due to the movement of ions and impurities within the silicon and is tested at 30°C under otherwise nominal operating conditions. Long-term drift is specified as ppm/√kHr due to the typically nonlinear nature of the drift. To calculate drift for a set time period, translate that time into thousands of hours, take the square root and multiply by the typical drift number. For instance, a year is 8.77kHr and would yield a drift of 266ppm at 90ppm/√kHr. Drift without power applied to the device may be approximated as 1/10th of the drift with power, or 9ppm/√kHr for a 90ppm/√kHr device. 

Rev. B 

4 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**V[+] = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.** 

**==> picture [519 x 560] intentionally omitted <==**

**----- Start of picture text -----**<br>
Frequency Error vs Temperature Frequency Error vs Temperature Frequency Error vs Temperature<br>3 3 3<br>GUARANTEED MAX OVER TEMPERATURE GUARANTEED MAX OVER TEMPERATURE GUARANTEED MAX OVER TEMPERATURE<br>2 2 2<br>RSET = 50k RSET = 200k RSET = 800k<br>3 PARTS 3 PARTS 3 PARTS<br>1 1 1<br>0 0 0<br>–1 –1 –1<br>–2 GUARANTEED MIN OVER TEMPERATURE –2 GUARANTEED MIN OVER TEMPERATURE –2 GUARANTEED MIN OVER TEMPERATURE<br>–3 –3 –3<br>–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125<br>TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)<br>699512 G01 699512 G02 699512 G03<br>Frequency Error vs RSET Frequency Drift vs Supply Voltage Typical VSET Distribution<br>3 0.5 250<br>2 LOTS<br>GUARANTEED MAX OVER TEMPERATURE 0.4 DFN AND SOT-23<br>2 1274 UNITS<br>3 PARTS 0.3 200<br>0.2<br>1<br>0.1 150<br>0 0<br>–0.1 100<br>–1<br>–0.2<br>REFERENCED TO V [+]  = 4.5V<br>–2 GUARANTEED MIN OVER TEMPERATURE –0.3 R SET  = 50k 50<br>–0.4 R SET  = 200k<br>RSET = 800k<br>–3 –0.5 0<br>0 200 400 600 800 2 3 4 5 6 0.98 0.988 0.996 1.004 1.012 1.02<br>RSET (kΩ) SUPPLY VOLTAGE (V) VSET (V)<br>699512 G04 699512 G05 699512 G06<br>VSET Drift vs ISET VSET Drift vs Supply VSET vs Temperature<br>1.0 1.0 1.020<br>3 PARTS<br>0.8 0.8<br>1.015<br>0.6 0.6<br>1.010<br>0.4 0.4<br>0.2 0.2 1.005<br>0 0 1.000<br>–0.2 –0.2<br>0.995<br>–0.4 –0.4<br>0.990<br>–0.6 –0.6<br>–0.8 –0.8 0.985<br>REFERENCED TO ISET = 10µA REFERENCED TO V [+]  = 4V<br>–1.0 –1.0 0.980<br>0 5 10 15 20 2 3 4 5 6 –50 –25 0 25 50 75 100 125<br>ISET (µA) SUPPLY (V) TEMPERATURE (°C)<br>699512 G07 699512 G08 699512 G09<br>ERROR (%) ERROR (%) ERROR (%)<br>ERROR (%) DRIFT (%)<br>NUMBER OF UNITS<br> (mV)  (V)<br>VSET DRIFT (mV) VSET<br>**----- End of picture text -----**<br>


Rev. B 

5 

For more information www.analog.com 

## - - LTC6995 1/LTC6995 2 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**V[+] = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.** 

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Supply Current<br>vs RST Pin Voltage<br>**----- End of picture text -----**<br>


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Supply Current vs Supply Voltage Supply Current vs Temperature vs RST Pin Voltage<br>150 150 250<br>RSET = 800k<br>RSET = 50k<br>125 125 200 5V 5V<br>RST FALLING<br>5V, RSET = 100k RST RISING<br>100 R SET  = 100k 100<br>RSET = 200k FE 2.5V, RSET = 100k E 150 ao<br>75 75 T 5V, RSET = 800k e RST FALLING3.3V ( 3.3VRST RISING<br>rr_| || |a[| 4 100 waZ 1 AX<br>50 RSET = 800k 50 2.5V, RSET = 800k<br>25 25 P| | 50 2Z2aNG@<br>0 0 0 | | tl<br>2 3 4 5 6 –50 –25 0 25 50 75 100 125 0 0.2 0.4 0.6 0.8 1.0<br>SUPPLY VOLTAGE (V) TEMPERATURE (°C) VRST/V [+]  (V/V)<br>699512 G10 699512 G11 699512 G12<br>RST Threshold Voltage<br>Supply Current vs RSET Typical ISET Current Limit vs V [+] vs Supply Voltage<br>150 1000 3.5<br>SET PIN SHORTED TO GND<br>125 3.0<br>V [+]  = 5V 800 POSITIVE-GOING<br>2.5<br>100<br>600<br>V [+]  = 3.3V 2.0<br>75 NEGATIVE-GOING<br>1.5<br>400<br>50 ——— V [+]  = 2.5V<br>1.0<br>25 rt of 200<br>0.5<br>0 0 0<br>0 200 400 600 800 2 3 4 5 6 2 3 4 5 6<br>RSET (kΩ) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)<br>699512 G14 699512 G15<br>699512 G13<br>Reset Propagation Delay (tRST)  Rise and Fall Time  Typical Frequency Error<br>vs Supply Voltage vs Supply Voltage vs Time (Long-Term Drift)<br>50 3.0 200<br>CLOAD = 5pF CLOAD = 5pF 65 UNITS<br>45 150 SOT-23 AND DFN PARTS<br>40 2.5 TA = 30°C<br>100<br>35<br>2.0<br>50<br>30 tRISE<br>25 1.5 0<br>20 tFALL –50 sie ee MRE i Gs oe ony Mee ONE ANA,<br>1.0<br>15<br>–100<br>10<br>0.5<br>5 –150<br>0 0 PF | | | –200 maa<br>2 3 4 5 6 2 3 4 5 6 0 400 800 1200 1600 2000 2400 2800<br>SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) TIME (h)<br>699512 G17 699512 G18<br>699512 G16<br>Rev. B<br>POWER SUPPLY CURRENT (µA) POWER SUPPLY CURRENT (µA) POWER SUPPLY CURRENT (µA)<br> (µA)<br>ISET<br>RST PIN VOLTAGE (V)<br>POWER SUPPLY CURRENT (µA)<br>RISE/FALL TIME (ns)<br>PROPAGATION DELAY (ns) DELTA FREQUENCY (ppm)<br>**----- End of picture text -----**<br>


6 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**V[+] = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.** 

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Output Resistance<br>vs Supply Current<br>50<br>45<br>40 SEe5<br>35 A<br>OUTPUT SOURCING CURRENT<br>30<br>25<br>20<br>15 OUTPUT SINKING CURRENT<br>1050 FEeea<br>2 3 4 5 6<br>SUPPLY VOLTAGE (V)<br>699512 G19<br>OUTPUT RESISTANCE (Ω)<br>**----- End of picture text -----**<br>


**==> picture [223 x 137] intentionally omitted <==**

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Typical LTC6995-1 Start-Up with<br>POL = 1<br>V [+]<br>5V/DIV SE<br>ME<br>RST<br>5V/DIV<br>RESET RELEASED,<br>OUT 100Hz OUTPUT CLOCK<br>OUTPUT RESET<br>5V/DIV<br>4ms START-UP<br>V [+]  = 5V 5ms/DIV 699512 G20<br>DIVCODE = 15<br>RSET = 499k<br>**----- End of picture text -----**<br>


## **PIN FUNCTIONS** 

## **(DCB/S6)** 

**V[+] (Pin 1/Pin 5):** Supply Voltage (2.25V to 5.5V). This supply should be kept free from noise and ripple. It should be bypassed directly to the GND pin with a 0.1µF capacitor. 

**DIV (Pin 2/Pin 4):** Programmable Divider and Polarity Input. An internal A/D converter (referenced to V[+] ) monitors the DIV pin voltage (VDIV) to determine a 4-bit result (DIVCODE). VDIV may be generated by a resistor divider between V[+] and GND. Use 1% resistors to ensure an accurate result. The DIV pin and resistors should be shielded from the OUT pin or any other traces that have fast edges. Limit the capacitance on the DIV pin to less than 100pF so that VDIV settles quickly. The MSB of DIVCODE (POL) determines the polarity of the OUT pin. 

**SET (Pin 3/Pin 3):** Frequency-Setting Input. The voltage on the SET pin (VSET) is regulated to 1V above GND. The amount of current sourced from the SET pin (ISET) programs the master oscillator frequency. The ISET current range is 1.25µA to 20µA. The output oscillation will stop if ISET drops below approximately 500nA. A resistor connected between SET and GND is the most accurate way to set the frequency. For best performance, use a precision metal or thin film resistor of 0.5% or better tolerance and 

50ppm/°C or better temperature coefficient. For lower accuracy applications an inexpensive 1% thick film resistor may be used. 

Limit the capacitance on the SET pin to less than 10pF to minimize jitter and ensure stability. Capacitance less than 100pF maintains the stability of the feedback circuit regulating the VSET voltage. 

**==> picture [117 x 79] intentionally omitted <==**

**----- Start of picture text -----**<br>
RST OUT<br>LTC6995-1/<br>V [+]<br>LTC6995-2<br>GND V [+]<br>C1<br>0.1µF R1<br>SET DIV<br>RSET 699512 PF R2<br>**----- End of picture text -----**<br>


**RST or RST (Pin 4/Pin 1):** Output Reset. The reset input is used to stop the output oscillator and to clear internal dividers. When reset is released the oscillator starts with a full half period time interval. The output logic state when reset is determined by the programmed DIVCODE. The LTC6995-1 has an active high RST input. The LTC6995-2 has an active low RST input. 

Rev. B 

7 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **PIN FUNCTIONS (DCB/S6)** 

**GND (Pin 5/Pin 2):** Ground. Tie to a low inductance ground plane for best performance. 

**OUT (Pin 6/Pin 6):** Oscillator Output. The OUT pin swings from GND to V[+] with an output resistance of approximately 

30Ω. When driving an LED or other low impedance load a series output resistor should be used to limit source/ sink current to 20mA. 

## **BLOCK DIAGRAM (S6 Package Pin Numbers Shown)** 

**==> picture [411 x 302] intentionally omitted <==**

**----- Start of picture text -----**<br>
5<br>V [+]<br>R1 POL BIT<br>DIV 4-BIT A/D DIGITAL<br>4<br>CONVERTER FILTER<br>R2<br>MASTER OSCILLATOR<br>tMASTER = 50kΩ [1][µ][s] • VISETSET MCLK DIVIDERFIXED PROGRAMMABLEDIVIDER POLARITYOUTPUT OUT 6<br>÷ 1024 ÷1, 8, 64, 512 tOUT<br>4096, 2 [15] , 2 [18] , 2 [21]<br>HALT OSCILLATOR DIVIDER<br>OUTPUT RESET<br>IF ISET < 500nA<br>ISET<br>POR<br>LTC6995-2<br>ONLY<br>VSET = 1V +– 1V<br>SET GND RST<br>3 2 1<br>699512 BD<br>ISET<br>RSET<br>+<br>–<br>**----- End of picture text -----**<br>


Rev. B 

8 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **OPERATION** 

The LTC6995 is built around a master oscillator with a 1MHz maximum frequency. The oscillator is controlled by the SET pin current (ISET) and voltage (VSET), with a 1MHz • 50k conversion factor that is accurate to ±0.8% under typical conditions. 

**==> picture [187 x 30] intentionally omitted <==**

A feedback loop maintains VSET at 1V ±30mV, leaving ISET as the primary means of controlling the output frequency. The simplest way to generate ISET is to connect a resistor (RSET) between SET and GND, such that ISET = VSET/RSET . The master oscillator equation reduces to: 

**==> picture [157 x 29] intentionally omitted <==**

From this equation, it is clear that VSET drift will not affect the output frequency when using a single program resistor (RSET). Error sources are limited to RSET tolerance and the inherent frequency accuracy ∆fOUT of the LTC6995. 

RSET may range from 50k to 800k (equivalent to ISET between 1.25µA and 20µA). 

Before reaching the OUT pin, the oscillator frequency passes through a fixed ÷1024 divider. The LTC6995 also includes a programmable frequency divider which can further divide the frequency by 1, 8, 64, 512, 4096, 2[15] , 2[18] or 2[21] . The divider ratio NDIV is set by a resistor divider attached to the DIV pin. 

**==> picture [172 x 71] intentionally omitted <==**

with RSET in place of VSET/ISET the equation reduces to: 

**==> picture [134 x 26] intentionally omitted <==**

## **DIVCODE** 

The DIV pin connects to an internal, V[+] referenced 4-bit A/D converter that determines the DIVCODE value. DIVCODE programs two settings on the LTC6995: 

1. DIVCODE determines the output frequency divider setting, NDIV . 

2. DIVCODE determines the polarity of the RST and OUT pins, via the POL bit. 

VDIV may be generated by a resistor divider between V[+] and GND as shown in Figure 1. 

**==> picture [93 x 94] intentionally omitted <==**

**----- Start of picture text -----**<br>
2.25V TO 5.5V<br>V [+]<br>LTC6995 R1<br>DIV<br>R2<br>GND<br>699512 F01<br>**----- End of picture text -----**<br>


**Figure 1. Simple Technique for Setting DIVCODE** 

Table 1 offers recommended 1% resistor values that accurately produce the correct voltage division as well as the corresponding NDIV and POL values for the recommended resistor pairs. Other values may be used as long as: 

1. The VDIV/V[+] ratio is accurate to ±1.5% (including resistor tolerances and temperature effects) 

2. The driving impedance (R1||R2) does not exceed 500kΩ. 

If the voltage is generated by other means (i.e., the output of a DAC) it must track the V[+] supply voltage. The last column in Table 1 shows the ideal ratio of VDIV to the supply voltage, which can also be calculated as: 

**==> picture [137 x 28] intentionally omitted <==**

For example, if the supply is 3.3V and the desired DIVCODE is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV. 

Figure 2 illustrates the information in Table 1, showing that NDIV is symmetric around the DIVCODE midpoint. 

Rev. B 

9 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **OPERATION** 

**Table 1. DIVCODE Programming** 

|**DIVCODE**|**POL**|**NDIV**|**RECOMMENDED tOUT**|**R1 (kΩ)**|**R2 (kΩ)**|**VDIV/V+**|
|---|---|---|---|---|---|---|
|0|0|1|1.024ms to 16.384ms|Open|Short|≤0.03125 ±0.015|
|1|0|8|8.192ms to 131ms|976|102|0.09375 ±0.015|
|2|0|64|65.5ms to 1.05sec|976|182|0.15625 ±0.015|
|3|0|512|524ms to 8.39sec|1000|280|0.21875 ±0.015|
|4|0|4,096|4.19sec to 67.1sec|1000|392|0.28125 ±0.015|
|5|0|32,768|33.6sec to 537sec|1000|523|0.34375 ±0.015|
|6|0|262,144|268sec to 4,295sec|1000|681|0.40625 ±0.015|
|7|0|2,097,152|2,147sec to 34,360sec|1000|887|0.46875 ±0.015|
|8|1|2,097,152|2,147sec to 34,360sec|887|1000|0.53125 ±0.015|
|9|1|262,144|268sec to 4,295sec|681|1000|0.59375 ±0.015|
|10|1|32,768|33.6sec to 537sec|523|1000|0.65625 ±0.015|
|11|1|4,096|4.19sec to 67.1sec|392|1000|0.71875 ±0.015|
|12|1|512|524ms to 8.39sec|280|1000|0.78125 ±0.015|
|13|1|64|65.5ms to 1.05sec|182|976|0.84375 ±0.015|
|14|1|8|8.192ms to 131ms|102|976|0.90625 ±0.015|
|15|1|1|1.024ms to 16.384ms|Short|Open|≥0.96875 ±0.015|



**==> picture [303 x 180] intentionally omitted <==**

**----- Start of picture text -----**<br>
POL BIT = 0 POL BIT = 1<br>10000 7 8<br>1000 6 9<br>100 5 10<br>4 11<br>10<br>3 12<br>1<br>2 13<br>0.1<br>1 14<br>0.01<br>0 15<br>0.001<br>0V 0.5•V [+] V [+]<br>INCREASING VDIV<br>699512 F02<br> (SECONDS)<br>tOUT<br>**----- End of picture text -----**<br>


**Figure 2. Frequency Range and POL Bit vs DIVCODE** 

Rev. B 

10 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **OPERATION** 

## **Reset and Polarity Bit Functions** 

The Reset input, RST for the LTC6995-1 and RST for the LTC6995-2, forces the output to a fixed state and resets the internal clock dividers. The output state when reset is determined by the polarity bit as selected by through the DIVCODE setting. 

|||**OUTPUT(OSCILLATOR START STATE)**|**OUTPUT(OSCILLATOR START STATE)**|
|---|---|---|---|
|**RST/RST**|**POLARITY**|**LTC6995-1**|**LTC6995-2**|
|0|0|Oscillating (Low)|0(Reset)|
|1|0|0(Reset)|Oscillating (Low)|
|0|1|Oscillating (High)|1(Reset)|
|1|1|1(Reset)|Oscillating (High)|



With the POL bit programmed to be 0, the output will be forced low when reset. When reset is released by changing state, the oscillator starts. The next rising edge at the output follows a precise half cycle delay. 

With the POL bit programmed to be 1, the output will be forced high when reset. When reset is released by changing state, the oscillator starts. The next falling edge at the output follows a precise half cycle delay. 

**==> picture [511 x 257] intentionally omitted <==**

**----- Start of picture text -----**<br>
tWIDTH tWIDTH<br>RST RST<br>tRST tRST<br>OUT REMAINS LOW OUT REMAINS LOW<br>OUT WHILE RST IS HIGH OUT WHILE RST IS LOW<br>699512 F03<br>tOUT tOUT<br>1/2 tOUT 1/2 tOUT<br>LTC6995-1 LTC6995-2<br>Figure 3. Reset Timing Diagram (POL Bit = 0)<br>tWIDTH tWIDTH<br>RST RST<br>tRST tRST<br>OUT REMAINS HIGH<br>OUT OUT REMAINS HIGH OUT WHILE RST IS LOW<br>WHILE RST IS HIGH<br>699512 F04<br>tOUT tOUT<br>1/2 tOUT 1/2 tOUT<br>LTC6995-1 LTC6995-2<br>**----- End of picture text -----**<br>


**Figure 4. Reset Timing Diagram (POL Bit = 1)** 

Rev. B 

11 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **OPERATION** 

## **Changing DIVCODE After Start-Up** 

Following start-up, the A/D converter will continue monitoring VDIV for changes. The LTC6995 will respond to DIVCODE changes in less than one cycle. 

## tDIVCODE < 500 • tMASTER < tOUT 

The output may have an inaccurate pulse width during the frequency transition. But the transition will be glitch-free and no high or low pulse can be shorter than the master clock period. A digital filter is used to guarantee the DIVCODE has settled to a new value before making changes to the output. 

## **Start-Up Time** 

When power is first applied, the power-on reset (POR) circuit will initiate the start-up time, tSTART . A supply voltage of typically 1.4V (1.2V to 1.5V over temperature) initiates the start-up sequence. The OUT pin is held low during this time. The typical value for tSTART ranges from 0.5ms to 8ms depending on the master oscillator frequency (independent of NDIV): 

## tSTART(TYP) = 500 • tMASTER 

During start-up, the DIV pin A/D converter must determine the correct DIVCODE before the output is enabled. The start-up time may increase if the supply or DIV pin 

voltages are not stable. For this reason, it is recommended to minimize the capacitance on the DIV pin so it will properly track V[+] . Less than 100pF will not affect performance. 

## **Start-Up Behavior** 

When first powered up, the output is held low. If the polarity is set for non-inversion (POL = 0) and the output is enabled at the end of the start-up time, OUT will begin oscillating. If the output is being reset (RST = 1 for LTC6995-1 and RST = 0 for LTC6995-2) at the end of the start-up time, it will remain low due to the POL bit = 0. When reset is released the oscillator starts and the output remains low for precisely one half cycle of the programmed period. 

In inverted operation (POL = 1), the start-up sequence is similar. However, the LTC6995 does not know the correct DIVCODE setting when first powered up, so the output defaults low. At the end of tSTART , the value of DIVCODE is recognized and OUT goes high (inactive) because POL = 1. If the output is being reset (RST = 1 for LTC6995-1 and RST = 0 for LTC6995-2) at the end of the start-up time, it will remain high due to the POL bit = 1. When reset is released the oscillator starts and the output remains high for precisely one half cycle of the programmed period. Figure 7 to Figure 10 detail the possible start-up sequences. 

**==> picture [455 x 98] intentionally omitted <==**

**----- Start of picture text -----**<br>
200mV/DIVDIV ----- | ---------------+----f----’i2 ---------4----------i | V [+] ----f --------------+----1----+---------4-----' Bs ’ | -----<br>J\Iii=:|! | 1V/DIV j-——-f-} |i = ! |<br>|___ So Bol Rae al na Py<br>1V/DIVOUT Jj|i|  2ii\ i}i i|| L|i\ 4 OUT — <a 500µs < ' ee a a !j| es|i|<br>pooi| +! 1i LE | i| 1V/DIV eei| +! ee re esos oe+! i|<br>a\| ii a :1 tht Sed atthe|i | I ii a : Jpii \|<br>|I Hi 2 Hi || |I Hi 2 Hi ||<br>V [+]  = 3.3V 10ms/DIV 699512  V [+]  = 2.5V 250µs/DIV 699512 F06<br>RSET = 200k F05 DIVCODE = 15<br>RSET = 50k<br>**----- End of picture text -----**<br>


**Figure 5. DIVCODE Change from 1 to 0** 

**Figure 6. Typical Start-Up LTC6995-1 with RST = 0V** 

Rev. B 

12 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **OPERATION** 

**==> picture [465 x 87] intentionally omitted <==**

**----- Start of picture text -----**<br>
RST RST<br>OUT OUT<br>tSTART tOUT tSTART tOUT<br>1/2 tOUT 1/2 tOUT<br>LTC6995-1 LTC6995-2 699512 F07<br>**----- End of picture text -----**<br>


**Figure 7. Start-Up Timing Diagram (Reset = 0, POL Bit = 0)** 

**==> picture [459 x 87] intentionally omitted <==**

**----- Start of picture text -----**<br>
RST RST<br>OUT OUT<br>tSTART tOUT tSTART tOUT<br>1/2 tOUT 1/2 tOUT<br>LTC6995-1 LTC6995-2 699512 F08<br>**----- End of picture text -----**<br>


**Figure 8. Start-Up Timing Diagram (Reset = 1, POL Bit = 0)** 

**==> picture [465 x 86] intentionally omitted <==**

**----- Start of picture text -----**<br>
RST RST<br>OUT OUT<br>tSTART tOUT tSTART tOUT<br>1/2 tOUT 1/2 tOUT<br>LTC6995-1 LTC6995-2 699512 F09<br>**----- End of picture text -----**<br>


**Figure 9. Start-Up Timing Diagram (Reset = 0, POL Bit = 1)** 

**==> picture [461 x 87] intentionally omitted <==**

**----- Start of picture text -----**<br>
RST RST<br>OUT OUT<br>tSTART tOUT tSTART tOUT<br>1/2 tOUT 1/2 tOUT<br>LTC6995-1 LTC6995-2 699512 F10<br>**----- End of picture text -----**<br>


**Figure 10. Start-Up Timing Diagram (Reset = 1, POL Bit = 1)** 

Rev. B 

13 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **APPLICATIONS INFORMATION** 

## **Basic Operation** 

The simplest and most accurate method to program the LTC6995 is to use a single resistor, RSET , between the SET and GND pins. The design procedure is a 3-step process. First select the POL bit setting and NDIV value, then calculate the value for the RSET resistor. 

_Example:_ Design a 1Hz oscillator with minimum power consumption, an active-high reset input, and the OUT pin low during reset. 

## **Step 1: Select the LTC6995 Version and POL Bit Setting** 

For active-high reset select the LTC6995-1. For OUT low during reset choose POL bit = 0. 

## **Step 1: Select the LTC6995 Version and POL Bit Setting** 

Determine if the application requires an active-high, LTC6995-1 or active-low, LTC6995-2 reset function. Otherwise the two versions share identical functionality. 

The OUT pin polarity depends on the setting of the POL bit. To force OUT = 0 during reset, choose POL bit = 0. To force OUT = 1 during reset, choose POL bit = 1. 

## **Step 2: Select the NDIV Frequency Divider Value** 

As explained earlier, the voltage on the DIV pin sets the DIVCODE which determines both the POL bit and the NDIV value. For a given output clock period, NDIV should be selected to be within the following range. 

**==> picture [239 x 26] intentionally omitted <==**

To minimize supply current, choose the lowest NDIV value (generally recommended). Alternatively, use Table 1 as a guide to select the best NDIV value for the given application. 

With POL already chosen, this completes the selection of DIVCODE. Use Table 1 to select the proper resistor divider or VDIV/V[+] ratio to apply to the DIV pin. 

## **Step 3: Calculate and Select RSET** 

The final step is to calculate the correct value for RSET using the following equation. 

**==> picture [240 x 29] intentionally omitted <==**

Select the standard resistor value closest to the calculated value. 

## **Step 2: Select the NDIV Frequency Divider Value** 

Choose an NDIV value that meets the requirements of Equation (1), using tOUT = 1000ms: 

61.04 ≤ NDIV ≤ 976.6 

Potential settings for NDIV include 64 and 512. NDIV = 64 is the best choice, as it minimizes supply current by using a large RSET resistor. POL = 0 and NDIV = 64 requires DIVCODE = 2. Using Table 1, choose R1 = 976k and R2 = 182k values to program DIVCODE = 2. 

## **Step 3: Select RSET** 

Calculate the correct value for RSET using Equation (2). 

**==> picture [157 x 26] intentionally omitted <==**

Since 763k is not available as a standard 1% resistor, substitute 768k if a –0.7% frequency shift is acceptable. Otherwise, select a parallel or series pair of resistors such as 576k + 187k to attain a more precise resistance. 

The completed design is shown in Figure 11. 

**==> picture [159 x 103] intentionally omitted <==**

**----- Start of picture text -----**<br>
RST RST OUT<br>LTC6995-1 2.25V TO 5.5V<br>GND V [+]<br>R1<br>976k<br>SET DIV DIVCODE = 2<br>RSET R2<br>763k 182k<br>699512 F11<br>**----- End of picture text -----**<br>


**Figure 11. 1Hz Oscillator** 

Rev. B 

14 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **APPLICATIONS INFORMATION** 

## **Power-On Reset (POR) Function** 

When power is applied to the LTC6995 the output is held low for tSTART, then takes on the value of the POL bit as the clock cycle begins. If POL = 0 (DIVCODE < 8) the output will remain low for a programmable interval of tSTART + 1/2 tOUT, assuming the RST pin is inactive. This makes the LTC6995 useful as a programmable long-time power-on reset (POR), with the low output used to hold a system in reset for a fixed period after power is applied. Timing begins when the V[+] supply exceeds approximately 1.4V. 

To prevent additional output transitions after the initial POR time, the oscillator can be disabled by removing the SET pin current. This prevents the internal master oscillator output from clocking the frequency dividers or output, while keeping it biased so it can resume operation quickly. The easiest way to implement this feature is to connect RSET between the SET and OUT pins. 

Figure 12 shows the basic power-on reset function. When the half cycle times out, the output goes high, eliminates the SET pin current, and stops additional OUT pin transitions. The output remains high until the device is reset by driving the RST input or power is cycled off then back on. 

**==> picture [250 x 218] intentionally omitted <==**

**----- Start of picture text -----**<br>
RST OUT POR<br>LTC6995-1<br>GND V [+] 2.25V TO 5.5V<br>RSET R1 0.1µF<br>191k 1M<br>SET DIV<br>R2<br>RST = V [+]  FOR LTC6995-2 280k<br>tPOR = 1 SECOND FOR VALUES SHOWN<br>POL = 0<br>DIVCODE = 3<br>NDIV = 512<br>V [+] tSTART<br>~1.4V STARTS TIMER<br>OUT tDELAY<br>POL = 0 (1/2 tOUT) TIMER STOPPED<br>POWER-ON RESET 699512 F12<br>**----- End of picture text -----**<br>


**Figure 12. Active Low Power-On Reset (1 Second Interval Example)** 

The POR interval is only one half of an oscillator period so component selection is slightly different. Table 2 provides the component values required for one half cycle time intervals. Timing starts after a short startup delay time following the application of the V[+] supply. 

**Table 2. Power-On Reset (POR). One Shot, One Half Cycle Delay Programming** 

|**Table 2. Power-On Reset(POR). One Shot, One Half Cycle Delay Programming**|**Table 2. Power-On Reset(POR). One Shot, One Half Cycle Delay Programming**|**Table 2. Power-On Reset(POR). One Shot, One Half Cycle Delay Programming**|**Table 2. Power-On Reset(POR). One Shot, One Half Cycle Delay Programming**|**Table 2. Power-On Reset(POR). One Shot, One Half Cycle Delay Programming**|
|---|---|---|---|---|
|**Output Low During Time Interval, POL = 0**|||||
|**DIVCODE**|**tDELAY TIME INTERVAL (1/2 tOUT)**|**R1 (kΩ)**|**R2 (kΩ)**|**~RSET (kΩ)**|
|0|512µs to 8.2ms|Open|Short|tDELAY(MS)• 97.6|
|1|4.1ms to 65.5ms|976|102|tDELAY(MS)• 12.2|
|2|32.8ms to 524.3ms|976|182|tDELAY(MS)• 1.5|
|3|262.1ms to 4.2sec|1000|280|tDELAY(SEC)• 190.7|
|4|2.1sec to 33.6sec|1000|392|tDELAY(SEC)• 23.8|
|5|16.8sec to 4.5min|1000|523|tDELAY(MIN)• 178.6|
|6|2.2min to 35.8min|1000|681|tDELAY(MIN)• 22.7|
|7|17.9min to 4.8hrs|1000|887|tDELAY(HR)• 167.6|



Note: Power-On Reset Time = tDELAY + tSTART 

Rev. B 

15 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **APPLICATIONS INFORMATION** 

For shorter power-on reset times (1ms to 73ms) the timer startup delay becomes a significant part of the total POR time. To take this delay into account the value for RSET can be modified from the values shown in Table 2. For a POR time in the range from 1ms to 16ms (DIVCODE = 0), RSET should be tPOR(ms) • 49.5. For a POR time in the range from 4.5ms to 73ms (DIVCODE = 1), RSET is tPOR(ms) • 10.9. For longer POR times (DIVCODE 2 through 7) the startup time is insignificant. After power on, the delay following a reset condition will be in the same range as shown for tDELAY in Table 2 for these two DIVCODE selections. 

For short POR times, a more precise estimation of the startup time can be found from the following: 

**==> picture [237 x 25] intentionally omitted <==**

Supply bounce resets the internal timer so the POR circuit automatically debounces supply noise. POR timing starts from the time that the V[+] supply has reached approximately 1.4 volts. 

## **Long Timer One Shots and Delay Generators** 

The POR circuit of Figure 12 is also useful when the reset inputs are driven. This creates edge triggered timing events that are active low and can either be re-triggered or can stop after one programmed interval. The programmed time interval can range from only 500µs to over 4 hours with just resistor value changes. 

The circuits in Figure 13 show how a POR or active low interval can be re-started to provide a full system reset time. 

The Figure 14 circuit requires an indication from the system being reset that it is ready before timing out. The LTC6995-2 can accommodate an active high OK signal. 

By forcing a reset condition at power on the LTC6995 can be used to create a long time delayed rising edge triggered by either a falling edge signal (LTC6995-1) or a rising edge signal (LTC6995-2) as show in Figure 15. 

**==> picture [492 x 285] intentionally omitted <==**

**----- Start of picture text -----**<br>
V [+] V [+]<br>100k<br>RST OUT POR RST OUT POR<br>100k LTC6995-1 LTC6995-2<br>GND V [+] V [+] GND V [+] V [+]<br>R1 0.1µF R1 0.1µF<br>RSET RSET<br>SET DIV SET DIV<br>R2 R2<br>ACTIVE HIGH RESET ACTIVE LOW RESET<br>V [+]<br>V [+] RESET<br>RESET<br>RST RST<br>OUT tSTART + TIMER OUT tSTART + TIMER<br>POL = 0 1/2 tOUT 1/2 tOUT STOPPED POL = 0 1/2 tOUT 1/2 tOUT STOPPED<br>POR TIMER POR POR TIMER POR<br>STOPPED STOPPED 699512 F13<br>**----- End of picture text -----**<br>


**Figure 13. System Resets On Command with Full POR Time Interval. Reset Pulse Is Debounced Automatically** 

Rev. B 

16 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **APPLICATIONS INFORMATION** 

**==> picture [427 x 120] intentionally omitted <==**

**----- Start of picture text -----**<br>
SYSTEM OK<br>V [+]<br>POR<br>RST OUT SYSTEM<br>LTC6995-1 RST<br>SYSTEM OK<br>GND V [+] V [+]<br>R1 0.1µF<br>RSET OUT tSTART + TIMER<br>SET DIV POL = 0 1/2 tOUT 1/2 tOUT STOPPED<br>R2<br>POR POR EXTENDED POR<br>699512 F14<br>**----- End of picture text -----**<br>


**Figure 14. Extended POR. Timer Reset During Initial POR Interval. Full POR Interval Provided Once System Signals the OK** 

**==> picture [490 x 216] intentionally omitted <==**

**----- Start of picture text -----**<br>
TRIGGER RST OUT OUTPUT TRIGGER RST OUT OUTPUT<br>LTC6995-1 LTC6995-2<br>GND V [+] V [+] GND V [+] V [+]<br>R1 0.1µF R1 0.1µF<br>RSET RSET<br>SET DIV SET DIV<br>FALLING EDGE TRIGGERED R2 RISING EDGE TRIGGERED R2<br>POL = 0 POL = 0<br>V [+] V [+]<br>TRIGGER TRIGGER<br>OUTPUT OUTPUT<br>1/2 tOUT 1/2 tOUT 1/2 tOUT 1/2 tOUT<br>699512 F15<br>**----- End of picture text -----**<br>


**Figure 15. Long Time Delayed Rising Edge. Delay Time Can Range from 500µs to 4.8 Hours** 

Rev. B 

17 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **APPLICATIONS INFORMATION** 

## **Watchdog Timers** 

Using the same circuits as shown in Figure 15 with periodic pulsing of the reset input can create an effective watchdog timer. A watchdog pulse is required from a system within each timing interval. The watchdog timeout interval can be programmed from 500µs to 4.8 hours. If a pulse is missed the output goes high to indicate that the system software may be caught in an infinite loop. This high level can be used to initiate software diagnostic or restart procedures. The LTC6995 internal clock stops and the output remains high until the software recovers and 

returns to issuing watchdog pulses. Figure 16 shows the timing for this application. 

Watchdog timers are used to detect if a system operating software is diverted from the designed program sequence for any reason. It is always a possibility that the software could get stuck in a way that keeps the watchdog pulse in the state that holds the timer in the reset so it can never time out. In this condition the watchdog timer is ineffective and will never force corrective action. To help to prevent this a second one shot can be used to reset the watchdog timer as shown in Figure 17. 

**==> picture [350 x 152] intentionally omitted <==**

**----- Start of picture text -----**<br>
V [+]<br>MISSED PULSE<br>RST (LTC6995-1)<br>WATCHDOG PULSES<br>RST (LTC6995-2)<br>OUTPUT<br>SERVICE WATCHDOG<br>TIMER RESTARTS TIMEOUT RESUME<br>699512 F16<br>**----- End of picture text -----**<br>


**Figure 16. Watchdog Timer. Same Circuits as Shown in Figure 15** 

**==> picture [328 x 147] intentionally omitted <==**

**----- Start of picture text -----**<br>
100µs ONE SHOT 50ms WATCHDOG TIMER<br>SYSTEM POSITIVE<br>TRG OUT RST OUT OUTPUT<br>WATCHDOG PULSE<br>LTC6993-1 LTC6995-1<br>GND V [+] V [+] GND V [+] V [+]<br>RSET R1 0.1µF<br>604k 976k<br>SET DIV SET DIV<br>RSET R2<br>619k<br>102k<br>RISING EDGE TRIGGERED FALLING EDGE TRIGGERED<br>POSITIVE OUTPUT PULSE POL = 0<br>DIVCODE = 1 DIVCODE = 1 699512 F17<br>**----- End of picture text -----**<br>


**Figure 17. Extra-Reliable Watchdog Timer. Allows Timeout if System Watchdog Pulse Gets Stuck in the Timer Reset State. Both Timer Devices Can Share the Same DIVCODE Setting** 

Rev. B 

18 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **APPLICATIONS INFORMATION** 

## **Gated Oscillators** 

The reset input (RST) clears all internal dividers so that, when released, the output will start clocking with a full programmed period. This edge can be used to gate the output ON and OFF at a known starting point for the clock. Circuits which count clock cycles for further timing purposes will always have an accurate count of full cycles until reset. The output clock is always at 50% duty cycle and the period of each cycle can range from 1ms to 9.5 hours. Depending on the polarity bit selection the output clock can start high or low as shown in Figure 18. 

## **Self-Resetting Circuits** 

The RST pin has hysteresis to accommodate slow-changing input voltages. Furthermore, the trip points are proportional to the supply voltage (see Note 6 and the RST Threshold Voltage vs Supply Voltage curve in Typical Performance Characteristics). This allows an RC time constant at the RST input to generate a delay that is nearly independent of the supply voltage. 

A simple application of this technique allows the LTC6995 output to reset itself, producing a well-controlled pulse once each cycle. Figure 19a and Figure 19b show circuits that produce approximately 1µs pulses once a minute. The only difference is the version of LTC6995 used and the POL bit setting, which controls whether the pulse is positive or negative. 

## **Voltage Controlled Frequency** 

With one additional resistor, the LTC6995 output frequency can be manipulated by an external voltage. As shown in Figure 20, voltage VCTRL sources/sinks a current through RVCO to vary the ISET current, which in turn modulates the output frequency as described in Equation (3). 

**==> picture [241 x 34] intentionally omitted <==**

**==> picture [475 x 112] intentionally omitted <==**

**----- Start of picture text -----**<br>
LTC6995-1 LTC6995-2<br>ACTIVE HIGH RESET ACTIVE LOW RESET<br>RST FALLING EDGE STARTS THE CLOCK RST RISING EDGE STARTS THE CLOCK<br>RST RST<br>OUT OUT<br>POL = 0 1/2 tOUT POL = 0 1/2 tOUT<br>OUT 1/2 tOUT OUT 1/2 tOUT<br>POL = 1 POL = 1<br>699512 F18<br>**----- End of picture text -----**<br>


**Figure 18. Gated Oscillators. First One-Half Cycle Time Always Accurate** 

Rev. B 

19 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **APPLICATIONS INFORMATION** 

**==> picture [156 x 482] intentionally omitted <==**

**----- Start of picture text -----**<br>
OUT<br>RPW<br>2.26k<br>RST OUT<br>CPW LTC6995-1<br>470pF 2.25V TO 5.5V<br>GND V [+]<br>RSET R1 0.1µF<br>178k 1M<br>SET DIV<br>R2<br>523k<br>tPULSE = –RPW • CPW • In(1– VRST(VRISING [+] ))<br>tPULSE ≈ –2.26kΩ • 470pF • In(1 – 0.61)<br>tPULSE ≈ 1µs<br>1µs PULSE WIDTH<br>60 SECONDS<br>699512 F19a<br>(a) Self-Resetting Circuit (DIVCODE = 5)<br>OUT<br>RPW<br>2.26k<br>RST OUT<br>CPW LTC6995-2<br>470pF 2.25V TO 5.5V<br>GND V [+]<br>RSET R1 0.1µF<br>178k 523k<br>SET DIV<br>R2<br>1M<br>tPULSE = –RPW • CPW • In( VRST(VFALLING [+] ))<br>tPULSE ≈ –2.26kΩ • 470pF • In(0.43)<br>tPULSE ≈ 0.9µs<br>0.9µs PULSE WIDTH<br>60 SECONDS<br>699512 F19b<br>**----- End of picture text -----**<br>


- (a) Self-Resetting Circuit (DIVCODE = 5) 

(b) Self-Resetting Circuit (DIVCODE = 10) 

**==> picture [179 x 101] intentionally omitted <==**

**----- Start of picture text -----**<br>
RST OUT<br>LTC6995-1 V [+]<br>GND V [+]<br>C1<br>0.1µF R1<br>RVCO<br>VCTRL SET DIV<br>RSET R2<br>699512 F20<br>**----- End of picture text -----**<br>


**Figure 20. Voltage-Controlled Oscillator** 

## **Digital Frequency Control** 

The control voltage can be generated by a DAC (digitalto-analog converter), resulting in a digitally-controlled frequency. Many DACs allow for the use of an external reference. If such a DAC is used to provide the VCTRL voltage, the VSET dependency can be eliminated by buffering VSET and using it as the DAC’s reference voltage, as shown in Figure 21. The DAC’s output voltage now tracks any VSET variation and eliminates it as an error source. The SET pin cannot be tied directly to the reference input of the DAC because the current drawn by the DAC’s REF input would affect the frequency. 

## **ISET Extremes (Master Oscillator Frequency Extremes)** 

When operating with ISET outside of the recommended 1.25µA to 20µA range, the master oscillator operates outside of the 62.5kHz to 1MHz range in which it is most accurate. 

The oscillator can still function with reduced accuracy for ISET < 1.25µA. At approximately 500nA, the oscillator output will be frozen in its current state. The output could halt in a high or low state. This avoids introducing short pulses when frequency modulating a very low frequency output. 

At the other extreme, it is not recommended to operate the master oscillator beyond 2MHz because the accuracy of the DIV pin ADC will suffer. 

**Figure 19.** 

Rev. B 

20 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **APPLICATIONS INFORMATION** 

**==> picture [329 x 199] intentionally omitted <==**

**----- Start of picture text -----**<br>
RST OUT<br>LTC6995-1 V [+]<br>V [+] GND V [+]<br>0.1µF C1<br>0.1µF R1<br>SET DIV<br>1/2<br>LTC6078 R2<br>V [+]<br>0.1µF<br>VCC REF fOUT = 1024 • N1MHz DIV• 50kΩ • RVCO • (1 + RRVCOSET – 4096DIN )<br>DIN RVCO DIN = 0 TO 4095<br>µP CLK LTC1659 VOUT<br>CS/LD RSET<br>GND<br>699512 F21<br>+<br>–<br>**----- End of picture text -----**<br>


**Figure 21. Digitally-Controlled Oscillator** 

## **Frequency Modulation and Settling Time** 

The LTC6995 will respond to changes in ISET up to a –3dB bandwidth of 0.4 • fOUT . 

Following a 2× or 0.5× step change in ISET , the output frequency takes less than one cycle to settle to within 1% of the final value. 

## **Power Supply Current** 

The power supply current varies with frequency, supply voltage and output loading. It can be estimated under any condition using the following equation. This equation ignores CLOAD (valid for CLOAD < 1nF) and assumes the output has 50% duty cycle. 

**==> picture [230 x 56] intentionally omitted <==**

## **Supply Bypassing and PCB Layout Guidelines** 

The LTC6995 is a 2.2% accurate silicon oscillator when used in the appropriate manner. The part is simple to use 

and by following a few rules, the expected performance is easily achieved. Adequate supply bypassing and proper PCB layout are important to ensure this. 

Figure 21 shows example PCB layouts for both the TSOT-23 and DFN packages using 0603 sized passive components. The layouts assume a two layer board with a ground plane layer beneath and around the LTC6995. These layouts are a guide and need not be followed exactly. 

1. Connect the bypass capacitor, C1, directly to the V[+] and GND pins using a low inductance path. The connection from C1 to the V[+] pin is easily done directly on the top layer. For the DFN package, C1’s connection to GND is also simply done on the top layer. For the TSOT-23, OUT can be routed through the C1 pads to allow a good C1 GND connection. If the PCB design rules do not allow that, C1’s GND connection can be accomplished through multiple vias to the ground plane. Multiple vias for both the GND pin connection to the ground plane and the C1 connection to the ground plane are recommended to minimize the inductance. Capacitor C1 should be a 0.1µF ceramic capacitor. 

Rev. B 

21 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **APPLICATIONS INFORMATION** 

**==> picture [335 x 241] intentionally omitted <==**

**----- Start of picture text -----**<br>
RST OUT<br>LTC6995-1<br>GND V [+] V [+]<br>C1<br>0.1µF R1<br>SET DIV<br>RSET R2<br>V [+]<br>C1 V [+]<br>R1 C1<br>V [+] OUT RST OUT<br>DIV GND GND V [+]<br>R2 SET RST SET DIV<br>R1<br>RSET RSET R2<br>699512 F22<br>DFN PACKAGE TSOT-23 PACKAGE<br>**----- End of picture text -----**<br>


**Figure 22. Supply Bypassing and PCB Layout** 

2.  Place all passive components on the top side of the board. This minimizes trace inductance. 

3.  Place RSET as close as possible to the SET pin and make a direct, short connection. The SET pin is a current summing node and currents injected into this pin directly modulate the operating frequency. Having a short connection minimizes the exposure to signal pickup. 

4.  Connect RSET directly to the GND pin. Using a long path or vias to the ground plane will not have a significant affect on accuracy, but a direct, short connection is recommended and easy to apply. 

5.  Use a ground trace to shield the SET pin. This provides another layer of protection from radiated signals. 

6.  Place R1 and R2 close to the DIV pin. A direct, short connection to the DIV pin minimizes the external signal coupling. 

Rev. B 

22 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **TYPICAL APPLICATIONS** 

## **Timed Power Switches, Auto Shutoff After One Hour** 

**==> picture [422 x 193] intentionally omitted <==**

**----- Start of picture text -----**<br>
P-CHANNEL<br>MOSFET<br>*<br>3V TO 36V TO LOAD<br>5V COUT CURRENT DEPENDS<br>LTC4412HV ON PMOS SELECTION<br>0.1µF VIN SENSE<br>PUSH TO ACTIVATE<br>GND GATE<br>LOW = ON CTL STAT<br>HIGH = OFF<br>RST OUT *DRAIN-SOURCE DIODE OF MOSFET<br>100k LTC6995-1<br>GND V [+] 5V<br>RSET R1 0.1µF<br>169k SET DIV 1M 2.6V TO 5.5V IN OUT TO LOADUP TO 2.6A<br>R2 1µF GNDLTC4411 4.7µFCOUT<br>ACTIVE HIGH RESET 887k<br>1/2 tOUT = 1 HOUR CTL STAT 699512 TA08<br>**----- End of picture text -----**<br>


## **5 Second On/Off Timed Relay Driver** 

**==> picture [228 x 180] intentionally omitted <==**

**----- Start of picture text -----**<br>
12V<br>0.1µF<br>L<br>C<br>D1<br>1N4148 NO<br>RESET 1<br>R4<br>RUN 10k COTO 1022 RELAY<br>RELAY ENABLE RST OUT Q1 9001-12-01<br>2N2219A<br>LTC6995-1<br>5V<br>GND V [+]<br>R1 C2<br>1M 0.1µF<br>SET DIV<br>R2<br>R3<br>392k<br>118k<br>699512 TA02<br>**----- End of picture text -----**<br>


Rev. B 

23 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **TYPICAL APPLICATIONS** 

## **1.5ms Radio Control Servo Reference Pulse Generator** 

**==> picture [364 x 121] intentionally omitted <==**

**----- Start of picture text -----**<br>
5V 20ms 1.5ms<br>FRAME RATE REFERENCE<br>R7<br>10k GENERATOR 20ms PERIOD PULSE<br>RESET = OPEN RST OUT TRIG OUT 1.5ms PULSE<br>RUN = GND<br>LTC6995-1 LTC6993-1<br>5V 5V<br>GND V [+] GND V [+]<br>C1 C2<br>R4 0.01µF R1 0.1µF<br>976k 1M<br>SET DIV SET DIV<br>R6 R5 R3 R2<br>121k 102k 146k 280k<br>699512 TA03<br>**----- End of picture text -----**<br>


**Cycling (10 Seconds On/Off) Symmetrical Power Supplies** 

**==> picture [224 x 198] intentionally omitted <==**

**----- Start of picture text -----**<br>
M2<br>Si4435DY<br>15VIN 15VOUT<br>R6<br>20k<br>R2<br>R11 1k<br>5k<br>M3<br>RST OUT<br>Si9410<br>LTC6995-1<br>GND V [+] 5V<br>R8 C1<br>1M 0.1µF<br>SET DIV M4<br>Si4435DY<br>R10 R9<br>237k 392k R3 R1<br>50k 100k<br>–15VIN –15VOUT<br>M1<br>Si9410 699512 TA04<br>**----- End of picture text -----**<br>


**Isolated AC Load Flasher** 

**==> picture [423 x 130] intentionally omitted <==**

**----- Start of picture text -----**<br>
5V 0.1µF<br>R310k 5 R4 U2 R5 40W LAMP<br>OPEN = OFF 1 V [+] 6 215Ω           1 MOC3041M 6 5.94k HOT<br>RST OUT<br>GND = ON 117V AC<br>LTC6995-1 R1 R7<br>2<br>3 SET DIV 4 1M 5V U3 100Ω<br>237kRSET GND2 R2392k CROSSINGZERO 4 R6 NTE5642 C20.022µF<br>10k<br>NEUTRAL<br>10 SECONDS ON/OFF 699512 TA05 AC<br>**----- End of picture text -----**<br>


ISOLATION BARRIER = 7500V 

Rev. B 

24 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **TYPICAL APPLICATIONS** 

## **Interval (Wiper) Timer** 

**==> picture [463 x 304] intentionally omitted <==**

**----- Start of picture text -----**<br>
2s<br>5s<br>15s<br>5V 30s<br>V [+]<br>1m<br>2m<br>4m<br>OFF<br>RST OUT TRIG OUT OUTPUT<br>24.9k LTC6995-1 LTC6993-1 2s<br>2s GND V [+] V [+] GND V [+] V [+]<br>178k 15s5s 0.1µF 1M 0.1µF 1M tINTERVAL<br>30s 2 SECONDS TO<br>59k SET DIV SET DIV 4 MINUTES<br>1m<br>2m 383k 681k<br>29.4k 4m OFF 2s<br>699512 TA06<br>90.9k<br>2s<br>280k<br>5s<br>15s<br>30s<br>113k<br>1m<br>2m<br>133k 4m OFF<br>154k<br>**----- End of picture text -----**<br>


## **Adjustable Time Lapse Photography Intervalometer** 

**==> picture [467 x 207] intentionally omitted <==**

**----- Start of picture text -----**<br>
SHUTTER<br>OPEN<br>TIME LAPSE TIME LAPSE<br>RST OUT TRG OUT OUTPUT<br>LTC6995-1 LTC6993-3<br>GND V [+] V [+] GND V [+] V [+]<br>0.1µF 1M<br>66.5k 3s TO 30m TO 56.2k<br>SET DIV 30s 3Hrs SET DIV<br>SHORT SHORT<br>1M 2M LONG TIMER 30s TO 3m TO 1M 2M NON-RETRIGGERABLE<br>LONG 3s TO 3Hrs 392k 3m 30m 967k LONG ONE SHOT TIMER<br>0.3s TO 30s<br>523k 681k 0.3s TO 3s TO<br>3s 30s<br>681k 887k<br>1M<br>TIME LAPSE EXPOSURE TIME 699512 TA09<br>**----- End of picture text -----**<br>


Rev. B 

25 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 **PACKAGE DESCRIPTION** 

**==> picture [524 x 640] intentionally omitted <==**

**----- Start of picture text -----**<br>
S6 Package<br>6-Lead Plastic TSOT-23<br>(Reference LTC DWG # 05-08-1636)<br>0.62 0.95 2.90 BSC<br>MAX REF (NOTE 4)<br>1.22 REF<br>e ee nae<br>3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC 1.50 – 1.75(NOTE 4)<br>PIN ONE ID<br>ooo | oo<br>RECOMMENDED SOLDER PAD LAYOUT 0.30 – 0.45<br>PER IPC CALCULATOR 0.95 BSC nut| be 6 PLCS (NOTE 3)<br>0.80 – 0.90<br>0.20 BSC<br>0.01 – 0.10<br>1.00 MAX<br>DATUM ‘A’<br>| i<br>sn+. 0.30 – 0.50 REF 0.09 – 0.20 ; EES= 1.90 BSC | fs |<br>(NOTE 3) S6 TSOT-23 0302<br>NOTE:<br>1. DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR<br>2. DRAWING NOT TO SCALE 5. MOLD FLASH SHALL NOT EXCEED 0.254mm<br>3. DIMENSIONS ARE INCLUSIVE OF PLATING 6. JEDEC PACKAGE REFERENCE IS MO-193<br>DCB Package<br>6-Lead Plastic DFN (2mm  ×  3mm)<br>(Reference LTC DWG # 05-08-1715 Rev A)<br>2.00 ±0.10 R = 0.115 0.40 ±0.10<br>(2 SIDES) R = 0.05 TYP 4 6<br>0.70 ±0.05 TYP<br>PACKAGE<br>3.55 ±0.05 1.65 ±0.05 OUTLINE 3.00 ±0.10 1.65 ±0.10<br>(2 SIDES) (2 SIDES) (2 SIDES)<br>2.15 ±0.05<br>Tee PIN 1 BAR an PIN 1 NOTCH<br>TOP MARK R0.20 OR 0.25<br>(SEE NOTE 6) × 45° CHAMFER<br>3 1 (DCB6) DFN 0405<br>0.25 ±0.05 0.25 ±0.05<br>0.50 BSC 0.200 REF 0.75 ±0.05 0.50 BSC<br>1.35 ±0.05 1.35 ±0.10<br>n i es = | Tal<br>(2 SIDES) (2 SIDES)<br>RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD<br>Coo l 7<br>NOTE: 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE<br>1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)     MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE<br>2.  DRAWING NOT TO SCALE 5. EXPOSED PAD SHALL BE SOLDER PLATED<br>3. ALL DIMENSIONS ARE IN MILLIMETERS 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE<br>TOP AND BOTTOM OF PACKAGE<br>Rev. B<br>a<br>**----- End of picture text -----**<br>


26 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **REVISION HISTORY** 

|**REV**|**DATE**|**DESCRIPTION**|**PAGE NUMBER**|
|---|---|---|---|
|A|09/13|Grammatical corrections<br>Correction to Master Oscillator, Block Diagram<br>DIVCODE changed from 4 to 5, Figure 19a<br>DIVCODE changed from 11 to 10, Figure 19b<br>LTC6995 block identified as LTC6995-1, Figure 21 and Figure 22<br>Replace V+with 5V, Sentry Time schematic|1, 4, 8, 16<br>8<br>20<br>20<br>21, 22<br>28|
|B|12/19|Added AEC-Q100 Qualified Note to Front Page<br>Added W Grade Order Information|1<br>3|



Rev. B 

27 

For more information www.analog.com 

- - LTC6995 1/LTC6995 2 

## **TYPICAL APPLICATION** 

## **Sentry Timer** 

**==> picture [346 x 229] intentionally omitted <==**

**----- Start of picture text -----**<br>
5V<br>Q CLK<br>5V FF<br>Q D 5V<br>100k<br>CLR<br>PUSH BUTTON RST OUT<br>EVERY 4 HOURS OR<br>ALARM SOUNDS LTC6995-2 15Ω<br>GND V [+] 5V 800Hz<br>4 HOUR TIMER ALARM TONE<br>R1 DIVCODE = 7 DIVCODE = 0<br>887k<br>SET DIV<br>R2 32Ω<br>49.9k 60.4k<br>332k<br>75k<br>699512 TA07<br>**----- End of picture text -----**<br>


## **RELATED PARTS** 

|**RELATED**|**PARTS**||
|---|---|---|
|**PART NUMBER**|**DESCRIPTION**|**COMMENTS**|
|LTC1799|1MHz to 33MHz ThinSOT Silicon Oscillator|Wide Frequency Range|
|LTC6900|1MHz to 20MHz ThinSOT Silicon Oscillator|Low Power, Wide Frequency Range|
|LTC6906/LTC6907|10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillators|Micropower, ISUPPLY= 35µA at 400kHz|
|LTC6930|Fixed Frequency Oscillator, 32.768kHz to 8.192MHz|0.09% Accuracy, 110µs Start-Up Time, 105µA at 32kHz|
|LTC6990|TimerBlox: Voltage-Controlled Silicon Oscillator|Fixed-Frequency or Voltage-Controlled Operation|
|LTC6991|TimerBlox: Very Low Frequency Oscillator with Reset|Cycle Time from 1ms to 9.5 Hours, No Capacitors, 2.2% Accurate|
|LTC6992|TimerBlox: Voltage-Controlled Pulse Width Modulator(PWM)|Simple PWM with Wide Frequency Range|
|LTC6993|TimerBlox: Monostable Pulse Generator(One Shot)|Resistor Programmable Pulse Width of 1µs to 34sec|
|LTC6994|TimerBlox: Delay Block/Debouncer|Delays Rising, Falling or Both Edges 1µs to 34sec|



Rev. B 

12/19 

28 

www.analog.com 

 ANALOG DEVICES, INC. 2013–2019 

For more information www.analog.com