# Power MOSFET, P Channel, 16.5 V, 500 mA, 1.5 ohm, TO-92, Through Hole

![Product image](https://novapart.co/image/farnell:2851547/)

**URL**: https://novapart.co/products/LP0701N3-G/power-mosfet-p-channel-165-v-500-ma-15-ohm-to-92
**SKU**: LP0701N3-G
**Manufacturer**: MICROCHIP
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.1000
**Stock**: 200+
**Lead Time**: 358 days (indicative)

## Description

Transistor Polarity:P Channel; Continuous Drain Current Id:-500mA; Drain Source Voltage Vds:-16.5V; On Resistance Rds(on):1.3ohm; Rds(on) Test Voltage Vgs:-5V; Threshold Voltage Vgs:

## Specifications

| Parameter | Value |
|---|---|
| Msl | - |
| Svhc | No SVHC (04-Feb-2026) |
| No. Of Pins | 3Pins |
| Channel Type | P Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 1W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 5V |
| Transistor Case Style | TO-92 |
| Drain Source Voltage Vds | 16.5V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 500mA |
| Drain Source On State Resistance | 1.5ohm |
| Gate Source Threshold Voltage Max | 700mV |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2851547/)

_**Su ertex inc. p**_ 

**LP0701** 

## **P-Channel Enhancement-Mode Lateral MOSFET** 

## **Features** 

- Ultra-low threshold 

- High input impedance 

- Low input capacitance 

- Fast switching speeds 

- Low on-resistance 

- Freedom from secondary breakdown 

- Low input and output leakage 

## **Applications** 

- Logic level interfaces 

- Solid state relays 

- Battery operated systems 

## **General Description** 

These enhancement-mode (normally-off) transistors utilize a lateral MOS structure and Supertex’s well-proven silicongate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and negative temperature coefficient inherent in MOS devices. 

Characteristic of all MOS structures, these devices are free from thermal runaway and thermally induced secondary breakdown. The low threshold voltage and low on-resistance characteristics are ideally suited for hand held, battery operated applications. 

- Photo voltaic drives 

- Analog switches 

► General purpose line drivers **Ordering Information Product Summary Part Number Package Options Packing BV /BV R V I DSS DGS DS(ON) GS(TH) D(ON)** LP0701LG-G 8-Lead SOIC 2500/Reel -16.5V 3.0kΩ -1.0V (max) 3.0mA (min) LP0701N3-G TO-92 1000/Bag ~~————~~ LP0701N3-G P002 TO-92 2000/Reel **Pin Configuration** LP0701N3-G P003 TO-92 2000/Reel **D D** LP0701N3-G P005 TO-92 2000/Reel **D           D** LP0701N3-G P013 TO-92 2000/Reel **DRAIN** LP0701N3-G P014 TO-92 2000/Reel **G            S SOURCE** ~~ee~~ **NC** _-G  denotes a lead (Pb)-free / RoHS compliant package_ **NC GATE** _Refer to ‘P0xx’ Tape & Reel Specs for P002, P003, P005, P013, and P014_ **8-Lead SOIC TO-92** _TO-92 Taping Specifications and Winding Styles_ **Product Marking Absolute Maximum Ratings YYWW** YY = Year Sealed **Parameter Value** WW = Week Sealed **P0701** L = Lot Number Drain-to-source voltage BVDSS **LLLL** = “Green” Packaging Drain-to-gate voltage BVDGS _Package may or may not include the following marks: Si or_ Gate-to-source voltage ±10V **8-Lead SOIC** Operating and storage temperature -55°C to +150°C _Absolute Maximum Ratings are those values beyond which damage to the device may_ **SiLP** YY = Year Sealed _occur. Functional operation under these conditions is not implied. Continuous operation_ **0 7 0 1** WW = Week Sealed _of the device at the absolute rating level may affect device reliability. All voltages are_ **YYW W** = “Green” Packaging _referenced to device ground._ ~~==".~~ _Package may or may not include the following marks: Si or_ 

**TO-92** 

_**Supertex inc. www.supertex.com**_ 

_Doc.# DSFP-LP0701 B071513_ 

**LP0701** 

## **Thermal Characteristics** 

|**Package**|**ID**<br>**(continuous)****_†_**<br>**(mA)**|**ID**<br>**(pulsed)****_†_**<br>**(A)**|**Power Dissipation**<br>**@TC = 25OC**<br>**(W)**|**_θja_**<br>**(OC/W)**|**IDR**<br>**(mA)**|**IDRM**<br>**_†_**<br>**(A)**|
|---|---|---|---|---|---|---|
|8-Lead SOIC|-700|-1.25|1.5_‡_|101_‡_|-700|-1.25|
|TO-92|-500|-1.25|1.0|132|-500|-1.25|



## _**Notes:**_ 

- _ID (continuous) is limited by max rated Tj._ 

- _Mounted on FR4 board, 25mm x 25mm x 1.57mm_ 

## **Electrical Characteristics** _(TA = 25°C unless otherwise specified)_ 

**==> picture [542 x 376] intentionally omitted <==**

**----- Start of picture text -----**<br>
Sym Parameter Min Typ Max Units Conditions<br>BVDSS Drain-to-source breakdown voltage -16.5 - - V VGS = 0V, ID = -1.0mA<br>VGS Gate threshold voltage -0.5 -0.7 -1.0 V VGS = VDS, ID = -1.0mA<br>ΔVGS(th) Change in VGS(th) with temperature - - -4.0 mV/ [O] C VGS = VDS, ID = -1.0mA<br>IGSS Gate body leakage - - -100 nA VGS = ±10V, VDS = 0V<br>- - -100 nA VDS = -15V, VGS = 0V<br>IDSS Zero gate voltage drain current - - -1.0 mA VDS = 0.8 Max Rating,<br>VGS = 0V, TA = 125 [O] C<br>- -0.4 - V  = V  = -2.0V<br>GS DS<br>I On-state drain current -0.6 -1.0 - A V  = V  = -3.0V<br>D(ON) GS DS<br>-1.25 -2.30 - V  = V  = -5.0V<br>GS DS<br>- 2.0 4.0 VGS = -2.0V, ID = -50mA<br>Static drain-to-source on-state<br>RDS(ON) resistance - 1.7 2.0 Ω VGS = -3.0V, ID = -150mA<br>- 1.3 1.5 VGS = -5.0V, ID = -300mA<br>ΔRDS(ON) Change in RDS(ON) with temperature - - 0.75 %/ [O] C VGS = -5.0V, ID = -300mA<br>GFS Forward transconductance 500 700 - mmho  VGS = -15V, ID = -1.0A<br>CISS Input capacitance - 120 250 VGS = 0V,<br>COSS Common source output capacitance - 100 125 pF VDS = -15V,<br>CRSS Reverse transfer capacitance - 40 60 f = 1.0MHz<br>td(ON) Turn-on delay time - - 20<br>t Rise time - - 20 VDD = -15V,<br>td(OFF)r Turn-off delay time - - 30 ns RID = -1.25A,GEN = 25Ω<br>t Fall time - - 30<br>f<br>VSD Diode forward voltage drop - -1.2 -1.5 V VGS = 0V, ISD = -500mA<br>**----- End of picture text -----**<br>


_**Notes:**_ 

_1. All D.C. parameters 100% tested at 25[O] C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)_ 

_2. All A.C. parameters sample tested._ 

## **Switching Waveforms and Test Circuit** 

**==> picture [418 x 114] intentionally omitted <==**

**----- Start of picture text -----**<br>
0V Pulse<br>10%<br>Generator<br>INPUT<br>-10V 90% RGEN<br>t(ON) t(OFF)<br>D.U.T.<br>td(ON) tr td(OFF) tf INPUT<br>OUTPUT<br>0V<br>OUTPUT 90% 90% RL<br>10% 10%<br>VDD<br>VDD<br>**----- End of picture text -----**<br>


_**Supertex inc.**_ 

_Doc.# DSFP-LP0701 B071513_ 

_**www.supertex.com**_ 

2 

**LP0701** 

## **Typical Performance Curves** 

**==> picture [191 x 609] intentionally omitted <==**

**----- Start of picture text -----**<br>
Output Characteristics<br>-2.5<br>VGS = -5.0V<br>-2.0<br>-4V<br>-1.5<br>-3V<br>-1.0<br>-2V<br>-0.5<br>-1V<br>0<br>0 -4 -8 -12 -16<br>VDS (volts)<br>Transconductance vs. Drain Current<br>1.0<br>VDS = -15V TA = -55 [O] C<br>0.8<br>0.6 TA = 25 [O] C<br>TA = 125 [O] C<br>0.4<br>0.2<br>0<br>0 -1.0 -2.0<br>ID (amperes)<br>Maximum Rated Safe Operating Area<br>-10<br>TO-92/SO-8 (pulsed)<br>-1.0<br>TO-92 (DC)<br>-0.1 SO-8 (DC)<br>TC = 25 [O] C<br>-0.01<br>-0.1 -1.0 -10 -100<br> VDS (volts)<br>(amperes)<br>ID<br>(seimens)<br>FS<br>G<br>(amperes)<br>ID<br>**----- End of picture text -----**<br>


**==> picture [191 x 612] intentionally omitted <==**

**----- Start of picture text -----**<br>
Saturation Characteristics<br>-2.5<br>VGS = -5.0V<br>-2.0<br>-4V<br>-1.5<br>-3V<br>-1.0<br>-2V<br>-0.5<br>-1V<br>0<br>0 -1 -2 -3 -4 -5<br>VDS (volts)<br>Power Dissipation vs. Case Temperature<br>2<br>SO-8<br>TO-92<br>1<br>0<br>0 25 50 75 100 125 150<br>TC ( [O] C)<br>Thermal Response Characteristics<br>1.0<br>0.8<br>0.6<br>TO-92<br>0.4 TC = 25V<br>PD = 1.0W<br>0.2<br>0<br>0.001 0.01 0.1 1.0 10<br>tp (seconds)<br>(amperes)<br>ID<br>(watts)<br>D<br>P<br>Thermal Resistance (normalized)<br>**----- End of picture text -----**<br>


_**Supertex inc.**_ 

_Doc.# DSFP-LP0701 B071513_ 

_**www.supertex.com**_ 

3 

**LP0701** 

## **Typical Performance Curves (cont.)** 

**==> picture [185 x 399] intentionally omitted <==**

**----- Start of picture text -----**<br>
 BVDSS Variation with Temperature<br>1.1<br>1.0<br>0.9<br>-50 0 50 100 150<br>TJ ( [O] C)<br>Transfer Characteristics<br>-2<br>VDS = -15V<br>-1<br>0<br>0 -1 -2 -3 -4 -5<br>V<br>GS (volts)<br> TA = -55OC<br> TA = 25OC<br> TA = 125OC<br> (normalized)<br>DSS<br>BV<br>(amperes)<br>ID<br>**----- End of picture text -----**<br>


**==> picture [189 x 188] intentionally omitted <==**

**----- Start of picture text -----**<br>
Capacitance vs. Drain-to-Source Voltage<br>200<br>f = 1.0MHz<br>CISS<br>100<br>COSS<br>CRSS<br>0<br>0 -5 -10 -15<br>VDS (volts)<br>C (picofarads)<br>**----- End of picture text -----**<br>


**==> picture [212 x 605] intentionally omitted <==**

**----- Start of picture text -----**<br>
On-Resistance vs. Drain Current<br>10<br>VGS = -2.0V<br>8<br>VGS = -3.0V<br>VGS = -5.0V<br>6<br>4<br>2<br>0<br>0 -1 -2 -3<br>ID (amperes)<br>V(th) and RDS Variation with Temperature<br>1.4 1.6<br>1.2 V(th) @ -1.0mA 1.4<br>1.0 1.2<br>0.8 1.0<br>RDS(ON) @ -5V, -300mA<br>0.6 0.8<br>0.4 0.6<br>-50 0 50 100 150<br>TJ ( [O] C)<br>Gate Drive Dynamic Characteristics<br>-10<br>VDS = -10V<br>-8<br>-20V<br>-6<br>238pF<br>-4<br>-2<br>CISS = 115pF<br>0<br>0 1 2 3 4 5<br>QG (nanocoulombs)<br> (ohms)<br>DSS(ON)<br>R<br>(normalized) (normalized)<br>GS(th)  DS(ON)<br>V R<br>(volts)<br>GS<br>V<br>**----- End of picture text -----**<br>


_**Supertex inc.**_ 

_Doc.# DSFP-LP0701 B071513_ 

_**www.supertex.com**_ 

4 

**LP0701** 

## **8-Lead SOIC (Narrow Body) Package Outline (LG)** 

**==> picture [459 x 314] intentionally omitted <==**

**----- Start of picture text -----**<br>
θ1<br>D<br>8<br>Note 1<br>(Index Area<br>D/2 x E1/2)<br>E1 E<br>L2 Gauge<br>Plane<br>L Seating<br>1 θ Plane<br>L1<br>Top View View B<br>View B<br>Note 1<br>h<br>h<br>A [A2]<br>Seating<br>Plane<br>A1 e b<br>Side View View A-A-AA<br>A<br>A<br>**----- End of picture text -----**<br>


**View A-A-AA** 

## _**Note:**_ 

_1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator._ 

**==> picture [542 x 74] intentionally omitted <==**

**----- Start of picture text -----**<br>
Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1<br>MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80* 0.25 0.40 0 [O] 5 [O]<br>Dimension 1.27 1.04 0.25<br>NOM - - - - 4.90 6.00 3.90 - - - -<br>(mm) BSC REF BSC<br>MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8 [O] 15 [O]<br>**----- End of picture text -----**<br>


- _JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. * This dimension is not specified in the JEDEC drawing._ 

## _**Drawings are not to scale.**_ 

_**Supertex Doc. #:** DSPD-8SOLGTG, Version I041309._ 

_**Supertex inc.**_ 

_Doc.# DSFP-LP0701 B071513_ 

_**www.supertex.com**_ 

5 

**LP0701** 

## **3-Lead TO-92 Package Outline (N3)** 

**==> picture [295 x 219] intentionally omitted <==**

**----- Start of picture text -----**<br>
D<br>A<br>Seating<br>Plane 1     2     3<br>L<br>b c<br>e1<br>e<br>**----- End of picture text -----**<br>


## **Front View** 

## **Side View** 

**==> picture [131 x 67] intentionally omitted <==**

**----- Start of picture text -----**<br>
E<br>E1<br>1 3<br>2<br>**----- End of picture text -----**<br>


## **Bottom View** 

**==> picture [542 x 73] intentionally omitted <==**

**----- Start of picture text -----**<br>
Symbol A b c D E E1 e e1 L<br>MIN .170 .014 [†] .014 [†] .175 .125 .080 .095 .045 .500<br>Dimensions<br>NOM - - - - - - - - -<br>(inches)<br>MAX .210 .022 [†] .022 [†] .205 .165 .105 .105 .055 .610*<br>**----- End of picture text -----**<br>


_JEDEC Registration TO-92. * This dimension is not specified in the JEDEC drawing._ 

_† This dimension differs from the JEDEC drawing._ 

## _**Drawings not to scale.**_ 

_**Supertex Doc.#:** DSPD-3TO92N3, Version E041009._ 

_(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)_ 

_**Supertex inc.**_ does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” _**Supertex inc.**_ does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the _**Supertex inc.**_ (website: http//www.supertex.com) 

©2013 _**Supertex inc.**_ All rights reserved. Unauthorized use or reproduction is prohibited. 

_**Supertex inc.**_ 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 _**www.supertex.com**_ 

_Doc.# DSFP-LP0701 B071513_ 

6 



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