LNK414EG

## LNK403-410/413-420 LinkSwitch-PH ™ LED Driver IC Family 

Single-Stage PFC, Primary-Side Constant Current Control and TRIAC Dimming/Non-Dimming Options 

## Product Highlights 

## 

- Single-stage combination of power factor correction and accurate constant-current (CC) output 

- Enables very long lifetime designs (no electrolytic capacitors) 

- Eliminates optocoupler and all secondary current control circuitry 

- Eliminates control loop compensation circuitry 

- Simple primary-side PWM dimming interface 

- Universal input voltage range 

- LNK403-410 optimized for fl icker-free TRIAC dimming 

## **EcoSmart[™]** 

- Single-stage PFC combined with output CC control 

- Greatly increases effi ciency, >90% achievable 

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RV<br>AC<br>IN<br>D V LinkSwitch-PH<br>CONTROL<br>BP<br>S R FB<br>PI-6543-082211<br>**----- End of picture text -----**<br>


_Figure 1. Typical Application Schematic._ 

- Reduces component count 

- No current sense resistors 

- Low standby power remote ON/OFF feature (<50 mW at 230 VAC) 

## **Accurate and Consistent Performance** 

- Compensates for transformer inductance variations 

- Compensates for line input voltage variation 

- Frequency jittering greatly reduces EMI fi lter size and cost 

## **Advanced Protection and Safety Features** 

- Auto-restart for short-circuit protection 

- Open circuit fault detection mode 

- Automatic thermal shutdown restart with hysteresis 

- Meets high voltage creepage requirement between DRAIN and all other signal pins both on PCB and at package 

## **Output Power Table[1,2]** 

|**Product5**|RV= 2 MW|RV= 2 MW|RV= 4 MW|RV= 4 MW|
|---|---|---|---|---|
||85-132 VAC||85-308 VAC||
||**Minimum**<br>**Output**<br>**Power3**|**Maximum**<br>**Output**<br>**Power4**|**Minimum**<br>**Output**<br>**Power3**|**Maximum**<br>**Output**<br>**Power4**|
|**LNK403/413E/L**<br>**LNK404/414E/L**<br>**LNK405/415E/L**<br>**LNK406/416E/L**<br>**LNK407/417E/L**<br>**LNK408/418E/L**<br>**LNK409/419E/L**<br>**LNK410/420E/L**|2.5 W<br>2.5 W<br>3.8 W<br>4.5 W<br>5.5 W<br>6.8 W<br>8.0 W<br>18 W|4.5 W<br>5.5 W<br>7.0 W<br>8.0 W<br>10 W<br>13.5 W<br>20 W<br>31 W|6.5 W<br>6.5 W<br>8.5 W<br>10 W<br>12 W<br>16 W<br>18 W<br>40 W|12 W<br>15 W<br>18 W<br>22 W<br>25 W<br>35 W<br>50 W<br>78 W|



## **Green Package** 

- Halogen free and ROHS compliant package 

_Table 1.    Output Power Table._ 

Notes _:_ 

## **Applications** 

- Off-line LED driver 

_1. Continuous power in an open frame with adequate heat sinking at device local ambient of 70 °C._ 

_2.  Power level calculated on typical LED string voltage with effi ciency_ > _80%._ 

_3. Minimum output power with CBP = 10_ m _F._ 

## Description 

_4.  Maximum output power with CBP = 100_ m _F.  LNK4x3EG CBP = 10_ m _F._ 

_5. Package: eSIP-7C, eSIP-7F._ 

The LinkSwitch-PH dramatically simplifi es implementation of LED drivers requiring long lifetime, high effi ciency, PF >0.9, and TRIAC dimming capability (LNK403-410).  The single-stage combined power factor and constant-current controller eliminates a switching stage and the electrolytic bulk capacitor.  The advanced primaryside control used by the LinkSwitch-PH device provides accurate constant current control while eliminating the need for an optocoupler and current sensing circuits. 

LinkSwitch-PH incorporates a 725 V power FET, a continuousmode PWM controller, a high-voltage switched current source for self biasing, frequency jittering, protection circuitry including cycle-by-cycle current limit and hysteretic thermal shutdown. 

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eSIP-7C (E Package)    eSIP-7F (L Package)<br>**----- End of picture text -----**<br>


_Figure 2. Package Options._ 

www.powerint.com 

May 2012 

**LNK403-410/413-420** 

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DRAIN (D)<br>BYPASS (BP) REGULATOR5.9 V<br>BYPASS<br>CAPACITOR SOFT-START<br>SELECT TIMER HYSTERETIC<br>THERMAL<br>SHUTDOWN<br>FAULT<br>ILIM MI AUTO-RESTART PRESENT 5.9 V<br>5.0 V<br>COUNTER<br>BYPASS PIN<br>1 V UNDERVOLTAGE DriverGate<br>VOLTAGE SenseFet<br>MONITOR (V) STOP JITTER<br>LOGIC CLOCK<br>Comparator<br>OSCILLATOR<br>LEB<br>3-VT DCFBMAXOFF<br>OCP<br>UV/OV<br>LINE<br>SENSE<br>FEEDBACK (FB) IV PFC/CC CURRENT LIMITCOMPARATOR ILIM<br>VBG IFB CONTROL MI VSENSE<br>FEEDBACK FBOFF<br>SENSE DCMAX<br>IS<br>REFERENCE (R) REFERENCEBLOCK VBG<br>6.4 V<br>PI-5431-102610 SOURCE (S)<br>+<br>-<br>-<br>+<br>+<br>-<br>**----- End of picture text -----**<br>


_Figure 3.   Functional Block Diagram._ 

## Pin Functional Description 

## DRAIN (D) Pin: 

This pin is the power FET drain connection.  It also provides internal operating current for both start-up and steady-state operation. 

## SOURCE (S) Pin: 

This pin is the power FET source connection.  It is also the ground reference for the BYPASS, FEEDBACK, REFERENCE and VOLTAGE MONITOR pins. 

## **BYPASS (BP) Pin:** 

This is the connection point for an external bypass capacitor for the internally generated 5.9 V supply.  This pin also provides output power selection through choice of the BYPASS pin capacitor value. 

## FEEDBACK (FB) Pin: 

The FEEDBACK pin is used for output voltage feedback.  The current into the FEEDBACK pin is directly proportional to the output voltage.  The FEEDBACK pin also includes circuitry to protect against open load and overload output conditions. 

## REFERENCE (R) Pin: 

This pin is connected to an external precision resistor and is used to configure for dimming (LNK403-410) and non-TRIAC dimming (LNK413-420) modes of operation. 

## VOLTAGE MONITOR (V) Pin: 

This pin interfaces with an external input line peak detector, consisting of a rectifier, filter capacitor and resistors.  The applied current is used to control stop logic for line undervoltage (UV), overvoltage (OV), provide feed-forward to control the output current and the remote ON/OFF function. 

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Exposed Pad<br>(Backside) Internally<br>Connected to<br>SOURCE Pin<br>E Package (eSIP-7C)<br>(Top View) L Package (eSIP-7F)<br>7 D<br>5 S<br>4 BP<br>3 FB<br>2 V<br>1 R<br>Exposed Pad 1 3 5<br>(backside) Internally R FB S<br>Connected to  Lead Bend Outward  2 4 7<br>SOURCE Pin (see  from Drawing V BP D<br>eSIP-7C Package  (Refer to eSIP-7F Package<br>Drawing) Outline Drawing)<br>PI-5432-082411<br>**----- End of picture text -----**<br>


_Figure 4.   Pin Configuration._ 

**2** 

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Rev. E 05/12 

**LNK403-410/413-420** 

## Functional Description 

A LinkSwitch-PH device monolithically integrates a controller and high-voltage power FET into one package.  The controller implements both high power factor and a constant current output in a single stage.  The LinkSwitch-PH controller consists of an oscillator, feedback (sense and logic) circuit, 5.9 V regulator, hysteretic over-temperature protection, frequency jittering, cycle-by-cycle current limit, auto-restart, inductance correction, power factor and constant current control. 

## FEEDBACK Pin Current Control Characteristics 

The figure shown below illustrates the operating boundaries of the FEEDBACK pin current.  Above IFB(SKIP) switching is disabled and below I the device enters into auto-restart. FB(AR) 

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I<br>FB(SKIP) Skip-Cycle<br>IFB CC ControlRegion<br>I<br>FB(DCMAXR)<br>Soft-Start and<br>CC Fold-Back<br>Region<br>I<br>FB(AR) Auto-Restart<br>DC10 DCMAX<br>Maximum Duty Cycle<br>PI-5433-060410<br>Figure 5.  FEEDBACK Pin Current Characteristic.<br>**----- End of picture text -----**<br>


The FEEDBACK pin current is also used to clamp the maximum duty cycle to limit the available output power for overload and open-loop conditions.  This duty cycle reduction characteristic also promotes a monotonic output current start-up characteristic to prevent over-shoot. 

## REFERENCE Pin 

The REFERENCE pin is tied to ground (SOURCE) via an external resistor.  The value selected sets the internal references, determining the operating mode for dimming (LNK403-410) and non-dimming (LNK413-420) operation and the line undervoltage and overvoltage thresholds of the VOLTAGE MONITOR pin.  For 

non-dimming or PWM dimming applications with LNK413-420, the external resistor should be a 24.9 kW ±1%, for high-line and universal input voltage designs, and 49.9 kW ±1% for low-line input voltage designs.  For phase angle AC dimming with LNK403-410, the external resistor should be a 49.9 kW ±1%. One percent resistors are recommended as the resistor tolerance directly affects the output tolerance.  Other resistor values should not be used. 

## BYPASS Pin Capacitor Power Gain Selection 

LinkSwitch-PH devices have the capability to tailor the internal gain to either full or a reduced output power setting.  This allows selection of a larger device to minimize dissipation for both thermal and efficiency reasons.  The power gain is selected with the value of the BYPASS pin capacitor.  The full power setting is selected with a 100 mF capacitor and the reduced power setting (for higher efficiency) is selected with a 10 mF capacitor.  The BYPASS pin capacitor sets both the internal power gain as well as the over-current protection (OCP) threshold.  Unlike the larger devices, the LNK4x3 power gain is not programmable. Use a 10 mF capacitor for the LNK4x3. 

## Switching Frequency 

The switching frequency is 66 kHz.  To further reduce the EMI level, the switching frequency is jittered (frequency modulated) by approximately ±1 kHz. 

## Soft-Start 

The controller includes a soft-start timing feature which inhibits the auto-restart protection feature for the soft-start period (tSOFT) to distinguish start-up into a fault (short-circuit) from a large output capacitor.  At start-up the LinkSwitch-PH clamps the maximum duty cycle to reduce the output power.  The total soft-start period is tSOFT. 

## Remote ON/OFF and EcoSmart 

The VOLTAGE MONITOR pin has a 1 V threshold comparator connected at its input.  This voltage threshold is used for remote ON/OFF control.  When a signal is received at the VOLTAGE MONITOR pin to disable the output (VOLTAGE MONITOR pin tied to ground through an optocoupler phototransistor) the LinkSwitch-PH will complete its current switching cycle before the internal power FET is forced off. 

The remote ON/OFF feature can also be used as an eco-mode or power switch to turn off the LinkSwitch-PH and keep it in a very low power consumption state for indefinite long periods. When the LinkSwitch-PH is remotely turned on after entering this mode, it will initiate a normal start-up sequence with soft-start the next time the BYPASS pin reaches 5.9 V.  In the worst case, the delay from remote on to start-up can be equal to the full discharge/charge cycle time of the BYPASS pin.  This reduced consumption remote off mode can eliminate expensive and unreliable in-line mechanical switches. 

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Rev. E 05/12 

**LNK403-410/413-420** 

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D V<br>CONTROL<br>BP<br>S R FB<br>PI-5435-052510<br>**----- End of picture text -----**<br>


_Figure 6. Remote ON/OFF VOLTAGE MONITOR pin Control_ 

## 5.9 V Regulator/Shunt Voltage Clamp 

The internal 5.9 V regulator charges the bypass capacitor connected to the BYPASS pin to 5.9 V by drawing a current from the voltage on the DRAIN pin whenever the power FET is off.  The BYPASS pin is the internal supply voltage node.  When the power FET is on, the device operates from the energy stored in the bypass capacitor.  Extremely low power consumption of the internal circuitry allows LinkSwitch-PH to operate continuously from current it takes from the DRAIN pin.  A bypass capacitor value of 10 or 100 mF is sufficient for both high frequency decoupling and energy storage.  In addition, there is a 6.4 V shunt regulator clamping the BYPASS pin at 6.4 V when current is provided to the BYPASS pin through an external resistor.  This facilitates powering of LinkSwitch-PH externally through a bias winding to increase operating efficiency.  It is recommended that the BYPASS pin is supplied current from the bias winding for normal operation. 

## Auto-Restart 

In the event of an open-loop fault (open FEEDBACK pin resistor or broken path to feedback winding), output short-circuits or an overload condition the controller enters into the auto-restart mode.  The controller annunciates both short-circuit and open-loop conditions once the FEEDBACK pin current falls below the IFB(AR) threshold after the soft-start period.  To minimize the power dissipation under this fault condition the shutdown/auto-restart circuit turns the power supply on (same as the soft-start period) and off at an auto-restart duty cycle of typically DCAR for as long as the fault condition persists.  If the fault is removed during the auto-restart off-time, the power supply will remain in auto-restart until the full off-time count is completed.  Special consideration must be made to appropriately size the output capacitor to ensure that after the soft-start period (tSOFT) the FEEDBACK pin current is above the IFB(AR) threshold to ensure successful power-supply start-up. After the soft-start time period, auto-restart is activated only when the FEEDBACK pin current falls below IFB(AR). 

## Over-Current Protection 

The current limit circuit senses the current in the power FET. When this current exceeds the internal threshold (ILIMIT), the power FET is turned off for the remainder of that cycle. A leading edge blanking circuit inhibits the current limit comparator for a short time (tLEB) after the power FET is turned on.  This leading edge blanking time has been set so that current spikes caused by capacitance and rectifier reverse recovery will not cause premature termination of the power FET conduction. 

## Line Under/Overvoltage Protection 

This device includes both line under- and overvoltage detection to limit the minimum start-up and maximum operating voltage detected through the VOLTAGE MONITOR pin.  An external peak detector consisting of a diode and capacitor are required to provide input line peak voltage to the VOLTAGE MONITOR pin through a resistor.  At power up, IUV+ keeps the LinkSwitch-PH off until the input line voltage reaches the undervoltage threshold. At power down, IUV- prevents restart attempts after the output goes out of regulation. 

The same resistor used for UV also sets line overvoltage (OV) shutdown threshold which, once exceeded, forces the LinkSwitch-PH to stop switching (after completion of the current switching cycle).  Once the line voltage returns to normal, the device resumes normal operation.  A small amount of hysteresis is provided on the OV threshold to prevent noise triggering. When the power FET is off, the rectified DC high voltage surge capability is increased to the voltage rating of the power FET (725 V), due to the absence of the reflected voltage and leakage spikes on the drain. 

## Hysteretic Thermal Shutdown 

The thermal shutdown circuitry senses the controller die temperature.  The threshold is set at 142 °C typical with a 75 °C hysteresis.  When the die temperature rises above this threshold (142 °C) the power FET is disabled and remains disabled until the die temperature falls by 75 °C, at which point the power FET is re-enabled. 

## Safe Operating Area (SOA) Protection 

The device also features a safe operating area (SOA) protection mode which disables FET switching for 40 cycles in the event the peak switch current reaches the ILIMIT threshold and the switch on-time is less than tON(SOA).  This protection mode protects the device under short-circuited LED conditions and at start-up during the soft-start period when auto-restart protection is inhibited. The SOA protection mode remains active in normal operation. 

**4** 

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**LNK403-410/413-420** 

## Application Example 

## **14 W TRIAC Dimmable High Power Factor LED Driver Design Example** 

The circuit schematic in Figure 7 shows a TRIAC dimmable high power-factor LED driver based on LNK406EG from the LinkSwitch-PH family of devices.  It was optimized to drive an LED string at a voltage of 28 V with a constant current of 0.5 A (±5%) ideal for PAR lamp retro-fit applications.  The design operates over a universal input voltage range of 90 VAC to 265 VAC but provides the specified output current tolerance over a line voltage range of 90 VAC to 132 VAC (this is configurable for high-line only applications by simple component value changes). 

The key goals of this design were compatibility with standard leading edge TRIAC AC dimmers, very wide dimming range (1000:1, 500 mA:0.5 mA), high efficiency (>85%) and high power factor (>0.9).  The design is fully protected from faults such as no-load, overload and output short-circuit conditions and over temperature. 

## Circuit Description 

The LinkSwitch-PH device (U1) integrates the power FET, controller and start-up functions into a single package reducing the component count versus typical implementations.  Configured as part of an isolated continuous conduction mode flyback converter, U1 provides high power factor via its internal control algorithm together with the small input capacitance of the design.  Continuous conduction mode operation results in reduced primary peak and RMS current.  This both reduces EMI noise, allowing simpler, smaller EMI filtering components and improves efficiency.  Output current regulation is maintained without the need for secondary-side sensing which eliminates current sense resistors and improves efficiency. 

## Input Stage 

Fuse F1 provides protection from component failures while RV1 provides a clamp during differential line surges, keeping the peak drain voltage of U1 below the 725 V rating of the internal power FET.  Bridge rectifier BR1 rectifies the AC line voltage. EMI filtering is provided by L1-L3, C1, R16 and R17 together with the safety rated Y class capacitor (C7) that bridges the safety isolation barrier between primary and secondary.  Resistor R16 and R17 act to damp any resonances formed between L1, L2, C1 and the AC line impedance.  A small bulk capacitor (C2) is required to provide a low impedance source for the primary switching current.  The maximum value of C1 and C2 is limited in order to maintain a power factor of greater than 0.9. 

## LinkSwitch-PH Primary 

To provide peak line voltage information to U1 the incoming rectified AC peak charges C3 via D2.  This is then fed into the VOLTAGE MONITOR pin of U1 as a current via R2 and R3.  This sensed current is also used by the device to set the line input overvoltage and undervoltage protection thresholds. Resistor R1 provides a discharge path for C3 with a time constant much longer than that of the rectified AC to prevent generation of line frequency ripple. 

The VOLTAGE MONITOR pin current and the FEEDBACK pin current are used internally to control the average output LED current.  For TRIAC phase-dimming applications a 49.9 kW resistor (R4) is used on the REFERENCE pin and 4 MW (R2+R3) on the VOLTAGE MONITOR pin to provide a linear relationship between input voltage and the output current and maximizing the dimming range.  Resistor R4 also sets the internal line input undervoltage and overvoltage protection thresholds. 

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C8 C10<br>11 FL1 330 50 VµF 330 50 VµF 20 kR15Ω 28 V, 500 mA<br>1000 L3µH MBRS4201T3GD8<br>750 k1%R9 Ω 240 k1/2 WR1 Ω DL4007D2 P6KE200AVR1 1 FL23 RTN<br>L 3.15 AF1 1 kR16Ω 2KBP06M600 VBR1 750 kR101% Ω 510 R181 WΩ 2 M1%R2Ω UF4007D3 RM8T1 2 150 R8Ω DL4936D6 10 kR7Ω 22 50 VC5µF<br>1000 L1µH 2 M1%R3Ω UF4002D4<br>90 - 265VACN 275 VACRV1 1000 R17L2µH 275 VAC47 nFC1 DL4002D1 ZMM5245B-715 VVR2 220 nF630 VC11 100 nF630 VC2 LinkSwitch-PH 400 V1 C3LNK406EGµF U1 D CONTROLV 1N4148D5 BP 3 kR5Ω 162 k1%R6 Ω BAV21WS-7-FD7<br>1 kΩ 2.4 MR11Ω FMMT558Q1 15 nF50 VC6 15 R121%Ω 130 1/2 WR13ΩIRFR310Q2 S R 49.9 k1%R4 FB Ω10 16 VC4µF MMBT39041 kR19ΩQ3 100 nF50 VC13 ZMM5259B-710 kR2039 VVR3Ω 50 V1 C12µF C7<br>2.2 nF<br>250 VAC<br>PI-5997-061510<br>**----- End of picture text -----**<br>


_Figure 7.   Schematic of an Isolated, TRIAC Dimmable, High Power Factor, Universal Input, 14 W LED Driver._ 

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**LNK403-410/413-420** 

Diode D3 and VR1 clamp the drain voltage to a safe level due to the effects of leakage inductance.  Diode D4 is necessary to prevent reverse current from flowing through U1 for the period of the rectified AC input voltage that the voltage across C2 falls to below the reflected output voltage (VOR). 

Diode D6, C5, R7 and R8 create the primary bias supply from an auxiliary winding on the transformer.  Capacitor C4 provides local decoupling for the BYPASS pin of U1 which is the supply pin for the internal controller.  During start-up C4 is charged to ~6 V from an internal high-voltage current source tied to the device DRAIN pin.  This allows the part to start switching at which point the operating supply current is provided from the bias supply via R5.  Capacitor C4 also selects the output power mode (10 mF for reduced power was selected to reduce dissipation in U1 and increase efficiency). 

## Feedback 

The bias winding voltage is proportional to the output voltage (set by the turns ratio between the bias and secondary windings).  This allows the output voltage to be monitored without secondary-side feedback components.  Resistor R6 converts the bias voltage into a current which is fed into the FEEDBACK pin of U1.  The internal engine within U1 combines the FEEDBACK pin current, VOLTAGE MONITOR pin current and drain current information to provide a constant output current over a 1.5:1 output voltage variation (LED string voltage variation of ±25%) at a fixed line input voltage. 

To limit the output voltage at no-load an output overvoltage protection circuit is set by D7, C12, R20, VR3, C13, Q3 and R19. Should the output load be disconnected then the bias voltage will increase until VR3 conducts, turning on Q3 and reducing the current into the FEEDBACK pin.  When this current drops below 20 mA the part enters auto-restart and switching is disabled for 1500 ms allowing time for the output and bias voltages to fall. 

## Output Rectification 

The transformer secondary winding is rectified by D8 and filtered by C8 and C10.  A Schottky barrier diode was selected for efficiency and the combined value of C8 and C10 were selected to give peak-to-peak and LED ripple current equal to 

40% of the mean value.  For designs where lower ripple is desirable the output capacitance value can be increased. A small pre-load is provided by R15 which limits the output voltage under no-load conditions. 

## TRIAC Phase Dimming Control Compatibility 

The requirement to provide output dimming with low cost, TRIAC-based, leading edge phase dimmers introduces a number of trade-offs in the design. 

Due to the much lower power consumed by LED based lighting the current drawn by the overall lamp is below the holding current of the TRIAC within the dimmer.  This can cause undesirable behaviors such as limited dimming range and/or flickering as the TRIAC fires inconsistently.  The relatively large impedance the LED lamp presents to the line allows significant ringing to occur due to the inrush current charging the input capacitance when the TRIAC turns on.  This too can cause similar undesirable behavior as the ringing may cause the TRIAC current to fall to zero and turn off. 

To overcome these issues two circuits, the Active Damper and Passive Bleeder, are incorporated.  The drawback of these circuits is increased dissipation and therefore reduced efficiency of the supply.  For non-dimming applications these components can simply be omitted. 

The Active Damper consists of components R9, R10, R11, R12, D1, Q1, C6, VR2, Q2 in conjunction with R13.  This circuit limits the inrush current that flows to charge C2 when the TRIAC turns on by placing R13 in series for the first 1 ms of the TRIAC conduction.  After approximately 1 ms, Q2 turns on and shorts R13. This keeps the power dissipation on R13 low and allows a larger value during current limiting.  Resistor R9, R10, R11 and C6 provide the 1 ms delay after the TRIAC conducts. Transistor Q1 discharges C6 when the TRIAC is not conducting and VR2 clamps the gate voltage of Q2 to 15 V. 

The Passive Bleeder circuit is comprised of C11 and R18.  This helps to keep the input current above the TRIAC holding current while the input current corresponding to the effective driver resistance increases during each AC half-cycle. 

**6** 

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**LNK403-410/413-420** 

## **7 W High Power Factor Non-Dimmable LED Driver Design Example with Enhanced Line Regulation** 

pin provides excellent line regulation over the entire 90 VAC to 265 VAC input range. 

The circuit schematic in Figure 8 shows a high power-factor LED driver based on a LNK413EG from the LinkSwitch-PH family of devices.  It was optimized to drive an LED string at a voltage of 21 V with a constant current of 0.33 A, ideal for PAR20/PAR30 lamp retro-fit applications.  The design operates over the universal input voltage range of 90 VAC to 265 VAC and is a non-dimming application.  A non-dimming application has tighter output current variation with changes in the line voltage than a dimming application.  It’s key to note that, although not specified for dimming, no circuit damage will result if the end user does operate the design with a phase controlled dimmer. 

## **Circuit Description** 

## Input Stage 

Fuse F1 provides protection from component failures while RV1 provides a clamp during differential line surges, keeping the peak drain voltage of U1 below the 725 V rating of the internal power FET.  Bridge rectifier BR1 rectifies the AC line voltage. EMI filtering is provided by L1-L3, C2 together with the safety rated Y class capacitor (C7) that bridges the safety isolation barrier between primary and secondary.  Resistor R2 and R3 act to damp any resonances formed between L1, L2, C2 and the AC line impedance.  A small bulk capacitor (C3) is required to provide a low impedance source for the primary switching current.  The maximum value of C2 and C3 is limited in order to maintain a power factor of greater than 0.9. 

## LinkSwitch-PH Primary 

To provide peak line voltage information to U1 the incoming rectified AC peak charges C8 via D6.  This is then fed into the VOLTAGE MONITOR pin of U1 as a current via R4, R7 and R8. The VOLTAGE MONITOR pin current and the FEEDBACK pin current are used internally to control the average output LED current.    The combined value of R4, R7 and R8 (3.909 MW) and R11, R12 (1.402 MW) connected to the VOLTAGE MONITOR 

The VOLTAGE MONITOR pin current is also used by the device to set the line input overvoltage and undervoltage protection thresholds. 

Diode D1 and VR1 clamp the drain voltage to a safe level due to the effects of leakage inductance.  A Zener clamp was selected for lowest component count and highest efficiency.  Diode D5 is necessary to prevent reverse current from flowing through U1 during the period when the AC input voltage is lower than the reflected output voltage (VOR).  A space efficient RM6 core was selected for this design.  The RM core geometry helps minimizes audible noise but requires the use of flying leads to meet safety spacing requirements. 

Diode D3, C6, R5, R9 and R18 create the primary bias supply from an auxiliary winding on the transformer.  Resistor R5 provides filtering of leakage inductance generated voltage spikes to improve tracking of the bias and output voltages.  It also forms a pole with C6 at ~100 Hz.  Resistors R9 and R18 act as a small load to ensure that the bias voltage collapses during output short-circuit when U1 enters auto-restart operation to protect the supply. 

Output overvoltage and load disconnection protection is provided by D8, C14, R24, VR3, C15, R23 and Q2.  Should the output LED load become disconnected the output voltage will rise causing an associated rise in the bias winding voltage across C14.  Once this exceeds the voltage rating of VR3, Q2 turns on pulling down the FEEDBACK pin of U1 and initiating auto-restart operation.  Once in auto-restart the low duty cycle of operation (~3%) together with the small pre-load on the output prevents the output voltage rising to a high level.  Once the output load is reconnected normal operation resumes. 

Capacitor C12 provides local decoupling for the BYPASS pin of U1 which is the supply pin for the internal controller.  During 

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C5 C4<br>FL1 FL2 150 35 VµF 150 35 VµF 20 kR6Ω 21 V, 330 mA<br>1000 L3µH MBRS4201T3GD2<br>DL4007D6 P6KE200AVR1 1 FL3<br>RTN<br>6<br>L 3.15 AF1 1 kR2Ω DF06S-E3/45600 VBR1 2 M1 M1%1%R4R7ΩΩ UF4007D1 RM6T1 2 75 R5Ω DL4936D3 10 kR18Ω 10 kR9Ω 22 50 VC6µF<br>1000 L1µH C2 100 nF400 VC3 400 V1 C8µF 909 k1%R8 Ω ES1DD5<br>90 - 265VAC 275 VACRV1 L2 275 VAC22 nF 1N4148D4<br>1000 µH D V 3 kR10Ω R15<br>N R3 1.0 MR111% Ω LinkSwitch-PH LNK413EGU1 CONTROL BP 150 kΩ BAV21WS-7-FD8<br>1 kΩ VR3<br>S R FB Q2 ZMM5259B-7<br>402 kR121% Ω 24.9 kR191% Ω10 10 VC12µF MMBT39041 kR23Ω 100 nF50 VC15 10 kR2439 VΩ 50 V1 C14µF C7<br>2.2 nF<br>250 VAC<br>PI-5991-101210<br>**----- End of picture text -----**<br>


_Figure 8. Schematic of an Isolated, Non-Dimmable, High Power Factor, Universal Input, 7 W LED Driver._ 

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start-up C4 is charged to ~6 V from an internal high-voltage current source tied to the device DRAIN pin.  Once the bias voltage has risen into regulation the operating supply current is provided via R10.  Diode D4 prevents U1 from charging C6 during start-up which would increase the start-up delay time. 

## Feedback 

The bias winding voltage is proportional to the output voltage (set by the turns ratio between the bias and secondary windings).  This allows the output voltage to be monitored without secondary-side feedback components.  Resistor R15 converts the bias voltage into a current which is fed into the FEEDBACK pin of U1.  The internal engine within U1 combines the FEEDBACK pin current, VOLTAGE MONITOR pin current and drain current information to provide a constant output current over a 2:1 output voltage range. 

## Output Rectification 

The transformer secondary winding is rectified by D2 and filtered by C4 and C5.  A Schottky barrier diode was selected for efficiency and the combined value of C4 and C5 were selected to give an acceptable LED ripple current.  For designs where lower ripple is desirable the output capacitance value can be increased.  A small pre-load is provided by R6 which limits the output voltage under no-load conditions. 

a 100 mF BYPASS pin capacitor for all but the LNK4x3 which has only one power setting.  In all cases in order to obtain the best output current tolerance maintain the device temperature below 100 °C 

## Maximum Input Capacitance 

To achieve high power factor, the capacitance used in both the EMI filter and for decoupling the rectified AC (bulk capacitor) must be limited in value.  The maximum value is a function of the output power of the design and reduces as the output power reduces.  For the majority of designs limit the total capacitance to less than 200 nF with a bulk capacitor value of 100 nF.  Film capacitors are recommended compared to ceramic types as they minimize audible noise with operating with leading edge phase dimmers.  Start with a value of 10 nF for the capacitance in the EMI filter and increase in value until there is sufficient EMI margin. 

## REFERENCE Pin Resistance Value Selection 

The LinkSwitch-PH family contains phase dimming devices, LNK403-410, and non-dimming devices, LNK413-420.  The non-dimmable devices use a 24.9 kW ±1% REFERENCE pin resistor in high-line and universal input voltage designs and 49.9 kW ±1% in low-line input voltage designs, for best output current tolerance (over AC input voltage changes).  The dimmable devices use 49.9 kW ±1% to achieve the widest dimming range. 

## Key Application Considerations 

## VOLTAGE MONITOR Pin Resistance Network Selection 

## Power Table 

The data sheet power table (Table 1) represents the minimum and maximum practical continuous output power based on the following conditions: 

For widest AC phase angle dimming range with LNK403-410, use a 4 MW resistor connected to the line voltage peak detector circuit.  Make sure that the resistor’s voltage rating is sufficient for the peak line voltage. If necessary use multiple series connected resistors. 

1. Efficiency of 80% 

2. Device local ambient of 70 °C 

3. Sufficient heat sinking to keep the device temperature below 100 °C 

4. For minimum output power column 

   - Reflected output voltage (VOR) of 120 V 

   - FEEDBACK pin current of 135 mA 

   - BYPASS pin capacitor value of 10 mF 

5. For maximum output power column 

   - Reflected output voltage (VOR) of 65 V 

   - FEEDBACK pin current of 165 mA 

   - BYPASS pin capacitor value of 100 mF (LNK4x3EG = 10 mF) 

Note that input line voltages above 85 VAC do not change the power delivery capability of LinkSwitch-PH devices. 

## Device Selection 

Select the device size by comparing the required output power to the values in Table 1.  For thermally challenging designs, e.g., incandescent lamp replacement, where either the ambient temperature local to the LinkSwitch-PH device is high and/or there is minimal space for heat sinking use the minimum output power column.  This is selected by using a 10 mF BYPASS pin capacitor and results in a lower device current limit and therefore lower conduction losses.  For open frame design or designs where space is available for heat sinking then refer to the maximum output power column.  This is selected by using 

For best line regulation, use a series combination of resistors that equals 3.909 MW connected to the line voltage peak detector.  In addition, connect a 1 MW in series with a 402 kW resistor (1.402 MW total) from the VOLTAGE MONITOR pin to SOURCE pin.  Use 1% tolerance resistors for good accuracy. Line regulation can be further improved by using the PIXls spreadsheet’s fine tuning section.  See the LinkSwitch-PH Application Note for more information. 

## Primary Clamp and Output Reflected Voltage VOR 

A primary clamp is necessary to limit the peak drain to source voltage.  A Zener clamp requires the fewest components and board space and gives the highest efficiency.  RCD clamps are also acceptable however the peak drain voltage should be carefully verified during start-up and output short-circuit as the clamping voltage varies with significantly with the peak drain current. 

For the highest efficiency, the clamping voltage should be selected to be at least 1.5 times the output reflected voltage, VOR, as this keeps the leakage spike conduction time short. When using a Zener clamp in a universal input or high-line only application, a VOR of less than 135 V is recommended to allow for the absolute tolerances and temperature variations of the Zener.  This will ensure efficient operation of the clamp circuit and will also keep the maximum drain voltage below the rated breakdown voltage of the FET.  An RCD (or RCDZ) clamp 

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provides tighter clamp voltage tolerance than a Zener clamp. The RCD clamp is more cost effective than the Zener clamp but requires more careful design to ensure that the maximum drain voltage does not exceed the power FET breakdown voltage. These VOR limits are based on the BVDSS rating of the internal FET, a VOR of 60 V to 100 V is typical for most designs, giving the best PFC and regulation performance. 

## Series Drain Diode 

An ultra-fast or Schottky diode in series with the drain is necessary to prevent reverse current flowing through the device.  The voltage rating must exceed the output reflected voltage, VOR. The current rating should exceed two times the average primary current and have a peak rating equal to the maximum drain current of the selected LinkSwitch-PH device. 

## Line Voltage Peak Detector Circuit 

LinkSwitch-PH devices use the peak line voltage to regulate the power delivery to the output.  A capacitor value of 1 mF to 4.7 mF is recommended to minimize line ripple and give the highest power factor (>0.9), smaller values are acceptable but result in lower PF and higher line current distortion. 

## Operation with Phase Controlled Dimmers 

Dimmer switches control incandescent lamp brightness by not conducting (blanking) for a portion of the AC voltage sine wave. This reduces the RMS voltage applied to the lamp thus reducing the brightness.  This is called natural dimming and the LinkSwitch-PH LNK403-410 devices when configured for dimming utilize natural dimming by reducing the LED current as the RMS line voltage decreases. By this nature, line regulation performance is purposely decreased to increase the dimming range and more closely mimic the operation of an incandescent lamp. Using a 49.9 kW REFERENCE pin resistance selects natural dimming mode operation. 

## Leading Edge Phase Controlled Dimmers 

The requirement to provide flicker-free output dimming with low cost, TRIAC-based, leading edge phase dimmers introduces a number of trade-offs in the design. 

Due to the much lower power consumed by LED based lighting the current drawn by the overall lamp is below the holding current of the TRIAC within the dimmer.  This causes undesirable behaviors such as limited dimming range and/or flickering.  The relatively large impedance the LED lamp presents to the line allows significant ringing to occur due to the inrush current charging the input capacitance when the TRIAC turns on.  This too can cause similar undesirable behavior as the ringing may cause the TRIAC current to fall to zero and turn off. 

To overcome these issues two circuits, the Active Damper and Passive Bleeder, are incorporated.  The drawback of these circuits is increased dissipation and therefore reduced efficiency of the supply so for non-dimming applications these components can simply be omitted. 

Figure 9(a) shows the line voltage and current at the input of a leading edge TRIAC dimmer with Figure 9(b) showing the resultant rectified bus voltage.  In this example, the TRIAC conducts at 90 degrees. 

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PI-5983-060810<br>**----- End of picture text -----**<br>


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350 0.35<br>Voltage<br>250 0.25<br>Current<br>150 —lpf 0.15<br>N<br>50 0.05<br>-150-50 0 .5 enNEF 50 100 150 200 250 300 350 40 0 -0.05-0.15<br>po re ae<br>-250 -0.25<br>po Nf<br>-350 -0.35<br>po [NS]<br>Conduction Angle (°)<br>PI-5984-060810<br>350 0.35<br>Voltage<br>300 0.3<br>250 pO Current {\ 0.25<br>200 0.2<br>2eee<br>150 po 0.15<br>100 0.1<br>eeee<br>50 0.05<br>0 PoFdENALENNe N L3 0<br>0 50 100 150 200 250 300 350 400<br>Conduction Angle (°)<br>Line Voltage (at Dimmer Input) (V) Line Current (Through Dimmer) (A)<br>Rectified Input Voltage (V) Rectified Input Current (A)<br>**----- End of picture text -----**<br>


_Figure 9. (a) Ideal Input Voltage and Current Waveforms for a Leading Edge TRIAC Dimmer at 90° Conduction Angle.  (b) Resultant Waveforms Following Rectification of TRIAC Dimmer Output._ 

Figure 10 shows undesired rectified bus voltage and current with the TRIAC turning off prematurely and restarting. 

If the TRIAC is turning off before the end of the half-cycle erratically or alternate half AC cycles have different conduction angles then flicker will be observed in the LED light due to variations in the output current.  This can be solved by including a bleeder and damper circuit. 

Dimmers will behave differently based on manufacturer and power rating, for example a 300 W dimmer requires less dampening and requires less power loss in the bleeder than a 600 W or 1000 W dimmer due to different drive circuits and TRIAC holding current specifications.  Line voltage also has a significant impact as at high-line for a given output power the input current and therefore TRIAC current is lower but the peak inrush current when the input capacitance charges is higher creating more ringing.  Finally multiple lamps in parallel driven from the same dimmer can introduce more ringing due to the increased capacitance of parallel units.  Therefore when testing dimmer operation verify on a number of models, different line voltages and with both a single driver and multiple drivers in parallel. 

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PI-5985-102810 PI-5986-060810<br>350 0.35 350 0.35<br>300 ie Voltage 0.3 250 Voltage 0.25<br>Current Current<br>250 0.25 150 0.15<br>ian \NGeNeenee Pf |<br>200 0.2 50 0.05<br>eee he 2<br>150 2 Ee ie 0.15 -50 0 ph 50 100 150 200 250 300 350 -0.05<br>100 0.1 -150 -0.15<br>50 n2e See ee 0.05 -250 eeee -0.25<br>0 peal NGNINNie 0 -350 P NGNE -0.35<br>0 50 100 150 200 250 300 350 400<br>Conduction Angle (°)<br>Conduction Angle (°)<br>Rectified Input Voltage (V) Rectified Input Current (A) Dimmer Output Voltage (V) Dimmer Output Current (A)<br>**----- End of picture text -----**<br>


_Figure 11. Ideal Dimmer Output Voltage and Current Waveforms for a Trailing Edge Dimmer at 90° Conduction Angle._ 

_Figure 10. Example of Phase Angle Dimmer Showing Erratic Firing._ 

Start by adding a bleeder circuit.  Add a 0.44 mF capacitor and 510 W 1 W resistor (components in series) across the rectified bus (C11 and R18 in Figure 7).  If this results in satisfactory operation reduce the capacitor value to the smallest that results in acceptable performance to reduce losses and increase efficiency. 

If the bleeder circuit does not maintain conduction in the TRIAC, then add an active damper as shown in Figure 7.  This consists of components R9, R10, R11, R12, D1, Q1, C6, VR2, Q2 in conjunction with R13.  This circuit limits the inrush current that flows to charge C2 when the TRIAC turns on by placing R13 in series for the first 1 ms of the TRIAC conduction.  After approximately 1 ms, Q2 turns on and shorts R13. This keeps the power dissipation on R13 low and allows a larger value to be used during current limiting.  Increasing the delay before Q2 turns on by increasing the values of resistors R9 and R10 will improve dimmer compatibility but cause more power to be dissipated across R13. Monitor the AC line current and voltage at the input of the power supply as you make the adjustments. Increase the delay until the TRIAC operates properly but keep the delay as short as possible for efficiency. 

As a general rule the greater the power dissipated in the bleeder and damper circuits, the more dimmer types will work with the driver. 

## Trailing Edge Phase Controlled Dimmers 

Figure 11 shows the line voltage and current at the input of the power supply with a trailing edge dimmer.  In this example, the dimmer conducts at 90 degrees.  Many of these dimmers use back-to-back connected power FETs rather than a TRIAC to control the load.  This eliminates the holding current issue of TRIACs and since the conduction begins at the zero crossing, high current surges and line ringing are minimized.  Typically these types of dimmers do not require damping and bleeder circuits. 

## Audible Noise Considerations for Use with Leading Edge Dimmers 

Noise created when dimming is typically created by the input capacitors, EMI filter inductors and the transformer.  The input capacitors and inductors experience high di/dt and dv/dt every AC half-cycle as the TRIAC fires and an inrush current flows to charge the input capacitance.  Noise can be minimized by selecting film vs ceramic capacitors, minimizing the capacitor value and selecting inductors that are physically short and wide. 

The transformer may also create noise which can be minimized by avoiding cores with long narrow legs (high mechanical resonant frequency).  For example, RM cores produce less audible noise than EE cores for the same flux density. Reducing the core flux density will also reduce the noise. Reducing the maximum flux density (BM) to 1500 Gauss usually eliminates any audible noise but must be balanced with the increased core size needed for a given output power. 

## Thermal and Lifetime Considerations 

Lighting applications present thermal challenges to the driver. In many cases the LED load dissipation determines the working ambient temperature experienced by the drive so thermal evaluation should be performed with the driver inside the final enclosure.  Temperature has a direct impact on driver and LED lifetime.  For every 10 °C rise in temperature, component life is reduced by a factor of 2. Therefore it is important to properly heat sink and verify the operating temperatures of all devices. 

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## Layout Considerations 

## Primary-Side Connections 

Use a single point (Kelvin) connection at the negative terminal of the input filter capacitor for the SOURCE pin and bias returns. This improves surge capabilities by returning surge currents from the bias winding directly to the input filter capacitor.  The BYPASS pin capacitor should be located as close to the BYPASS pin and connected as close to the SOURCE pin as possible.  The SOURCE pin trace should not be shared with the main power FET switching currents.  All FEEDBACK pin 

components that connect to the SOURCE pin should follow the same rules as the BYPASS pin capacitor.  It is critical that the main power FET switching currents return to the bulk capacitor with the shortest path as possible.  Long high current paths create excessive conducted and radiated noise. 

## Secondary-Side Connections 

The output rectifier and output filter capacitor should be as close as possible.  The transformer’s output return pin should have a short trace to the return side of the output filter capacitor. 

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Bulk Capacitor Clamp LNK403EG<br>FL1<br>6<br>1<br>Input EMI Filter R14<br>2<br>VR1<br>R2<br>Transformer<br>D1<br>L3 C3 5<br>U1<br>ey| oe | C9 A axe C8 —@ OC 4<br>3<br>F1 T1<br>L1 C2<br>L2<br>L RV1 C7<br>N C12<br>Oo he \ oO<br>C5<br>R3 VR3 Output<br>C4 Filter<br>R16 R24 Capacitors<br>mS) oc<br>C14 V<br>Copper Area for R10 C6<br>Heat Sinking RES D8  5 V<br>BYPASS Pin<br>Capacitor PI-5987-060110<br>R15<br>C15 FL3<br>R23<br>FL2<br>**----- End of picture text -----**<br>


_Figure 12. RD-193 7 W Layout Example, Top Layer._ 

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R13 D6<br>R12<br>D1<br>D7<br>| i |<br>D5<br>00 I Ho sl Oo | o<br>D1 R17 R5<br>S<br>O e.. 209 o Ia, C0<br>R20 C13 D3<br>S R7<br>R4<br>Oo ra BR1 je VR2 es 0 ap Output<br>Rectifier<br>Bridge Rectifier R9 D2<br>6 F1 on a af<br>B3 R18 R6<br>° °<br>vam ie<br>Active Damper<br>MOSFET<br>PI-5988-060110<br>R19<br>**----- End of picture text -----**<br>


_Figure 13. RD-193 7 W Layout Example, Bottom Layer._ 

## Quick Design Checklist 

## Maximum Drain Voltage 

Verify that the peak VDS does not exceed 725 V under all operating conditions including start up and fault conditions. 

## Maximum Drain Current 

Measure the peak drain current under all operation conditions including start up and fault conditions.  Look for signs of transformer saturation (usually occurs at highest operating ambient temperatures).  Verify that the peak current is less that stated for the Absolute Maximum Rating in the data sheet. 

## Thermal Check 

At maximum output power, both minimum and maximum line voltage and ambient temperature; verify that temperature specifications are not exceeded for the LinkSwitch-PH, transformer, output diodes, output capacitors and drain clamp components. 

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## **Absolute Maximum Ratings[(1,4)]** 

|DRAIN Pin Peak Current(5): LNK403, LNK413 ...................1.37 A|Lead Temperature(3)....................................................... .........260°C|
|---|---|
|LNK404, LNK414 ...................2.08 A|Storage Temperature …………………. .................. -65 to 150 °C|
|LNK405, LNK415 ...................2.72 A|Operating Junction Temperature(2).........................-40 to 150 °C|
|LNK406, LNK416 .................. 4.08 A||
|LNK407,  LNK417 .................. 5.44 A|Notes:|
|LNK408, LNK418 .................. 6.88 A|1. All voltages referenced to SOURCE, TA= 25°C.|
|LNK409, LNK419 ................... 7.73 A|2. Normally limited by internal circuitry.|
|LNK410, LNK420 .................. 9.00 A<br>DRAIN Pin Voltage ……………………… ................  -0.3 to 725 V|3. 1/16 in. from case for 5 seconds.<br>4.  Absolute Maximum Ratings specifed may be applied, one|
|BYPASS Pin Voltage ……………………… .................  -0.3 to 9 V|at a time without causing permanent damage to the|
|BYPASS Pin Current ……………………… .....................  100 mA|product. Exposure to Absolute Maximum Ratings for|
|VOLTAGE MONITOR Pin Voltage …....................………-0.3 to 9 V|extended periods of time may affect product reliability.|
|FEEDBACK Pin Voltage …….. ..................................  -0.3 to 9 V|5.  Peak DRAIN current is allowed while the DRAIN voltage is|
|REFERENCE Pin Voltage .......................................... -0.3 to 9 V|simultaneously less than 400 V. See also Figure 17.|



## **Thermal Resistance** 

|**Thermal Resistance**|**Thermal Resistance**|**Thermal Resistance**|**Thermal Resistance**|**Thermal Resistance**|**Thermal Resistance**|**Thermal Resistance**|**Thermal Resistance**|**Thermal Resistance**|
|---|---|---|---|---|---|---|---|---|
|Thermal Resistance: eSIP Package:<br>(qJA) ....................................................105°C/W(1)<br>(qJC) .....................................................2°C/W(2)<br>Notes:<br>1.  Free Standing with no heat sink.<br>2.  Measured at back surface tab.|||||||||
|**Parameter**|**Symbol**|**Conditions**<br>SOURCE = 0 V; TJ= -20 °C to 125 °C<br>(Unless Otherwise Specifed)|||**Min**|**Typ**|**Max**|**Units**|
|**Control Functions**|||||||||
|**Switching Frequency**|fOSC|TJ= 25 °C||Average|62|66|70|kHz|
|||||Peak-Peak Jitter||9|||
|**Frequency Jitter**<br>**Modulation Rate**|fM|TJ= 25 °C<br>See Note B||||1||kHz|
|**BYPASS Pin**<br>**Charge Current**|ICH1|VBP= 0 V,<br>TJ= 25 °C|LNK403, LNK413||-5.0|-4.2|-3.4|mA|
||||LNK404, LNK414||-9.6|-8.0|-6.4||
||||LNK405-410,<br>LNK415-420||-17|-12|-8.8||
||ICH2|VBP= 5 V,<br>TJ= 25 °C|LNK403, LNK413||-1.6|-1.2|-0.6||
||||LNK404, LNK414||-4.2|-3.5|-2.8||
||||LNK405-410,<br>LNK415-420||-9|-6.8|-4.6||
|**Charging Current**<br>**Temperature Drift**||See Note A||||0.5||%/°C|
|**BYPASS Pin Voltage**|VBP|0 °C < TJ< 100 °C|||5.7|5.9|6.1|V|
|**BYPASS Pin Voltage**<br>**Hysteresis**|VBP(H)|0 °C < TJ< 100 °C||||0.85||V|
|**BYPASS Pin**<br>**Shunt Voltage**|VBP(SHUNT)|IBP= 2 mA<br>0 °C < TJ< 100 °C|||6.0|6.4|6.7|V|
|**Soft-Start Time**|tSOFT|TJ= 25 °C<br>VBP= 5.9 V|||40|||ms|



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**----- Start of picture text -----**<br>
Conditions<br>Parameter Symbol SOURCE = 0 V; T(Unless Otherwise Specified)J = -20 °C to 125 °C  Min Typ Max Units<br>Control Functions (cont.)<br>ICD2 0 °C < TFET Not SwitchingJ < 100 °C 0.5 0.85 1.2<br>Drain Supply Current mA<br>ICD1 FET Switching at f0 °C < TJ < 100 °C OSC 0.9 1.5 2.25<br>VOLTAGE MONITOR Pin<br>Line Brown-InThreshold Current IUV+ TJ = 25 °C RRRR = 24.9 k = 49.9 kWW 21.022.8 22.524.5 24.026.2 mA<br>Line Brown-OutThreshold Current IUV- TJ = 25 °C RRRR = 24.9 k = 49.9 kWW 18.515.0 mA<br>Line Brown-In/OutHysteresis IUV(H) TJ = 25 °C RRRR = 24.9 k = 49.9 kWW 15 9.44 mA<br>Line Overvoltage  TJ = 25 °C Threshold  107 112 117<br>Threshold IOV RR = 24.9 kW mA<br>RR = 49.9 kW Hysteresis 4<br>VOLTAGE MONITOR Pin Voltage VV 0 °C < TIUV- < IJ < 100 °C V < IOV 2.75 3.0 3.25 V<br>VOLTAGE MONITOR Pin Short-Circuit Current IV(SC) TVJ = 25 °CV = 5 V 170 190 210 mA<br>Remote ON/OFF<br>Threshold VV(REM) TJ = 25 °C 0.5 V<br>FEEDBACK Pin<br>FEEDBACK Pin Current<br>at Onset of Maximum  IFB(DCMAXR)  0 °C < TJ < 100 °C 85 mA<br>Duty Cycle<br>FEEDBACK Pin Current<br>Skip Cycle Threshold IFB(SKIP)  0 °C < TJ < 100 °C 220 mA<br>Maximum Duty Cycle DCMAX IFB(DCMAXR)  0 °C < T< IJ < 100 °CFB < IFB(SKIP) 90 99.9 %<br>FEEDBACK Pin Voltage VFB 0 °C <IFB = 150 TJ < 100 °C mA 2.08 2.40 2.62 V<br>FEEDBACK Pin  Short-Circuit Current IFB(SC) TVJ = 25 °CFB = 5 V 320 400 480 mA<br>DC10 IFB = IFB(AR), TJ = 25 °C, See Note B 10<br>Duty Cycle Reduction DC40 IFB = 40 mA, TJ = 25 °C  20 %<br>DC60 IFB = 60 mA, TJ = 25 °C 36<br>Auto-Restart<br>  Auto-Restart ON-Time tAR VTBPJ = 25 °C = 5.9 V 40 ms<br>Auto-Restart<br>Duty Cycle DCAR TJ = 25 °C 3 %<br>**----- End of picture text -----**<br>


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|**Parameter**|**Symbol**|**Conditions**<br>SOURCE = 0 V; TJ= -20 °C to 125 °C<br>(Unless Otherwise Specifed)|**Conditions**<br>SOURCE = 0 V; TJ= -20 °C to 125 °C<br>(Unless Otherwise Specifed)|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|---|
|**Auto-Restart(cont.)**||||||||
|**SOA Minimum Switch**<br>**ON-Time**|tON(SOA)|TJ= 25 °C<br>See Note B||||1.75|ms|
|**FEEDBACK Pin**<br>**Current During**<br>**Auto-Restart**|IFB(AR)|0 °C < TJ< 100 °C||||17.5|mA|
|**REFERENCE Pin**||||||||
|**REFERENCE Pin**<br>**Voltage**|VR|RR= 24.9 kW<br>0 °C < TJ< 100 °C||1.215|1.245|1.275|V|
|**REFERENCE Pin**<br>**Current**|IR|||48.45|49.70|50.95|mA|
|**Current Limit/Circuit Protection**||||||||
|**Full Power**<br>**Current Limit**<br>**(CBP = 100**m**F)**|ILIMIT(F)<br>TJ= 25 °C|di/dt = 174 mA/ms|LNK404, LNK414|1.02||1.18|A|
|||di/dt = 174 mA/ms|LNK405, LNK415|1.24||1.44||
|||di/dt = 225 mA/ms|LNK406, LNK416|1.50||1.74||
|||di/dt = 320 mA/ms|LNK407, LNK417|1.77||2.06||
|||di/dt = 350 mA/ms|LNK408, LNK418|2.39||2.77||
|||di/dt = 426 mA/ms|LNK409, LNK419|3.26||3.79||
|||di/dt = 1060 mA/ms|LNK410, LNK420|4.90||5.70||
|**Reduced Power**<br>**Current Limit**<br>**(CBP = 10**m**F)**|ILIMIT(R)<br>TJ= 25 °C|di/dt = 133 mA/ms|LNK403, LNK413|0.75||0.85|A|
|||di/dt = 195 mA/ms|LNK404, LNK414|0.81||0.94||
|||di/dt = 192 mA/ms|LNK405, LNK415|1.00||1.16||
|||di/dt = 240 mA/ms|LNK406, LNK416|1.19||1.38||
|||di/dt = 335 mA/ms|LNK407, LNK417|1.42||1.66||
|||di/dt = 380 mA/ms|LNK408, LNK418|1.73||2.01||
|||di/dt = 466 mA/ms|LNK409, LNK419|2.35||2.73||
|||di/dt = 1060 mA/ms|LNK410, LNK420|4.90||5.70||
|**Minimum ON-Time**<br>**Pulse**|tLEB+ tIL(D)|TJ= 25 °C||300|500|700|ns|
|**Leading Edge**<br>**Blanking Time**|tLEB|TJ= 25 °C<br>See Note B||150||500|ns|
|**Current Limit Delay**|tIL(D)|TJ= 25 °C<br>See Note B|||150||ns|
|**Thermal Shutdown**<br>**Temperature**||||135|142|150|°C|
|**Thermal Shutdown**<br>**Hysteresis**|||||75||°C|
|**BYPASS Pin Power-Up**<br>**Reset Threshold**<br>**Voltage**|VBP(RESET)|0 °C < TJ< 100 °C||2.25|3.5|4.25|V|



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|**Parameter**|**Symbol**|**Conditions**<br>SOURCE = 0 V; TJ= -20 °C to 125 °C<br>(Unless Otherwise Specifed)|**Conditions**<br>SOURCE = 0 V; TJ= -20 °C to 125 °C<br>(Unless Otherwise Specifed)|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|---|
|**Output**||||||||
|**ON-State Resistance**|RDS(ON)|LNK403, LNK413<br>ID= 100 mA|TJ= 25 °C||9.00|10.35|W|
||||TJ= 100 °C||13.50|15.5||
|||LNK404, LNK414<br>ID= 100 mA|TJ= 25 °C||5.40|6.25||
||||TJ= 100 °C||8.35|9.7||
|||LNK405, LNK415<br>ID= 150 mA|TJ= 25 °C||4.10|4.7||
||||TJ= 100 °C||6.30|7.3||
|||LNK406, LNK416<br>ID= 150 mA|TJ= 25 °C||2.80|3.2||
||||TJ= 100 °C||4.10|4.75||
|||LNK407, LNK417<br>ID= 200 mA|TJ= 25 °C||2.00|2.3||
||||TJ= 100 °C||3.10|3.6||
|||LNK408, LNK418<br>ID= 250 mA|TJ= 25 °C||1.60|1.85||
||||TJ= 100 °C||2.40|2.8||
|||LNK409, LNK419<br>ID= 350 mA|TJ= 25 °C||1.40|1.6||
||||TJ= 100 °C||2.10|2.45||
|||LNK410, LNK420<br>ID= 550 mA|TJ= 25 °C||1.05|1.2||
||||TJ= 100 °C||1.6|1.85||
|**OFF-State Drain**<br>**Leakage Current**|IDSS|VBP= 6.4 V<br>VDS= 560 V<br>TJ= 100°C||||50|mA|
|**Breakdown Voltage**|BVDSS|VBP= 6.4 V<br>TJ= 25 °C||725|||V|
|**Minimum Drain**<br>**Supply Voltage**||TJ< 100 °C||36|||V|
|**Rise Time**|tR|Measured in a Typical Flyback|||100||ns|
|**Fall Time**|tF||||50||ns|



## NOTES: 

A. For specifications with negative values, a negative temperature coefficient corresponds to an increase in magnitude with increasing temperature and a positive temperature coefficient corresponds to a decrease in magnitude with increasing temperature. 

B. Guaranteed by characterization. Not tested in production. 

**16** 

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## Typical Performance Characteristics 

**==> picture [187 x 407] intentionally omitted <==**

**----- Start of picture text -----**<br>
10000<br>Scaling Factors:<br>LNK403, LNK413   0.18<br>LNK404, LNK414   0.28<br>LNK405, LNK415   0.38<br>LNK406, LNK416   0.56<br>1000 LNK407, LNK417   0.75<br>LNK408, LNK418   1.00<br>LNK409, LNK419   1.16<br>LNK410, LNK420   1.55<br>100<br>0<br>0 100 200 300 400 500 600<br>DRAIN Pin Voltage (V)<br>Figure 14.   Drain Capacitance vs. Drain Pin Voltage.<br>5<br>4<br>3<br>Scaling Factors:<br>LNK403, LNK413   0.18<br>LNK404, LNK414   0.28<br>2 LNK405, LNK415   0.38<br>LNK406, LNK416   0.56<br>LNK407, LNK417   0.75<br>LNK408, LNK418   1.00<br>1 LNK409, LNK419   1.16<br>LNK410, LNK420   1.55<br>LNK408 TLNK408 TCASE CASE = 25 = 100 °C°C<br>0<br>0 2 4 6 8 10 12 14 16 18 20<br>DRAIN Voltage (V)<br>PI-5992-032912<br>DRAIN Capacitance (pF)<br>PI-5994-032912<br>DRAIN Current (A)<br>**----- End of picture text -----**<br>


_Figure 16.   Drain Current vs. Drain Voltage._ 

**==> picture [186 x 178] intentionally omitted <==**

**----- Start of picture text -----**<br>
300<br>Scaling Factors:<br>LNK403, LNK413   0.18<br>LNK404, LNK414   0.28<br>LNK405, LNK415   0.38<br>LNK406, LNK416   0.56<br>200 LNK407, LNK417   0.75<br>LNK408, LNK418   1.00<br>LNK409, LNK419   1.16<br>LNK410, LNK420   1.55<br>100<br>0<br>0 100 200 300 400 500 600 700<br>DRAIN Voltage (V)<br>PI-5993-032912<br>Power (mW)<br>**----- End of picture text -----**<br>


_Figure 15.   Power vs. Drain Voltage._ 

**==> picture [198 x 195] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.2<br>1<br>0.8<br>0.6<br>0.4<br>0.2<br>0<br>0 100 200 300 400 500 600 700 800<br>DRAIN Voltage (V)<br>PI-6010-060410<br>DRAIN Current<br>(Normalized to Absolute Maximum Rating)<br>**----- End of picture text -----**<br>


_Figure 17.   Maximum Allowable Drain Current vs. Drain Voltage._ 

**17** 

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**LNK403-410/413-420** 

## **eSIP-7C (E Package)** 

**==> picture [513 x 489] intentionally omitted <==**

**----- Start of picture text -----**<br>
C<br>2<br>A 0.403 (10.24) 0.081 (2.06) 0.264 (6.70)<br>0.397 (10.08) 0.077 (1.96) Ref.<br>B<br>Detail A<br>2<br>0.325 (8.25) 0.290 (7.37)<br>0.320 (8.13) Ref. 0.198 (5.04) Ref.<br>0.519 (13.18)<br>Ref.<br>Pin #1 0.140 (3.56) 0.016 (0.41) 0.207 (5.26)<br>I.D. 0.120 (3.05) Ref. 0.187 (4.75)<br>0.070 (1.78) Ref. 0.047 (1.19) 3 4<br>0.050 (1.27) 3 0.016 (0.40.011 (0.28)1) 6× 0.118 (3.00) 0.100 (2.54) 0.010 M  0.25 M  C A B0.033 (0.84)0.028 (0.71) 6×<br>0.020 M  0.51 M  C<br>FRONT VIEW SIDE VIEW BACK VIEW<br>10 °  Ref. 0.100 (2.54)<br>All Around<br>0.021 (0.53) 0.060 (1.52) 0.020 (0.50) 0.050 (1.27)<br>0.019 (0.48) Ref. 0.050 (1.27)<br>PIN 1<br>0.048 (1.22) 0.059 (1.50) 0.155 (3.93)<br>0.378 (9.60) 0.046 (1.17)<br>Ref. 0.019 (0.48) Ref.<br>0.023 (0.58) PIN 7<br>END VIEW<br>0.027 (0.70)<br>0.059 (1.50)<br>Notes:<br>1.  Dimensioning and tolerancing per ASME Y14.5M-1994.    DETAIL A<br>2.  Dimensions noted are determined at the outermost  0.100 (2.54) 0.100 (2.54)<br>     extremes of the  plastic body exclusive of mold flash,<br>     tie bar burrs, gate burrs, and interlead flash, but including MOUNTING HOLE PATTERN<br>     any mismatch between the top and bottom of the plastic (not to scale)<br>     body. Maximum mold protrusion is 0.007 [0.18] per side.<br>3.  Dimensions noted are inclusive of plating thickness.<br>4.  Does not include inter-lead flash or protrusions.<br>5.  Controlling dimensions in inches (mm).<br>PI-4917-061510<br>**----- End of picture text -----**<br>


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**==> picture [518 x 420] intentionally omitted <==**

**----- Start of picture text -----**<br>
eSIP-7F (L Package)<br>2 C<br>A 0.403 (10.24) 0.081 (2.06)<br>0.397 (10.08) 0.077 (1.96) 0.264 (6.70) Ref.<br>B<br>Detail A<br>2 0.325 (8.25) 0.290 (7.37) 0.198 (5.04) Ref.<br>0.320 (8.13) 3 Ref.<br>0.490 (12.45) Ref.<br>0.016 (0.41) 6×<br>0.011 (0.28)<br>0.020 M  0.51 M  C   0.173 (4.40)<br>1 7 0.163 (4.15) 7 1<br>0.084 (2.14)<br>Pin 1 I.D.<br>0.089 (2.26)<br>0.047 (1.19) Ref. 0.079 (2.01)<br>0.070 (1.78) Ref.<br>0.050 (1.27) 0.100 (2.54) 3 4<br>0.129 (3.28) 0.033 (0.84) 6×<br>0.122 (3.08) 0.028 (0.71)<br>0.010 M  0.25 M  C A B<br>BOTTOM VIEW SIDE VIEW TOP VIEW<br>Exposed pad hidden Exposed pad up<br>Notes:<br>0.060 (1.52) Ref. 1 7 0.021 (0.53) 0.020 (0.50) 1.  Dimensioning and tolerancing per ASME      Y14.5M-1994.<br>0.019 (0.48)<br>2.  Dimensions noted are determined at the<br>     outermost extremes of the plastic body<br>     exclusive of mold flash, tie bar burrs, gate<br>     burrs, and interlead flash, but including<br>0.019 (0.48) Ref. 0.023 (0.58)      any mismatch between the top and bottom<br>0.378 (9.60) 0.048 (1.22)      of the plastic body. Maximum mold<br>Ref. 0.046 (1.17) 0.027 (0.70)      protrusion is 0.007 [0.18] per side.<br>3.  Dimensions noted are inclusive of plating<br>     thickness.<br>END VIEW DETAIL A (Not drawn to scale) 4.  Does not include inter-lead flash or<br>     protrusions.<br>5.  Controlling dimensions in inches (mm).<br>PI-5204-061510<br>**----- End of picture text -----**<br>


## **Part Ordering Information** 

**==> picture [314 x 92] intentionally omitted <==**

**----- Start of picture text -----**<br>
 • LinkSwitch Product Family<br> • PH Series Number<br> • Package Identifier<br>E  eSIP-7C<br>L  eSIP-7F<br> • Package Material<br>LNK   409    E   G   G  GREEN: Halogen Free and RoHS Compliant<br>**----- End of picture text -----**<br>


**19** 

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|**Revision**|**Notes**|**Date**|
|---|---|---|
|A<br>B<br>C<br>D<br>E<br>E|Initial Release.<br>Updated Power Table.<br>Added Non-Dimming Parts and Related Text.<br>Added L Package.<br>Added new LNK410 and LNK420 Parts.<br>Updated Output Power Table values for LNK410/420. Updated Parameter Table values for LNK410/420.|06/09/10<br>08/06/10<br>11/10<br>08/11<br>12/11<br>03/12|



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