# MEMS Accelerometer, 3-Axis, ± 2g, ± 8g, X, Y, Z, I2C, SPI, LGA, 14 Pins, 18mg/digit, 72mg/digit
**URL**: https://novapart.co/products/LIS302DL/mems-accelerometer-3-axis-2g-8g-x-y-z-i2c-spi-lga
**SKU**: LIS302DL
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - ICs || IC Sensors || MEMS Accelerometers
**Price**: €1.2900
**Stock**: 10+
## Description
MEMS Sensor Output:Digital; Measurement Axis:X, Y, Z; Acceleration Range:± 2g, ± 8g; Supply Voltage Min:2.16V; Supply Voltage Max:3.6V; Sensor Case Style:LGA; No. of Pins:14Pins; Sensiti
## Specifications
| Parameter | Value |
|---|---|
| No. Of Pins | 14Pins |
| Sensing Axis | X, Y, Z |
| Product Range | - |
| Qualification | - |
| Sensitivity Max | 19.8mg/digit, 79.2mg/digit |
| Sensitivity Min | 16.2mg/digit, 64.8mg/digit |
| Sensitivity Typ | 18mg/digit, 72mg/digit |
| Output Interface | I2C, SPI |
| Sensor Case Style | LGA |
| Mems Sensor Output | Digital |
| Supply Voltage Max | 3.6V |
| Supply Voltage Min | 2.16V |
| Sensor Case / Package | LGA |
| Operating Temperature Max | 85°C |
| Operating Temperature Min | -40°C |
| Sensing Range - Accelerometer | ± 2g, ± 8g |
## Datasheet
📄 [Download PDF](https://novapart.co/datasheet/farnell:1435588/)
**LIS302DL** MEMS motion sensor
**==> picture [61 x 39] intentionally omitted <==**
## 3-axis - ± 2g/± 8g smart digital output “piccolo” accelerometer
## **Feature**
- 2.16 V to 3.6 V supply voltage
- 1.8 V compatible IOs
- <1 mW power consumption
- ± 2g/± 8g dynamically selectable full-scale
- I[2] C/SPI digital output interface
**==> picture [79 x 54] intentionally omitted <==**
**LGA 14 (3x5x0.9mm)**
- Programmable multiple interrupt generator
- Click and double click recognition
- Embedded high pass filter
- Embedded self test
The LIS302DL has dynamically user selectable full scales of ± 2g/± 8g and it is capable of measuring accelerations with an output data rate of 100 Hz or 400 Hz.
- 10000g high shock survivability
- ECOPACK® RoHS and “Green” compliant (see _Section 9_ )
## **Description**
The LIS302DL is an ultra compact low-power three axes linear accelerometer. It includes a sensing element and an IC interface able to provide the measured acceleration to the external world through I[2] C/SPI serial interface.
The sensing element, capable of detecting the acceleration, is manufactured using a dedicated process developed by ST to produce inertial sensors and actuators in silicon.
The IC interface is manufactured using a CMOS process that allows to design a dedicated circuit which is trimmed to better match the sensing element characteristics.
A self-test capability allows the user to check the functioning of the sensor in the final application.
The device may be configured to generate inertial wake-up/free-fall interrupt signals when a programmable acceleration threshold is crossed at least in one of the three axes. Thresholds and timing of interrupt generators are programmable by the end user on the fly.
The LIS302DL is available in plastic Thin Land Grid Array package (TLGA) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C.
The LIS302DL belongs to a family of products suitable for a variety of applications:
- Free-fall detection
- Motion activated functions
- Gaming and virtual reality input devices
- Vibration monitoring and compensation
**Table 1. Device summary**
|**Part number**|**Temp range,**°**C**|**Package**|**Packing**|
|---|---|---|---|
|LIS302DL|-40 to +85|LGA|Tray|
|LIS302DLTR|-40 to +85|LGA|Tape and reel ( 5000 pcs/reel )|
|LIS302DLTR8|-40 to +85|LGA|Tape and reel ( 8000 pcs/reel )|
October 2008
1/42
Rev 4
_www.st.com_
**Contents**
**LIS302DL**
## **Contents**
|**1**|**Block**|**diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8**|
|---|---|---|
||1.1|Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
||1.2|Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|**2**|**Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10**||
||2.1|Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10|
||2.2|Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
||2.3|Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|||2.3.1
SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|||2.3.2
I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
||2.4|Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
||2.5|Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|||2.5.1
Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|||2.5.2
Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|||2.5.3
Self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|||2.5.4
Click and double click recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|**3**|**Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16**||
||3.1|Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
||3.2|IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
||3.3|Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
|**4**|**Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17**||
||4.1|Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17|
|**5**|**Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18**||
||5.1|I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|||5.1.1
I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
||5.2|SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|||5.2.1
SPI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22|
|||5.2.2
SPI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22|
|||5.2.3
SPI Read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
2/42
|**LIS302DL**||**Contents**|
|---|---|---|
|**6**|**Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24**||
|**7**|**Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26**||
||7.1|WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
||7.2|CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
||7.3|CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27|
||7.4|CTRL_REG3 [Interrupt CTRL register] (22h) . . . . . . . . . . . . . . . . . . . . . . 28|
||7.5|HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
||7.6|STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
||7.7|OUT_X (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
||7.8|OUT_Y (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
||7.9|OUT_Z (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
||7.10|FF_WU_CFG_1 (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
||7.11|FF_WU_SRC_1 (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
||7.12|FF_WU_THS_1 (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
||7.13|FF_WU_DURATION_1 (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
||7.14|FF_WU_CFG_2 (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
||7.15|FF_WU_SRC_2 (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
||7.16|FF_WU_THS_2 (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
||7.17|FF_WU_DURATION_2 (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
||7.18|CLICK_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
||7.19|CLICK_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
||7.20|CLICK_THSY_X (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
||7.21|CLICK_THSZ (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
||7.22|CLICK_TimeLimit (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
||7.23|CLICK_Latency (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
||7.24|CLICK_Window (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|**8**|**Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 37**||
||8.1|Mechanical characteristics at 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
||8.2|Mechanical characteristics derived from measurement in the -40°C to +85°C|
|||temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
||8.3|Electro-mechanical characteristics at 25°C . . . . . . . . . . . . . . . . . . . . . . . 39|
3/42
|**Contents**|**LIS302DL**|
|---|---|
|**9**|**Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40**|
|**10**|**Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41**|
4/42
**LIS302DL**
**List of tables**
## **List of tables**
|Table|1.|Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1|
|---|---|---|
|Table|2.|Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
|Table|3.|Mechanical characteristics|
|||(All the parameters are specified @ Vdd=2.5V, T = 25°C unless otherwise noted) . . . . . . 10|
|Table|4.|Electrical characteristics|
|||(All the parameters are specified @ Vdd=2.5V, T= 25°C unless otherwise noted) . . . . . . 11|
|Table|5.|SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|Table|6.|I2C slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
|Table|7.|Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|Table|8.|Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|Table|9.|Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|Table|10.|SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|Table|11.|Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|Table|12.|Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|Table|13.|Transfer when Master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 20|
|Table|14.|ransfer when master is receiving (reading). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|Table|15.|Multiple bytes of data from slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|Table|16.|Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|Table|17.|WHO_AM_I (0Fh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|Table|18.|CTRL_REG1 (20h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|Table|19.|CTRL_REG1 (20h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|Table|20.|CTRL_REG2 (21h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27|
|Table|21.|CTRL_REG2 (21h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27|
|Table|22.|High pass filter cut-off frequency configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|Table|23.|CTRL_REG3 (22h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|Table|24.|CTRL_REG3 (22h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|Table|25.|CTRL_REG3 (22h) truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|Table|26.|STATUS_REG (27h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|Table|27.|STATUS_REG (27h) register desription. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|Table|28.|OUT_X (29h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|Table|29.|OUT_Y (2Bh) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|Table|30.|OUT_Z (2Dh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|Table|31.|FF_WW_CFG_1 (30h) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|Table|32.|FF_WW_CFG_1(30h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|Table|33.|FF_WU_SRC_1 (31h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|Table|34.|FF_WU_SRC_1 (31h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|Table|35.|FF_WU_THS_1 (32h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|Table|36.|FF_WU_THS_1 (32h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|Table|37.|FF_WU_DURATION_1 (33h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
|Table|38.|FF_WU_DURATION_1 (33h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
|Table|39.|FF_WU_CFG_2 (34h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
|Table|40.|FF_WU_CFG_2 (34h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
|Table|41.|FF_WU_SRC_2 (35h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
|Table|42.|FF_WU_SRC_2 (35h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
|Table|43.|FF_WU_THS_2 (36h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
|Table|44.|FF_WU_THS_2 (36h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
|Table|45.|FF_WU_DURATION_2 (37h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
|Table|46.|FF_WU_DURATION_2 (37h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
5/42
**LIS302DL**
**List of tables**
|Table|47.|CLICK_CFG (38h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
|---|---|---|
|Table|48.|CLICK_CFG (38h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
|Table|49.|CLICK_CFG (38h) truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
|Table|50.|CLICK_SRC (39h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
|Table|51.|CLICK_SRC (39h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|Table|52.|CLICK_THSY_X (3Bh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|Table|53.|CLICK_THSY_X (3Bh) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|Table|54.|CLICK_THSZ (3Ch) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|Table|55.|CLICK_THSZ (3Ch) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|Table|56.|CLICK_TimeLimit (3Dh) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|Table|57.|CLICK_Latency (3Eh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|Table|58.|CLICK_Window (3Fh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|Table|59.|Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41|
6/42
**LIS302DL**
**List of figures**
## **List of figures**
|Figure|1.|Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|---|---|---|
|Figure|2.|Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|Figure|3.|SPI slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
|Figure|4.|I2C Slave timing diagram (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|Figure|5.|LIS302DL electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
|Figure|6.|Read & write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|Figure|7.|SPI Read protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21|
|Figure|8.|Multiple bytes SPI Read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21|
|Figure|9.|SPI Write protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21|
|Figure|10.|Multiple bytes SPI Write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22|
|Figure|11.|SPI Read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22|
|Figure|12.|X axis zero-g level at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|Figure|13.|X axis sensitivity at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|Figure|14.|Y axis zero-g level at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|Figure|15.|Y axis sensitivity at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|Figure|16.|Z axis zero-g level at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|Figure|17.|Z axis sensitivity at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|Figure|18.|X axis zero-g level change vs. temperature at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
|Figure|19.|X axis sensitivity change vs. temperature at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
|Figure|20.|Y axis zero-g level change vs. temperature at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
|Figure|21.|Y axis sensitivity change vs. temperature at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
|Figure|22.|Z axis zero-g level change vs. temperature at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
|Figure|23.|Z axis sensitivity change vs. temperature at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
|Figure|24.|Current consumption in normal mode at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
|Figure|25.|Current consumption in power down mode at 2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
|Figure|26.|LGA 14: mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39|
7/42
**LIS302DL**
**Block diagram and pin description**
## **1 Block diagram and pin description**
## **1.1 Block diagram**
## **Figure 1. Block diagram**
**==> picture [397 x 126] intentionally omitted <==**
**----- Start of picture text -----**
X+
Y+ CHARGE
Z+ AMPLIFIER CS
I [2] C SCL/SPC
A/D
a MUX CONVERTER CONTROL LOGIC SDA/SDO/SDI
Z- SPI SDO
Y-
X-
CONTROL LOGIC INT 1
SELF TEST REFERENCE TRIMMING CLOCK &
CIRCUITS INTERRUPT GEN. INT 2
**----- End of picture text -----**
## **1.2 Pin description**
## **Figure 2. Pin connection**
**==> picture [275 x 101] intentionally omitted <==**
**----- Start of picture text -----**
Z 1 6
1
Y X
13
6
8
13 8
TOP VIEW BOTTOM VIEW
**----- End of picture text -----**
8/42
**LIS302DL**
**Block diagram and pin description**
**Table 2. Pin description**
|**Pin#**|**Name**|**Function**|
|---|---|---|
|1|Vdd_IO|Power supply for I/O pins|
|2|GND|0V supply|
|3|Reserved|Connect to Vdd|
|4|GND|0V supply|
|5|GND|0V supply|
|6|Vdd|Power supply|
|7|CS|SPI enable
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)|
|8|INT 1|Inertial interrupt 1|
|9|INT 2|Inertial interrupt 2|
|10|GND|0V supply|
|11|Reserved|Connect to Gnd|
|12|SDO|SPI Serial Data Output
I2C less significant bit of the device address|
|13|SDA
SDI
SDO|I2C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)|
|14|SCL
SPC|I2C Serial Clock (SCL)
SPI Serial Port Clock (SPC)|
9/42
**LIS302DL**
**Mechanical and electrical specifications**
## **2 Mechanical and electrical specifications**
## **2.1 Mechanical characteristics**
## **Table 3. Mechanical characteristics[(1)]**
(All the parameters are specified @ Vdd=2.5 V, T = 25°C unless otherwise noted)
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.(2)**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|FS|Measurement range(3)|FS bit set to 0|±2.0|±2.3||g|
|||FS bit set to 1|±8.0|±9.2|||
|So|Sensitivity|FS bit set to 0|16.2|18|19.8|mg/digit|
|||FS bit set to 1|64.8|72|79.2||
|TCSO|Sensitivity change vs
temperature|FS bit set to 0||±0.01||%/°C|
|TyOff|Typical zero-g level offset
accuracy(4),(5)|FS bit set to 0||±40||mg|
|||FS bit set to 1||±60||mg|
|TCOff|Zero-g level change vs
temperature|Max delta from 25°C||±0.5||mg/°C|
|Vst|Self test output
change(6),(7),(8),(9)|FS bit set to 0
STP bit used
X axis|-32||-3|LSb|
|||FS bit set to 0
STP bit used
Y axis|3||32|LSb|
|||FS bit set to 0
STP bit used
Z axis|3||32|LSb|
|BW|System bandwidth(10)|||ODR/2||Hz|
|Top|Operating temperature range||-40||+85|°C|
|Wh|Product weight|||30||mgram|
1. The product is factory calibrated at 2.5V. The device can be used from 2.16V to 3.6V
2. Typical specifications are not guaranteed
3. Verified by wafer level test and measurement of initial offset and sensitivity
4. Typical zero-g level offset value after MSL3 preconditioning
5. Offset can be eliminated by enabling the built-in high pass filter
6. If STM bit is used values change in sign for all axes
7. Self Test output changes with the power supply. Vst at 3.3V is typically in the range [-74; -7] LSb for X axis and [7;74] LSb for Y and Z axes.
8. “Self Test Output Change” is defined as OUTPUT[LSb](Self-test bit on ctrl_reg1=1) -OUTPUT[LSb](Self-test bit on ctrl_reg1=0). 1LSb=4.6g/256 at 8bit representation, ±2.3g Full-Scale
9. Output data reach 99% of final value after 3/ODR when enabling Self-Test mode due to device filtering
10. ODR is output data rate. Refer to _Table 4_ for specifications
10/42
**LIS302DL**
**Mechanical and electrical specifications**
## **2.2 Electrical characteristics**
## **Table 4. Electrical characteristics[(1)]**
(All the parameters are specified @ Vdd=2.5 V, T= 25°C unless otherwise noted)
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.(2)**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Vdd|Supply voltage||2.16|2.5|3.6|V|
|Vdd_IO|I/O pins supply voltage(3)||1.71||Vdd+0.1|V|
|Idd|Supply current|T = 25°C, ODR=100Hz||0.3|0.4|mA|
|IddPdn|Current consumption in
power-down mode|T = 25°C||1|5|µA|
|VIH|Digital high level input
voltage||0.8*Vdd
_IO|||V|
|VIL|Digital low level input voltage||||0.2*Vdd
_IO|V|
|VOH|High level output voltage||0.9*Vdd
_IO|||V|
|VOL|Low level output voltage||||0.1*Vdd
_IO|V|
|ODR|Output data rate|DR=0||100||Hz|
|||DR=1||400|||
|BW|System bandwidth(4)|||ODR/2||Hz|
|Ton|Turn-on time(5)|||3/ODR||s|
|Top|Operating temperature range||-40||+85|°C|
1. The product is factory calibrated at 2.5V. The device can be used from 2.16V to 3.6V
2. Typical specification are not guaranteed
3. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off.
4. Filter cut-off frequency
5. Time to obtain valid data after exiting Power-Down mode
11/42
**LIS302DL**
**Mechanical and electrical specifications**
## **2.3 Communication interface characteristics**
## **2.3.1 SPI - Serial Peripheral Interface**
Subject to general operating conditions for Vdd and Top.
## **Table 5. SPI slave timing values**
|**Symbol**|**Parameter**|**Value (**1**)**|**Value (**1**)**|**Unit**|
|---|---|---|---|---|
|||**Min.**|**Max.**||
|tc(SPC)|SPI clock cycle|100||ns|
|fc(SPC)|SPI clock frequency||10|MHz|
|tsu(CS)|CS setup time|5||ns|
|th(CS)|CS hold time|8|||
|tsu(SI)|SDI input setup time|5|||
|th(SI)|SDI input hold time|15|||
|tv(SO)|SDO valid output time||50||
|th(SO)|SDO output hold time|6|||
|tdis(SO)|SDO output disable time||50||
## **Figure 3. SPI slave timing diagram[(2)]**
**==> picture [461 x 207] intentionally omitted <==**
**----- Start of picture text -----**
CS (3) (3)
tsu(CS) tc(SPC) th(CS)
SPC (3) (3)
tsu(SI) th(SI)
SDI (3) MSB IN LSB IN (3)
tv(SO) th(SO) tdis(SO)
SDO (3) MSB OUT LSB OUT (3)
**----- End of picture text -----**
1. Values are guaranteed at 10MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production
2. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and Output port
3. When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors
12/42
**LIS302DL**
**Mechanical and electrical specifications**
## **2.3.2 I[2] C - inter IC control interface**
Subject to general operating conditions for Vdd and Top.
## **Table 6. I[2] C slave timing values**
|**Ta**|**ble 6.**
**I2C slave timing**|**values**|**values**||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**I2C standard mode (1)**
**Min**
**Max**||**I2C fast mode (1)**||**Unit**|
||||**Max**|**Min**|**Max**||
|f(SCL)|SCL clock frequency|0|100|0|400|KHz|
|tw(SCLL)|SCL clock low time|4.7||1.3||µs|
|tw(SCLH)|SCL clock high time|4.0||0.6|||
|tsu(SDA)|SDA setup time|250||100||ns|
|th(SDA)|SDA data hold time|0|3.45(**2)**|0|0.9(**2)**|µs|
|tr(SDA)tr(SCL)|SDA and SCL rise time||1000|20 + 0.1Cb
(**3)**|300|ns|
|tf(SDA)tf(SCL)|SDA and SCL fall time||300|20 + 0.1Cb
(**3)**|300||
|th(ST)|START condition hold time|4||0.6||µs|
|tsu(SR)|Repeated START condition
setup time|4.7||0.6|||
|tsu(SP)|STOP condition setup time|4||0.6|||
|tw(SP:SR)|Bus free time between STOP
and START condition|4.7||1.3|||
## **Figure 4. I[2] C Slave timing diagram[ (4)]**
**==> picture [461 x 183] intentionally omitted <==**
**----- Start of picture text -----**
REPEATED
START
START
tsu(SR)
SDA tw(SP:SR) START
tf(SDA) tr(SDA) tsu(SDA) th(SDA)
tsu(SP) STOP
SCL
th(ST) tw(SCLL) tw(SCLH) tr(SCL) tf(SCL)
**----- End of picture text -----**
1. Data based on standard I[2] C protocol requirement, not tested in production
2. A device must internally provide an hold time of at least 300ns for the SDA signal (referred to VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL
3. Cb = total capacitance of one bus line, in pF
4. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port
13/42
**LIS302DL**
**Mechanical and electrical specifications**
## **2.4 Absolute maximum ratings**
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
**Table 7. Absolute maximum ratings**
|**Table 7.**|**Absolute maximum ratingsgss**|||
|---|---|---|---|
|**Symbol**|**Ratings**|**Maximum value**|**Unit**|
|Vdd|Supply voltage|-0.3 to 6|V|
|Vdd_IO|I/O pins supply voltage|-0.3 to 6|V|
|Vin|Input voltage on any control pin
(CS, SCL/SPC, SDA/SDI/SDO)|-0.3 to Vdd_IO +0.3|V|
|APOW|Acceleration (any axis, powered, Vdd=2.5V)|3000g for 0.5 ms||
|||10000g for 0.1 ms||
|AUNP|Acceleration (any axis, unpowered)|3000g for 0.5 ms||
|||10000g for 0.1 ms||
|TOP|Operating temperature range|-40 to +85|°C|
|TSTG|Storage temperature range|-40 to +125|°C|
|ESD|Electrostatic discharge protection|4 (HBM)|kV|
|||1.5 (CDM)|kV|
|||200 (MM)|V|
_Note: Supply voltage on any pin should never exceed 6.0V_
This is a mechanical shock sensitive device, improper handling can cause permanent damages to the part
This is an ESD sensitive device, improper handling can cause permanent damages to the part
## **2.5 Terminology**
## **2.5.1**
## **Sensitivity**
Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (point to the sky) and noting the output value again. By doing so, ±1g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one and dividing the result by 2 leads to the actual sensitivity of the sensor. This value changes very little over temperature and also very little over time. The Sensitivity Tolerance describes the range of Sensitivities of a large population of sensor.
14/42
**LIS302DL**
**Mechanical and electrical specifications**
## **2.5.2 Zero-g level**
Zero-g level Offset (Off) describes the deviation of an actual output signal from the ideal output signal if there is no acceleration present. A sensor in a steady state on a horizontal surface will measure 0g in X axis and 0g in Y axis whereas the Z axis will measure 1g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to a precise MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zero-g level change vs. temperature”. The Zero-g level of an individual sensor is stable over lifetime. The Zero-g level tolerance describes the range of Zero-g levels of a population of sensors.
## **2.5.3**
## **Self test**
Self Test allows to check the sensor functionality without moving it. The Self Test function is off when the self-test bit of CTRL_REG1 (control register 1) is programmed to ‘0‘. When the self-test bit of ctrl_reg1 is programmed to ‘1‘ an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which is related to the selected full scale through the device sensitivity. When Self Test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified inside _Table 3_ , than the sensor is working properly and the parameters of the interface chip are within the defined specification.
## **2.5.4 Click and double click recognition**
The Click and Double Click recognition functions help to create man-machine interface with little software overload. The device can be configured to output an interrupt signal on dedicated pin when tapped in any direction.
If the sensor is exposed to a single input stimulus it generates an interrupt request on inertial interrupt pin (INT1 and/or INT2). A more advanced feature allows to generate and interrupt request when a “double click” with programmable time between the two events enabling a “mouse button like” use.
This function can be fully programmed by the user in terms of expected amplitude and timing of the stimuli.
15/42
**LIS302DL**
**Functionality**
## **3 Functionality**
The LIS302DL is a ultracompact, low-power, digital output 3-axis linear accelerometer packaged in a LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an I[2] C/SPI serial interface.
## **3.1 Sensing element**
A proprietary process is used to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation.
When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor.
At steady state the nominal value of the capacitors are few pF and when an acceleration is applied the maximum variation of the capacitive load is in fF range.
## **3.2 IC interface**
The complete measurement chain is composed by a low-noise capacitive amplifier which converts into an analog voltage the capacitive unbalancing of the MEMS sensor and by analog-to-digital converters.
The acceleration data may be accessed through an I[2] C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller.
The LIS302DL features a Data-Ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device.
The LIS302DL may also be configured to generate an inertial Wake-Up and Free-Fall interrupt signal accordingly to a programmed acceleration event along the enabled axes. Both Free-Fall and Wake-Up can be available simultaneously on two different pins.
## **3.3 Factory calibration**
The IC interface is factory calibrated for sensitivity (So) and Zero-g level (Off).
The trimming values are stored inside the device by a non volatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the normal operation. This allows the user to use the device without further calibration.
16/42
**LIS302DL**
**Application hints**
## **4 Application hints**
**==> picture [206 x 11] intentionally omitted <==**
**----- Start of picture text -----**
Figure 5. LIS302DL electrical connection
**----- End of picture text -----**
**==> picture [376 x 220] intentionally omitted <==**
**----- Start of picture text -----**
Vdd
Vdd_IO
6 1 Z
1
Y X
13
10uF 6
Top VIEW
8
100nF 8 13 TOP VIEW
DIRECTIONS OF THE
DETECTABLE
ACCELERATIONS
GND
CS INT 1 INT 2 SDO SDA/SDI/SDO SCL/SPC
**----- End of picture text -----**
**==> picture [309 x 9] intentionally omitted <==**
**----- Start of picture text -----**
Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO
**----- End of picture text -----**
The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Al) should be placed as near as possible to the pin 6 of the device (common design practice).
All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to _Figure 5_ ). It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off.
The functionality of the device and the measured acceleration data is selectable and accessible through the I[2] C/SPI interface.When using the I[2] C, CS must be tied high.
The functions, the threshold and the timing of the two interrupt pins (INT 1 and INT 2) can be completely programmed by the user though the I[2] C/SPI interface.
## **4.1 Soldering information**
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020C.
Leave “Pin 1 Indicator” unconnected during soldering.
Land pattern and soldering recommendation are available at www.st.com/mems.
17/42
**LIS302DL**
**Digital interfaces**
## **5 Digital interfaces**
The registers embedded inside the LIS302DL may be accessed through both the I[2] C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I[2] C interface, CS line must be tied high (i.e connected to Vdd_IO).
**Table 8. Serial interface pin description**
|**Table 8.**
**Serial**|**interfacepin description**|
|---|---|
|**PIN name**|**PIN description**|
|CS|SPI enable
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)|
|SCL/SPC|I2C Serial Clock (SCL)
SPI Serial Port Clock (SPC)|
|SDA/SDI/SDO|I2C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)|
|SDO|SPI Serial Data Output (SDO)|
## **5.1 I[2] C Serial Interface**
The LIS302DL I[2] C is a bus slave. The I[2] C is employed to write the data into the registers whose content can also be read back.
The relevant I[2] C terminology is given in the table below.
**Table 9. Serial interface pin description**
|**Table 9.**
**Serial**|**interfacepin description**|
|---|---|
|**Term**|**Description**|
|Transmitter|The device which sends data to the bus|
|Receiver|The device which receives data from the bus|
|Master|The device which initiates a transfer, generates clock signals and terminates a
transfer|
|Slave|The device addressed by the master|
There are two signals associated with the I[2] C bus: the Serial Clock Line (SCL) and the Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded inside the LIS302DL. When the bus is free both the lines are high.
The I[2] C interface is compliant with Fast Mode (400 kHz) I[2] C standards as well as the Normal Mode.
18/42
**LIS302DL**
**Digital interfaces**
## **5.1.1 I[2] C operation**
The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the Master.
The Slave ADdress (SAD) associated to the LIS302DL is 001110xb. **SDO** pad can be used to modify less significant bit of the device address. If SDO pad is connected to voltage supply LSb is ‘1’ (address 0011101b) else if SDO pad is connected to ground LSb value is ‘0’ (address 0011100b). This solution permits to connect and address two different accelerometer to the same I[2] C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data has been received.
The I[2] C embedded inside the LIS302DL behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a salve address is sent, once a slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7 LSb represent the actual register address while the MSB enables address auto increment. If the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented to allow multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the Master will transmit to the slave with direction unchanged. _Table 10_ explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations.
**Table 10. SAD+Read/Write patterns**
|**Command**|**SAD[6:1]**|**SAD[0] = SDO**|**R/W**|**SAD+R/W**|
|---|---|---|---|---|
|Read|001110|0|1|00111001 (39h)|
|Write|001110|0|0|00111000 (38h)|
|Read|001110|1|1|00111011 (3Bh)|
|Write|001110|1|0|00111010 (3Ah)|
## **Table 11. Transfer when master is writing one byte to slave**
|Master|Master|ST|ST|SAD + W|SAD + W|||SUB|SUB|||DATA|DATA|||SP|SP|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Slave||||||SAK||||SAK||||SAK||||
|**Table 12.**
**Transfer when master is writing multiple bytes to slave**||||||||||||||||||
|Master|ST||SAD + W||||SUB||DATA||||DATA||||SP|
|Slave|||||SAK|||SAK|||SAK||||SAK|||
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**LIS302DL**
**Digital interfaces**
**Table 13. Transfer when Master is receiving (reading) one byte of data from slave**
|Master|ST|SAD + W||SUB||SR|SAD + R|||NMAK|SP|
|---|---|---|---|---|---|---|---|---|---|---|---|
|Slave|||SAK||SAK|||SAK|DATA|||
## **Table 14. ransfer when master is receiving (reading)**
|Master|ST|SAD + W||SUB||SR|SAD + R|||MAK|
|---|---|---|---|---|---|---|---|---|---|---|
|Slave|||SAK||SAK|||SAK|DATA||
## **Table 15. Multiple bytes of data from slave**
|Master||MAK||NMAK|SP|
|---|---|---|---|---|---|
|Slave|DATA||DATA|||
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left HIGH by the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to read.
In the presented communication format MAK is Master Acknowledge and NMAK is No Master Acknowledge.
## **5.2 SPI bus interface**
The LIS302DL SPI is a bus slave. The SPI allows to write and read the registers of the device.
The Serial Interface interacts with the outside world with 4 wires: **CS** , **SPC** , **SDI** and **SDO** .
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**Digital interfaces**
## **Figure 6. Read & write protocol**
**==> picture [331 x 104] intentionally omitted <==**
**----- Start of picture text -----**
CS
SPC
SDI
RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
**----- End of picture text -----**
**CS** is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. **SPC** is the Serial Port Clock and it is controlled by the SPI master. It is stopped high when **CS** is high (no transmission). **SDI** and **SDO** are respectively the Serial Port Data Input and Output. Those lines are driven at the falling edge of **SPC** and should be captured at the rising edge of **SPC** .
Both the Read Register and Write Register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple byte read/write. Bit duration is the time between two falling edges of **SPC** . The first bit (bit 0) starts at the first falling edge of **SPC** after the falling edge of **CS** while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of **CS** .
_**bit 0**_ : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive **SDO** at the start of bit 8.
_**bit 1**_ : MS bit. When 0, the address will remain unchanged in multiple read/write commands. When 1, the address will be auto incremented in multiple read/write commands.
_**bit 2-7**_ : address AD(5:0). This is the address field of the indexed register.
_**bit 8-15**_ : data DI(7:0) (write mode). This is the data that will be written into the device (MSb first).
_**bit 8-15**_ : data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods will be added. When MS bit is 0 the address used to read/write data remains the same for every block. When MS bit is 1 the address used to read/write data is incremented at every block.
The function and the behavior of **SDI** and **SDO** remain unchanged.
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**LIS302DL**
**Digital interfaces**
## **5.2.1 SPI Read**
**Figure 7. SPI Read protocol**
**==> picture [282 x 90] intentionally omitted <==**
**----- Start of picture text -----**
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
**----- End of picture text -----**
The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one.
## _**bit 0**_ : READ bit. The value is 1.
_**bit 1**_ : MS bit. When 0 do not increment address, when 1 increment address in multiple reading.
_**bit 2-7**_ : address AD(5:0). This is the address field of the indexed register.
_**bit 8-15**_ : data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).
_**bit 16-...**_ : data DO(...-8). Further data in multiple byte reading.
## **Figure 8. Multiple bytes SPI Read protocol (2 bytes example)**
**==> picture [379 x 97] intentionally omitted <==**
**----- Start of picture text -----**
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8
**----- End of picture text -----**
## **5.2.2 SPI Write**
## **Figure 9. SPI Write protocol**
**==> picture [306 x 69] intentionally omitted <==**
**----- Start of picture text -----**
CS
SPC
SDI
RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
MS AD5 AD4 AD3 AD2 AD1 AD0
**----- End of picture text -----**
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**LIS302DL**
**Digital interfaces**
The SPI Write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one.
_**bit 0**_ : WRITE bit. The value is 0.
_**bit 1**_ : MS bit. When 0 do not increment address, when 1 increment address in multiple writing.
_**bit 2 -7**_ : address AD(5:0). This is the address field of the indexed register.
_**bit 8-15**_ : data DI(7:0) (write mode). This is the data that will be written inside the device (MSb first).
_**bit 16-...**_ : data DI(...-8). Further data in multiple byte writing.
## **Figure 10. Multiple bytes SPI Write protocol (2 bytes example)**
**==> picture [392 x 83] intentionally omitted <==**
**----- Start of picture text -----**
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
**----- End of picture text -----**
## **5.2.3 SPI Read in 3-wires mode**
3-wires mode is entered by setting to 1 bit SIM (SPI Serial Interface Mode selection) in CTRL_REG2.
## **Figure 11. SPI Read protocol in 3-wires mode**
CS SPC SDI/O RW DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 MS AD5 AD4 AD3 AD2 AD1 AD0
The SPI Read command is performed with 16 clock pulses:
_**bit 0**_ : READ bit. The value is 1.
_**bit 1**_ : MS bit. When 0 do not increment address, when 1 increment address in multiple reading.
_**bit 2-7**_ : address AD(5:0). This is the address field of the indexed register.
_**bit 8-15**_ : data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).
Multiple read command is also available in 3-wires mode.
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**LIS302DL**
**Register mapping**
## **6 Register mapping**
The table given below provides a listing of the 8 bit registers embedded in the device and the related address:
## **Table 16. Register address map**
|**Name**|**Type**|**Register address**|**Register address**|**Default**|**Comment**|
|---|---|---|---|---|---|
|||**Hex**|**Binary**|||
|Reserved (Do not modify)||00-0E|||Reserved|
|Who_Am_I|r|0F|000 1111|00111011|Dummy register|
|Reserved (Do not modify)||10-1F|||Reserved|
|Ctrl_Reg1|rw|20|010 0000|00000111||
|Ctrl_Reg2|rw|21|010 0001|00000000||
|Ctrl_Reg3|rw|22|010 0010|00000000||
|HP_filter_reset|r|23|010 0011|dummy|Dummy register|
|Reserved (Do not modify)||24-26|||Reserved|
|Status_Reg|r|27|010 0111|00000000||
|--|r|28|010 1000||Not Used|
|OutX|r|29|010 1001|output||
|--|r|2A|010 1010||Not Used|
|OutY|r|2B|010 1011|output||
|--|r|2C|010 1100||Not Used|
|OutZ|r|2D|010 1101|output||
|Reserved (Do not modify)||2E-2F|||Reserved|
|FF_WU_CFG_1|rw|30|011 0000|00000000||
|FF_WU_SRC_1(ack1)|r|31|011 0001|00000000||
|FF_WU_THS_1|rw|32|011 0010|0000000x||
|FF_WU_DURATION_1|rw|33|011 0011|00000000||
|FF_WU_CFG_2|rw|34|011 0100|00000000||
|FF_WU_SRC_2 (ack2)|r|35|011 0101|00000000||
|FF_WU_THS_2|rw|36|011 0110|00000000||
|FF_WU_DURATION_2|rw|37|011 0111|00000000||
|CLICK_CFG|rw|38|011 1000|00000000||
|CLICK_SRC (ack)|r|39|011 1001|00000000||
|--||3A|||Not Used|
|CLICK_THSY_X|rw|3B|011 1011|00000000||
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**LIS302DL**
**Register mapping**
## **Table 16. Register address map (continued)**
|**Name**|**Type**|**Register address**|**Register address**|**Default**|**Comment**|
|---|---|---|---|---|---|
|||**Hex**|**Binary**|||
|CLICK_THSZ|rw|3C|011 1100|00000000||
|CLICK_TimeLimit|rw|3D|011 1101|00000000||
|CLICK_Latency|rw|3E|011 1110|00000000||
|CLICK_Window|rw|3F|011 1111|00000000||
Registers marked as _Reserved_ must not be changed. The writing to those registers may cause permanent damages to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered-up.
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**LIS302DL**
**Register description**
## **7 Register description**
The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data through serial interface.
## **7.1 WHO_AM_I (0Fh)**
|**Table 17.**
**WHO_AM_I (0Fh) register**|**Table 17.**
**WHO_AM_I (0Fh) register**|**Table 17.**
**WHO_AM_I (0Fh) register**|**Table 17.**
**WHO_AM_I (0Fh) register**|**Table 17.**
**WHO_AM_I (0Fh) register**|**Table 17.**
**WHO_AM_I (0Fh) register**|**Table 17.**
**WHO_AM_I (0Fh) register**|**Table 17.**
**WHO_AM_I (0Fh) register**|
|---|---|---|---|---|---|---|---|
|0|0|1|1|1|0|1|1|
Device identification register. This register contains the device identifier that for LIS302DL is set to 3Bh.
## **7.2 CTRL_REG1 (20h)**
## **Table 18. CTRL_REG1 (20h) register**
|DR|PD|PD|FS|STP|STM|Zen|Yen|Xen|
|---|---|---|---|---|---|---|---|---|
|**Table 19.**
**CTRL_REG1(20h) register description**|||||||||
|DR||Data rate selection. Default value: 0
(0: 100 Hz output data rate; 1: 400 Hz output data rate)|||||||
|PD||Power Down Control. Default value: 0
(0: power down mode; 1: active mode)|||||||
|FS||Full Scale selection. Default value: 0
(refer to_Table 3_for typical full scale value)|||||||
|STP, STM||Self Test Enable. Default value: 0
(0: normal mode; 1: self test P, M enabled)|||||||
|Zen||Z axis enable. Default value: 1
(0: Z axis disabled; 1: Z axis enabled)|||||||
|Yen||Y axis enable. Default value: 1
(0: Y axis disabled; 1: Y axis enabled)|||||||
|Xen||X axis enable. Default value: 1
(0: X axis disabled; 1: X axis enabled)|||||||
**DR** bit allows to select the data rate at which acceleration samples are produced. The default value is 0 which corresponds to a data-rate of 100Hz. By changing the content of DR to “1” the selected data-rate will be set equal to 400Hz.
**PD** bit allows to turn on the turn the device out of power-down mode. The device is in powerdown mode when PD= “0” (default value after boot). The device is in normal mode when PD is set to 1.
**STP, STM** bit is used to activate the self test function. When the bit is set to one, an output change will occur to the device outputs (refer to _Table 3_ and _4_ for specification) thus allowing to check the functionality of the whole measurement chain.
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**LIS302DL**
**Register description**
**Zen** bit enables the generation of Data Ready signal for Z-axis measurement channel when set to 1. The default value is 1.
**Yen** bit enables the generation of Data Ready signal for Y-axis measurement channel when set to 1. The default value is 1.
**Xen** bit enables the generation of Data Ready signal for X-axis measurement channel when set to 1. The default value is 1.
## **7.3 CTRL_REG2 (21h)**
## **Table 20. CTRL_REG2 (21h) register**
|SIM|BOOT|BOOT|--|FDS|HP_FF_W
U2|HP_FF_W
U1|HP_coeff2|HP_coeff1|
|---|---|---|---|---|---|---|---|---|
|**Table 21.**
**CTRL_REG2(21h) register description**|||||||||
|SIM||SPI Serial Interface Mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface)|||||||
|BOOT||Reboot memory content. Default value: 0
(0: normal mode; 1: reboot memory content)|||||||
|FDS||Filtered Data Selection. Default value: 0
(0: internal filter bypassed; 1: data from internal filter sent to output register)|||||||
|HP FF_WU2||High Pass filter enabled for FreeFall/WakeUp # 2. Default value: 0
(0: filter bypassed; 1: filter enabled)|||||||
|HPFF_WU1||High Pass filter enabled for Free-Fall/Wake-Up #1. Default value: 0
(0: filter bypassed; 1: filter enabled)|||||||
|HP coeff2
HP coeff1||High pass filter cut-off frequency configuration. Default value: 00
(See table below)|||||||
**SIM** bit selects the SPI Serial Interface Mode. When SIM is ‘0’ (default value) the 4-wire interface mode is selected. The data coming from the device are sent to SDO pad. In 3-wire interface mode output data are sent to SDA_SDI pad.
**BOOT** bit is used to refresh the content of internal registers stored in the flash memory block. At the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. If for any reason the content of trimming registers was changed it is sufficient to use this bit to restore correct values. When BOOT bit is set to ‘1’ the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. These values are factory trimmed and they are different for every accelerometer. They permit a good behavior of the device and normally they have not to be changed. At the end of the boot process the BOOT bit is set again to ‘0’.
**FDS** bit enables (FDS=1) or bypass (FDS=0) the high pass filter in the signal chain of the sensor
**HP_coeff[2:1]** . These bits are used to configure high-pass filter cut-off frequency ft.
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**LIS302DL**
**Register description**
## **Table 22. High pass filter cut-off frequency configuration**
|**HP_coeff2,1**|**ft (Hz)**
**(DR=100 Hz)**|**ft (Hz)**
**(DR=400 Hz)**|
|---|---|---|
|00|2|8|
|01|1|4|
|10|0.5|2|
|11|0.25|1|
## **7.4 CTRL_REG3 [Interrupt CTRL register] (22h)**
**Table 23. CTRL_REG3 (22h) register**
IHL PP_OD I2CFG2 I2CFG1 I2CFG0 I1CFG2 I1CFG1 I1CFG0
**Table 24. CTRL_REG3 (22h) register description**
|IHL|Interrupt active high, low. Default value 0.
(0: active high; 1: active low)|
|---|---|
|PP_OD|Push-pull/Open Drain selection on interrupt pad. Default value 0.
(0: push-pull; 1: open drain)|
|I2CFG2
I2CFG1
I2CFG0|Data Signal on Int2 pad control bits. Default value 000.
(see table below)|
|I1CFG2
I1CFG1
I1CFG0|Data Signal on Int1 pad control bits. Default value 000.
(see table below)|
## **Table 25. CTRL_REG3 (22h) truth table**
|**I1(2)_CFG2**|**I1(2)_CFG1**|**I1(2)_CFG0**|**Int1(2) Pad**|
|---|---|---|---|
|0|0|0|GND|
|0|0|1|FF_WU_1|
|0|1|0|FF_WU_2|
|0|1|1|FF_WU_1 or FF_WU_2|
|1|0|0|Data ready|
|1|1|1|Click interrupt|
## **7.5 HP_FILTER_RESET (23h)**
Dummy register. Reading at this address zeroes instantaneously the content of the internal high pass-filter. If the high pass filter is enabled all three axes are instantaneously set to 0g. This allows to overcome the settling time of the high pass filter.
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**LIS302DL**
**Register description**
## **7.6 STATUS_REG (27h)**
## **Table 26. STATUS_REG (27h) register**
|ZXYOR|ZOR|ZOR|YOR|XOR|ZYXDA|ZDA|YDA|XDA|
|---|---|---|---|---|---|---|---|---|
|**Table 27.**
**STATUS_REG(27h) register desription**|||||||||
|ZYXOR||X, Y and Z axis data overrun. Default value: 0
(0: no overrun has occurred;
1: new data has over written the previous one before it was read)|||||||
|ZOR||Z axis data overrun. Default value: 0
(0: no overrun has occurred;
1: a new data for the Z-axis has overwritten the previous one)|||||||
|YOR||Y axis data overrun. Default value: 0
(0: no overrun has occurred;
1: a new data for the Y-axis has overwritten the previous one)|||||||
|XOR||X axis data overrun. Default value: 0
(0: no overrun has occurred;
1: a new data for the X-axis has overwritten the previous one)|||||||
|ZYXDA||X, Y and Z axis new data available. Default value: 0
(0: a new set of data is not yet available; 1: a new set of data is available)|||||||
|ZDA||Z axis new data available. Default value: 0
(0: a new data for the Z-axis is not yet available;
1: a new data for the Z-axis is available)|||||||
|YDA||Y axis new data available. Default value: 0
(0: a new data for the Y-axis is not yet available;
1: a new data for the Y-axis is available)|||||||
|XDA||X axis new data available. Default value: 0
(0: a new data for the X-axis is not yet available;
1: a new data for the X-axis is available)|||||||
## **7.7 OUT_X (29h)**
## **Table 28. OUT_X (29h) register**
XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0
X axis output data.
## **7.8 OUT_Y (2Bh)**
**Table 29. OUT_Y (2Bh) register description**
YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0
Y axis output data.
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**LIS302DL**
**Register description**
## **7.9 OUT_Z (2Dh)**
**Table 30. OUT_Z (2Dh) register**
ZD7 ZD6 ZD5 ZD4 ZD3 ZD2 ZD1 ZD0
Z axis output data.
## **7.10 FF_WU_CFG_1 (30h)**
## **Table 31. FF_WW_CFG_1 (30h) register**
AOI LIR ZHIE ZLIE YHIE YLIE XHIE XLIE
**Table 32. FF_WW_CFG_1(30h) register description**
|AOI|And/or combination of Interrupt events. Default value: 0
(0: OR combination of interrupt events; 1: AND combination of interrupt events)|
|---|---|
|LIR|Latch Interrupt request into FF_WU_SRC reg with the FF_WU_SRC reg cleared by
reading FF_WU_SRC_1 reg. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)|
|ZHIE|Enable interrupt generation on Z high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)|
|ZLIE|Enable interrupt generation on Z low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)|
|YHIE|Enable interrupt generation on Y high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)|
|YLIE|Enable interrupt generation on Y low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)|
|XHIE|Enable interrupt generation on X high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)|
|XLIE|Enable interrupt generation on X low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)|
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**LIS302DL**
**Register description**
## **7.11 FF_WU_SRC_1 (31h)**
**Table 33. FF_WU_SRC_1 (31h) register**
|X|X|IA|ZH|ZL|YH|YL|XH|XL|
|---|---|---|---|---|---|---|---|---|
|**Table 34.**
**FF_WU_SRC_1(31h) register description**|||||||||
|IA|Interrupt active. Default value: 0
(0: no interrupt has been generated; 1: one ore more interrupt has been generated)||||||||
|ZH|Z high. Default value: 0
(0: no interrupt, 1: ZH event has occurred)||||||||
|ZL|Z low. Default value: 0
(0: no interrupt; 1: ZL event has occurred)||||||||
|YH|Y high. Default value: 0
(0: no interrupt, 1: YH event has occurred)||||||||
|YL|Y low. Default value: 0
(0: no interrupt, 1: YL event has occurred)||||||||
|XH|X high. Default value: 0
(0: no interrupt, 1: XH event has occurred)||||||||
|XL|X low. Default value: 0
(0: no interrupt, 1: XL event has occurred)||||||||
Free-fall and wake-up source register. Read only register.
Reading at this address clears FF_WU_SRC_1 register and the FF, WU 1 interrupt and allows the refreshment of data in the FF_WU_SRC_1 register if the latched option was chosen.
## **7.12 FF_WU_THS_1 (32h)**
|**Table 35.**
**FF_WU_THS_1(32h) register**|**Table 35.**
**FF_WU_THS_1(32h) register**|**Table 35.**
**FF_WU_THS_1(32h) register**|**Table 35.**
**FF_WU_THS_1(32h) register**|**Table 35.**
**FF_WU_THS_1(32h) register**|**Table 35.**
**FF_WU_THS_1(32h) register**|**Table 35.**
**FF_WU_THS_1(32h) register**|**Table 35.**
**FF_WU_THS_1(32h) register**|**Table 35.**
**FF_WU_THS_1(32h) register**|
|---|---|---|---|---|---|---|---|---|
|DCRM|THS6||THS5|THS4|THS3|THS2|THS1|THS0|
|**Table 36.**
**FF_WU_THS_1(32h) register description**|||||||||
|DCRM||Resetting mode selection. Default value: 0
(0: counter resetted; 1: counter decremented)|||||||
|THS6, THS0||Free-fall / wake-up threshold: default value: 000 000x|||||||
Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If DCRM=0 counter is resetted when the interrupt is no more active else if DCRM=1 duration counter is decremented.
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**LIS302DL**
**Register description**
## **7.13 FF_WU_DURATION_1 (33h)**
|**Table 37.**
**FF_WU_DURATION_1(33h) register**|**Table 37.**
**FF_WU_DURATION_1(33h) register**|**Table 37.**
**FF_WU_DURATION_1(33h) register**|**Table 37.**
**FF_WU_DURATION_1(33h) register**|**Table 37.**
**FF_WU_DURATION_1(33h) register**|**Table 37.**
**FF_WU_DURATION_1(33h) register**|**Table 37.**
**FF_WU_DURATION_1(33h) register**|**Table 37.**
**FF_WU_DURATION_1(33h) register**|**Table 37.**
**FF_WU_DURATION_1(33h) register**|
|---|---|---|---|---|---|---|---|---|
|D7|D6||D5|D4|D3|D2|D1|D0|
|**Table 38.**
**FF_WU_DURATION_1(33h) register description**|||||||||
|D7-D0||Duration value. Default value: 0000 0000|||||||
Duration register for Free-Fall/Wake-Up interrupt 1. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400Hz, else step 10 msec, from 0 to 2.55 sec when ODR=100Hz. The counter used to implement duration function is blocked when LIR=1 in configuration register and the interrupt event is verified
## **7.14 FF_WU_CFG_2 (34h)**
|**Table 39.**
**FF_WU_CFG_2(34h) register**|**Table 39.**
**FF_WU_CFG_2(34h) register**|**Table 39.**
**FF_WU_CFG_2(34h) register**|**Table 39.**
**FF_WU_CFG_2(34h) register**|**Table 39.**
**FF_WU_CFG_2(34h) register**|**Table 39.**
**FF_WU_CFG_2(34h) register**|**Table 39.**
**FF_WU_CFG_2(34h) register**|**Table 39.**
**FF_WU_CFG_2(34h) register**|**Table 39.**
**FF_WU_CFG_2(34h) register**|
|---|---|---|---|---|---|---|---|---|
|AOI|LIR||ZHIE|ZLIE|YHIE|YLIE|XHIE|XLIE|
|**Table 40.**
**FF_WU_CFG_2(34h) register description**|||||||||
|AOI||And/or combination of Interrupt events. Default value: 0
(0: OR combination of interrupt events; 1: AND combination of interrupt events)|||||||
|LIR||Latch interrupt request into FF_WU_SRC reg with the FF_WU_SRC reg cleared by
reading FF_WU_SRC_2 reg. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)|||||||
|ZHIE||Enable interrupt generation on Z high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)|||||||
|ZLIE||Enable interrupt generation on Z low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)|||||||
|YHIE||Enable interrupt generation on Y high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)|||||||
|YLIE||Enable interrupt generation on Y low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)|||||||
|XHIE||Enable interrupt generation on X high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)|||||||
|XLIE||Enable interrupt generation on X low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)|||||||
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**LIS302DL**
**Register description**
## **7.15 FF_WU_SRC_2 (35h)**
|**Table 41.**
**FF_WU_SRC_2(35h) register**|**Table 41.**
**FF_WU_SRC_2(35h) register**|**Table 41.**
**FF_WU_SRC_2(35h) register**|**Table 41.**
**FF_WU_SRC_2(35h) register**|**Table 41.**
**FF_WU_SRC_2(35h) register**|**Table 41.**
**FF_WU_SRC_2(35h) register**|**Table 41.**
**FF_WU_SRC_2(35h) register**|**Table 41.**
**FF_WU_SRC_2(35h) register**|**Table 41.**
**FF_WU_SRC_2(35h) register**|
|---|---|---|---|---|---|---|---|---|
|X|IA||ZH|ZL|YH|YL|XH|XL|
|**Table 42.**
**FF_WU_SRC_2(35h) register description**|||||||||
|IA||Interrupt active. Default value: 0
(0: no interrupt has been generated;
1: one or more interrupt event has been generated)|||||||
|ZH||Z high. Default value: 0
(0: no interrupt; 1: ZH event has occurred)|||||||
|ZL||Z low. Default value: 0
(0: no interrupt; 1: ZL event has occurred)|||||||
|YH||Y high. Default value: 0
(0: no interrupt; 1: YH event has occurred)|||||||
|YL||Y low. Default value: 0
(0: no interrupt; 1: YL event has occurred)|||||||
|XH||X high. Default value: 0
(0: no interrupt; 1: XH event has occurred)|||||||
|XL||X low. Default value: 0
(0: no interrupt; 1: XL event has occurred)|||||||
Free-fall and wake-up source register. Read only register.
Reading at this address clears FF_WU_SRC_2 register and the FF, WU 2 interrupt and allows the refreshment of data in the FF_WU_SRC_2 register if the latched option was chosen.
## **7.16 FF_WU_THS_2 (36h)**
|**FF_WU_THS_2 (36h)**|**FF_WU_THS_2 (36h)**|**FF_WU_THS_2 (36h)**|**FF_WU_THS_2 (36h)**|**FF_WU_THS_2 (36h)**|**FF_WU_THS_2 (36h)**|**FF_WU_THS_2 (36h)**|**FF_WU_THS_2 (36h)**|**FF_WU_THS_2 (36h)**|
|---|---|---|---|---|---|---|---|---|
|**Table 43.**
**FF_WU_THS_2(36h) register**|||||||||
|DCRM|THS6||THS5|THS4|THS3|THS2|THS1|THS0|
|**Table 44.**
**FF_WU_THS_2(36h) register description**|||||||||
|DCRM||Resetting mode selection. Default value: 0
(0: counter resetted; 1: counter decremented)|||||||
|THS6, THS0||Free-fall / wake-up Threshold. Default value: 000 0000|||||||
Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If DCRM=0 counter is resetted when the interrupt is no more active else if DCRM=1 duration counter is decremented.
## **7.17 FF_WU_DURATION_2 (37h)**
**Table 45. FF_WU_DURATION_2 (37h) register**
D7 D6 D5 D4 D3 D2 D1 D0
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**LIS302DL**
**Register description**
|**Table 46.**
**FF_WU_DURATION_2(37h) register description**|**Table 46.**
**FF_WU_DURATION_2(37h) register description**|
|---|---|
|D7-D0|Duration value. Default value: 0000 0000|
Duration register for Free-Fall/Wake-Up interrupt 2. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400Hz, else step 10 msec, from 0 to 2.55 sec when ODR=100Hz. The counter used to implement duration function is blocked when LIR=1 in configuration register and the interrupt event is verified.
## **7.18 CLICK_CFG (38h)**
## **Table 47. CLICK_CFG (38h) register**
|-|LIR|LIR|Double_Z|Single_Z|Double_Y|Single_Y|Double_X|Single_X|
|---|---|---|---|---|---|---|---|---|
|**Table 48.**
**CLICK_CFG(38h) register description**|||||||||
|LIR||Latch interrupt request into CLICK_SRC reg with the CLICK_SRC reg
refreshed by reading CLICK_SRC reg. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)|||||||
|Double_Z||Enable interrupt generation on double click event on Z axis. Default value: 0
(0: disable interrupt request; 1: enable interrupt request)|||||||
|Single_Z||Enable interrupt generation on single click event on Z axis. Default value: 0
(0: disable interrupt request; 1: enable interrupt request)|||||||
|Double_Y||Enable interrupt generation on double click event on Y axis. Default value: 0
(0: disable interrupt request; 1: enable interrupt request)|||||||
|Single_Y||Enable interrupt generation on single click event on Y axis. Default value: 0
(0: disable interrupt request; 1: enable interrupt request)|||||||
|Double_X||Enable interrupt generation on double click event on X axis. Default value: 0
(0: disable interrupt request; 1: enable interrupt request)|||||||
|Single_X||Enable interrupt generation on single click event on X axis. Default value: 0
(0: disable interrupt request; 1: enable interrupt request)|||||||
## **Table 49. CLICK_CFG (38h) truth table**
|**Double_Z / Y / X**|**Single_Z / Y / X**|**Click output**|
|---|---|---|
|0|0|0|
|0|1|Single|
|1|0|Double|
|1|1|Single or double|
## **7.19 CLICK_SRC (39h)**
## **Table 50. CLICK_SRC (39h) register**
X IA Double_Z Single_Z Double_Y Single_Y Double_X Single_X
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**LIS302DL**
**Register description**
## **Table 51. CLICK_SRC (39h) register description**
|**Table 51.**|**CLICK_SRC(39h) register description**|
|---|---|
|IA|Interrupt active. Default value: 0
(0: no interrupt has been generated;
1: one or more interrupt event has been generated)|
|Double_Z|Double click on Z axis event. Default value: 0
(0: no interrupt; 1: Double Z event has occurred)|
|Single_Z|Single click on Z axis event. Default value: 0
(0: no interrupt; 1: Single Z event has occurred)|
|Double_Y|Double click on Y axis event. Default value: 0
(0: no interrupt; 1: Double Y event has occurred)|
|Single_Y|Single click on Y axis event.Default value: 0
(0: no interrupt; 1: Single Y event has occurred)|
|Double_X|Double click on X axis event. Default value: 0
(0: no interrupt; 1: Double X event has occurred)|
|Single_X|Single click on X axis event. Default value: 0
(0: no interrupt; 1: Single X event has occurred)|
## **7.20 CLICK_THSY_X (3Bh)**
**Table 52. CLICK_THSY_X (3Bh) register**
|THSy3|THSy2|THSy2|THSy1|THSy0|THSx3|THSx2|THSx1|THSx0|
|---|---|---|---|---|---|---|---|---|
|**Table 53.**
**CLICK_THSY_X(3Bh) register description**|||||||||
|THSy3-THSy0||Click threshold on Y axis. Default value: 0000|||||||
|THSx3-THSx0||Click threshold on X axis. Default value: 0000|||||||
From 0.5g(0001) to 7.5g(1111) with step of 0.5g.
## **7.21 CLICK_THSZ (3Ch)**
**Table 54. CLICK_THSZ (3Ch) register**
|X|X|X|X|X|THSz3|THSz2|THSz1|THSz0|
|---|---|---|---|---|---|---|---|---|
|**Table 55.**
**CLICK_THSZ(3Ch) register description**|||||||||
|THSz3-THSz0||Click Threshold on Z axis. Default value: 0000|||||||
From 0.5g(0001) to 7.5g(1111) with step of 0.5g.
## **7.22 CLICK_TimeLimit (3Dh)**
**Table 56. CLICK_TimeLimit (3Dh) register**
Dur7 Dur6 Dur5 Dur4 Dur3 Dur2 Dur1 Dur0
From 0 to 127.5msec with step of 0.5 msec,
35/42
**LIS302DL**
**Register description**
## **7.23 CLICK_Latency (3Eh)**
|**Table 57.**
**CLICK_Latency (3Eh) register**|**Table 57.**
**CLICK_Latency (3Eh) register**|**Table 57.**
**CLICK_Latency (3Eh) register**|**Table 57.**
**CLICK_Latency (3Eh) register**|**Table 57.**
**CLICK_Latency (3Eh) register**|**Table 57.**
**CLICK_Latency (3Eh) register**|**Table 57.**
**CLICK_Latency (3Eh) register**|**Table 57.**
**CLICK_Latency (3Eh) register**|
|---|---|---|---|---|---|---|---|
|Lat7|Lat6|Lat5|Lat4|Lat3|Lat2|Lat1|Lat0|
|From 0 to 255 msec with step of 1 msec.||||||||
## **7.24 CLICK_Window (3Fh)**
|**Table 58.**
**CLICK_Window(3Fh) register**|**Table 58.**
**CLICK_Window(3Fh) register**|**Table 58.**
**CLICK_Window(3Fh) register**|**Table 58.**
**CLICK_Window(3Fh) register**|**Table 58.**
**CLICK_Window(3Fh) register**|**Table 58.**
**CLICK_Window(3Fh) register**|**Table 58.**
**CLICK_Window(3Fh) register**|**Table 58.**
**CLICK_Window(3Fh) register**|
|---|---|---|---|---|---|---|---|
|Win7|Win6|Win5|Win4|Win3|Win2|Win1|Win0|
From 0 to 255 msec with step of 1 msec.
36/42
**LIS302DL**
**Typical performance characteristics**
## **8 Typical performance characteristics**
## **8.1 Mechanical characteristics at 25°C**
**Figure 12. X axis 0-g level at 2.5V**
## **Figure 13. X axis sensitivity at 2.5V**
**==> picture [461 x 486] intentionally omitted <==**
**----- Start of picture text -----**
30 15
25
20 10
15
10 5
5
−1500 −100 −50 0 50 100 150 016 16.5 17 17.5 18 18.5 19 19.5 20
Zero−g Level Offset [mg] Sensitivity [mg/digits]
Figure 14. Y axis 0-g level at 2.5V Figure 15. Y axis sensitivity at 2.5V
30 14
25 12
10
20
8
15
6
10
4
5 2
0 0
−150 −100 −50 0 50 100 150 16 16.5 17 17.5 18 18.5 19 19.5 20
Zero−g Level Offset [mg] Sensitivity [mg/digits]
Figure 16. Z axis 0-g level at 2.5V Figure 17. Z axis sensitivity at 2.5V
25 15
20
10
15
10
5
5
0 0
−150 −100 −50 0 50 100 150 16 16.5 17 17.5 18 18.5 19 19.5 20
Zero−g Level Offset [mg] Sensitivity [mg/digits]
Percent of parts [%] Percent of parts [%]
Percent of parts [%] Percent of parts [%]
Percent of parts [%] Percent of parts [%]
**----- End of picture text -----**
37/42
**LIS302DL**
**Typical performance characteristics**
## **8.2 Mechanical characteristics derived from measurement in the -40°C to +85°C temperature range**
**Figure 18. X axis 0-g level change vs Figure 19. X axis Sensitivity change vs temperature at 2.5V temperature at 2.5V**
**==> picture [461 x 510] intentionally omitted <==**
**----- Start of picture text -----**
35 60
30 50
25
40
20
30
15
20
10
5 10
0 0
−3 −2 −1 0 1 2 3 −0.05 0 0.05
0−g level drift (mg/ [ο] C) sensitivity drift (%/deg. C)
Figure 20. Y axis 0-g level change vs Figure 21. Y axis sensitivity change Vs
temperature at 2.5V temperature at 2.5V
35 60
30 50
25
40
20
30
15
20
10
5 10
0 0
−3 −2 −1 0 1 2 3 −0.05 0 0.05
0−g level drift (mg/ [ο] C) sensitivity drift (%/deg. C)
Figure 22. Z axis 0-g level change vs Figure 23. Z axis sensitivity change vs
temperature at 2.5V temperature at 2.5V
35 60
30 50
25
40
20
30
15
20
10
5 10
0 0
−2 −1 0 1 2 3 4 −0.05 0 0.05
0−g level drift (mg/ [ο] C) sensitivity drift (%/deg. C)
Percent of parts (%) Percent of parts (%)
Percent of parts (%) Percent of parts (%)
Percent of parts (%) Percent of parts (%)
**----- End of picture text -----**
38/42
**LIS302DL**
**Typical performance characteristics**
## **8.3 Electro-mechanical characteristics at 25°C**
**Figure 24. Current consumption in normal Figure 25. Current consumption in power mode at 2.5V down mode at 2.5V**
**==> picture [175 x 139] intentionally omitted <==**
**----- Start of picture text -----**
30
25
20
15
10
5
0
200 220 240 260 280 300 320 340 360 380 400
Current consumption [uA]
Percent of parts [%]
**----- End of picture text -----**
**==> picture [174 x 131] intentionally omitted <==**
**----- Start of picture text -----**
35
30
25
20
15
10
5
0
−1 0 1 2 3 4 5
current consumption (uA)
Percent of parts (%)
**----- End of picture text -----**
39/42
**LIS302DL**
**Package information**
## **9 Package information**
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
## **Figure 26. LGA 14: mechanical data and package dimensions**
|**D**|**IM.**||**mm**|**mm**|||**inch**
**MIN.**
**TYP.**
**MAX.**
0.0362 0.0394
0.0275
0071 0.0087 0.0102
1122 0.1181 0.1240
1909 0.1968 0.2027
0.0315
0.0118
0.1575
0.0535
0.0472
0380 0.0384 0.0386
0252 0.0256 0.0260
0295 0.0315 0.0335
0177 0.0197 0.0217
0472
0.0630
0.0059
0.0020
0.0039
0.0039|**inch**
**MIN.**
**TYP.**
**MAX.**
0.0362 0.0394
0.0275
0071 0.0087 0.0102
1122 0.1181 0.1240
1909 0.1968 0.2027
0.0315
0.0118
0.1575
0.0535
0.0472
0380 0.0384 0.0386
0252 0.0256 0.0260
0295 0.0315 0.0335
0177 0.0197 0.0217
0472
0.0630
0.0059
0.0020
0.0039
0.0039|**OUTLINE AND**
**MECHANICAL DATA**
**LGA14 (3x5x0.92mm) Pitch 0.8mm**
**L**and**G**rid**A**rray**Package**|**OUTLINE AND**
**MECHANICAL DATA**
**LGA14 (3x5x0.92mm) Pitch 0.8mm**
**L**and**G**rid**A**rray**Package**|**OUTLINE AND**
**MECHANICAL DATA**
**LGA14 (3x5x0.92mm) Pitch 0.8mm**
**L**and**G**rid**A**rray**Package**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|||**MI**|**N.**|**TYP.**|**MAX.**||**MIN.**|**TYP.**||||
||A1|||0.920|1.000||0|.0362||||
||A2||||0.700|||||||
||A3|0.1|80|0.220|0.260|0.|0071 0|.0087||||
||D1|2.8|50|3.000|3.150|0.|1122 0|.1181||||
||E1|4.8|50|5.000|5.150|0.|1909 0|.1968||||
||e|||0.800|||0|.0315||||
||d|||0.300|||0|.0118||||
||L1|||4.000|||0|.1575||||
||N|||1.360|||0|.0535||||
||N1|||1.200|||0|.0472||||
||P1|0.9|65|0.975|0.985|0.|0380 0|.0384||||
||P2|0.6|40|0.650|0.660|0.|0252 0|.0256||||
||T1|0.7|50|0.800|0.850|0.|0295 0|.0315||||
||T2|0.4|50|0.500|0.550|0.|0177 0|.0197||||
||R|1.2|00||1.600|0.|0472|||||
||h|||0.150|||0|.0059||||
||k|||0.050|||0|.0020||||
||i|||0.100|||0|.0039||||
||s|||0.100|||0|.0039||||
|||||||||||||
|||||||||||||
|||||||||||||
|||||||||||||
||||||||||||7773587 C|
40/42
**LIS302DL**
**Revision history**
## **10 Revision history**
## **Table 59. Document revision history**
|**Date**|**Revision**|**Changes**|
|---|---|---|
|3-Oct-2006|1|Initial release.|
|6-Feb-2007|2|Added functions and registers information and typical performance
characteristics|
|25-Oct-2007|3|Added interfaces timing characteristics and global datasheet review
to improved readability|
|21-Oct-2008|4|Updated self test limits (_Table 3_)|
41/42
**LIS302DL**
## **Please Read Carefully:**
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42/42
## Links
- [View this product on Novapart](https://novapart.co/products/LIS302DL/mems-accelerometer-3-axis-2g-8g-x-y-z-i2c-spi-lga)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/stmicroelectronics/lis302dl/ic-accelerometer-3-axis-14lga/dp/1435588)
---
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