# Power MOSFET, N Channel, 30 V, 161 A, 0.0033 ohm, TO-251AA, Through Hole

![Product image](https://novapart.co/image/farnell:1013426/)

**URL**: https://novapart.co/products/IRLU7843PBF/power-mosfet-n-channel-30-v-161-a-00033-ohm-to
**SKU**: IRLU7843PBF
**Manufacturer**: INFINEON
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.6500
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Power Dissipation | 140W |
| Transistor Mounting | Through Hole |
| Transistor Polarity | N Channel |
| Power Dissipation Pd | 140W |
| Rds(On) Test Voltage | 10V |
| On Resistance Rds(On) | 0.0033ohm |
| Transistor Case Style | TO-251AA |
| Drain Source Voltage Vds | 30V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 161A |
| Drain Source On State Resistance | 0.0033ohm |
| Gate Source Threshold Voltage Max | 2.3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:1013426/)

## PD - 95440B IRLR7843PbF IRLU7843PbF 

## **Applications** 

High Frequency Synchronous Buck Converters for Computer Processor Power High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use Lead-Free 

## HEXFET Power MOSFET 

|**VDSS**|**RDS(on) max**|**Qg**|
|---|---|---|
|**30V**|**3.3m**|**34nC**|



## **Benefits** 

Very Low RDS(on) at 4.5V VGS Ultra-Low Gate Impedance Fully Characterized Avalanche Voltage and Current 

D-Pak I-Pak IRLR7843PbF IRLU7843PbF 

## **Absolute Maximum Ratings** 

||**Parameter**|**Max.**|**Units**|
|---|---|---|---|
|VDS|Drain-to-Source Voltage<br>~~a~~<br>~~ee~~|30<br>~~a~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|
|VGS|Gate-to-Source Voltage<br>~~ee~~<br>~~ee~~|± 20<br>~~ee~~<br>~~ee~~||
|ID@ TC= 25°C|Continuous Drain Current, VGS@ 10V<br>~~a~~<br>~~ee~~|161<br>~~a~~<br>~~ee~~|A<br>~~ee~~|
|ID@ TC= 100°C|Continuous Drain Current, VGS@ 10V<br>~~OO~~<br>~~ee~~|113<br>~~OO~~<br>~~ee~~||
|IDM|Pulsed Drain Current<br>~~ee~~|620<br>~~ee~~||
|PD@TC= 25°C|Maximum Power Dissipation<br>~~ee~~<br>~~ee~~|140<br>~~ee~~<br>~~ee~~|W<br>~~ee~~<br>~~ee~~<br>~~LT~~|
|PD@TC= 100°C|Maximum Power Dissipation<br>~~ee~~<br>~~TT~~|71<br>~~ee~~<br>~~LT~~||
|~~po~~|Linear Derating Factor<br>~~ee~~<br>~~TT~~<br>~~po~~|0.95<br>~~ee~~<br>~~LT~~<br>~~po~~|W/°C<br>~~ee~~<br>~~LT~~<br>~~po~~|
|TJ<br>TSTG<br>~~po~~|Operating Junction and<br>Storage Temperature Range<br>~~TT~~<br>~~po~~|-55  to + 175<br>~~LT~~<br>~~po~~|°C<br>~~LT~~<br>~~po~~|
|~~po~~|Soldering Temperature, for 10 seconds<br>~~po~~|300 (1.6mm from case)<br>~~po~~||



Notes 0) hrough ©) are on page 11 www.irf.com 

1 04/30/08 

**Static @ TJ = 25°C (unless otherwise specified)** 

|~~pO~~|**Parameter**<br>~~pO~~|**Min.**|**Typ.**|**Max. **|**Units**|**Conditions**|
|---|---|---|---|---|---|---|
|BVDSS<br>~~pO~~|Drain-to-Source Breakdown Voltage<br>~~pO~~|30|–––|–––|V|VGS= 0V, ID= 250µA|
|∆ΒVDSS/∆TJ<br>~~pO~~|Breakdown Voltage Temp. Coefficient<br>~~pO~~<br>~~pO~~|–––<br>~~pO~~|19<br>~~pO~~|–––<br>~~pO~~|mV/°C<br>~~pO~~|Reference to 25°C, ID= 1mA<br>~~pO~~|
|RDS(on)|Static Drain-to-Source On-Resistance<br>~~eS~~|–––<br>~~eS~~<br>~~|~~|2.6<br>~~eS~~<br>~~||~~|3.3<br>~~|~~|mΩ|VGS= 10V, ID= 15A<br>~~e~~|
|||–––<br>~~eS~~<br>~~|~~|3.2<br>~~eS~~<br>~~||~~|4.0<br>~~|~~||VGS= 4.5V, ID= 12A<br>~~e~~|
|VGS(th)|Gate Threshold Voltage<br>~~a~~|1.4<br>~~|~~<br>~~a~~|–––<br>~~| |~~<br>~~a~~|2.3<br>~~|~~<br>~~a~~|V<br>~~a~~|VDS= VGS, ID= 250µA<br>~~e~~<br>~~——~~|
|∆VGS(th)/∆TJ|Gate Threshold Voltage Coefficient<br>~~a~~|–––<br>~~a~~<br>~~|~~|-5.4<br>~~a~~<br>~~|~~|–––<br>~~a~~<br>~~—~~<br>|mV/°C<br>~~a~~<br>~~—~~||
|IDSS|Drain-to-Source Leakage Current<br>~~a~~|–––<br>~~a~~<br>~~|~~|–––<br>~~a~~<br>~~|~~|1.0<br>~~a~~<br>~~—~~<br>|µA<br>~~a~~<br>~~—~~|VDS= 24V, VGS= 0V<br>~~a~~|
|||–––<br>~~a~~<br>~~|~~|–––<br>~~a~~<br>~~||~~|150<br>~~a~~<br>~~—~~<br>~~|~~||VDS= 24V, VGS= 0V, TJ= 125°C<br>~~a~~|
|IGSS<br>~~pO~~|Gate-to-Source Forward Leakage<br>~~a~~<br>~~—————~~|–––<br>~~a~~<br>~~|~~<br>~~a~~|–––<br>~~a~~<br>~~||~~|100<br>~~a~~<br>~~—~~<br>~~|~~|nA<br>~~a~~<br>~~—~~|VGS= 20V<br>~~a~~|
||Gate-to-Source Reverse Leakage<br>~~—————~~<br>~~pO~~|–––<br>~~|~~<br>~~a~~|–––<br>~~|~~|-100<br>~~—~~<br>||VGS= -20V|
|gfs<br>~~pO~~|Forward Transconductance<br>~~—————~~<br>~~pO~~|37<br>~~a~~|–––|–––|S|VDS= 15V, ID= 12A|
|Qg<br>~~pO~~|Total Gate Charge<br>~~pO~~<br>~~ee~~|–––<br>~~ee~~|34<br>~~ee~~|50<br>~~ee~~|nC|See Fig. 16<br>VDS= 15V<br>VGS= 4.5V<br>ID= 12A|
|Qgs1|Pre-Vth Gate-to-Source Charge<br>~~po~~|–––<br>~~po~~|9.1<br>~~po~~|–––<br>~~po~~|||
|Qgs2|Post-Vth Gate-to-Source Charge<br>~~a~~|–––<br>~~a~~|2.5<br>~~a~~|–––<br>~~a~~|||
|Qgd|Gate-to-Drain Charge<br>~~po~~|–––<br>~~po~~|12<br>~~po~~|–––<br>~~po~~|||
|Qgodr|Gate Charge Overdrive<br>~~a~~|–––<br>~~a~~|10<br>~~a~~|–––<br>~~a~~|||
|Qsw|Switch Charge (Qgs2+ Qgd)<br>~~ee~~|–––<br>~~ee~~|15<br>~~ee~~|–––<br>~~ee~~|||
|Qoss<br>~~po~~|Output Charge<br>~~ee~~<br>~~pT~~<br>~~po~~|–––<br>~~ee~~<br>~~pT~~|21<br>~~ee~~<br>~~pT~~|–––<br>~~ee~~<br>~~pT~~|nC<br>~~pT~~|VDS= 15V, VGS= 0V<br>~~pT~~<br>°|
|td(on)<br>~~po~~|Turn-On DelayTime<br>~~pT~~<br>~~po~~|–––<br>~~pT~~|25<br>~~pT~~|–––<br>~~pT~~|ns<br>~~pT~~|ID= 12A<br>VDD= 15V, VGS= 4.5V<br>Clamped Inductive Load<br>~~pT~~<br>°|
|tr<br>~~po~~|Rise Time<br>~~po~~<br>~~a~~|–––<br>~~a~~|42<br>~~a~~|–––<br>~~a~~|||
|td(off)|Turn-Off DelayTime<br>~~po~~|–––<br>~~po~~|34<br>~~po~~|–––<br>~~po~~|||
|tf|Fall Time<br>~~a~~|–––<br>~~a~~|19<br>~~a~~|–––<br>~~a~~|||
|Ciss|Input Capacitance<br>~~po~~|–––<br>~~po~~|4380<br>~~po~~|–––<br>~~po~~|pF|ƒ= 1.0MHz<br>VGS= 0V<br>VDS= 15V|
|Coss|Output Capacitance<br>~~a~~|–––<br>~~a~~|940<br>~~a~~|–––<br>~~a~~|||
|Crss|Reverse Transfer Capacitance<br>~~ee~~|–––<br>~~ee~~|430<br>~~ee~~|–––<br>~~ee~~|||



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1000 1000<br>VGS VGS<br>SEES tHtt TOP           10V                   4.5V P H TOP           10V                   4.5V<br>                   3.7V                    3.7V<br>                   3.5V                    3.5V<br>100                    3.3V                    3.3V<br>7 a                    3.0V                   2.7V 100 05                    3.0V                   2.7V<br>Me“ae ee el BOTTOM  2.5V | ee O 6 tne BOTTOM  2.5V 4<br>10 e e AAe H<br>2.5V<br>10<br>a 2.5V ear C o<br>1 a O TTER<br>FTA<br>F e r<br>20µs PULSE WIDTH 20µs PULSE WIDTH<br>@Gtinne Tj = 25°C eee Tj = 175°C<br>0.1 1<br>0.1 1 10 100 0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)<br>Fig 1.   Typical Output Characteristics Fig 2.   Typical Output Characteristics<br>1000 2.0<br>e ses ee ID = 30A<br>es ee ee ee es VGS = 10V<br>100 P| TJ = 175°C fLeta ee 1.5 LT ELELELVaEYZ<br>ee ee a ee ee ee ee<br>S e p lane<br>Ee i a 6 ee ee ee eee wa<br>See<br>TJ = 25°C<br>10 a eee e ee ee 1.0 e eae<br>a ee es es es es<br>= p ease<br>| es ee ee ee ee A]<br>VDS = 15V<br>20µs PULSE WIDTH<br>1 ee ee ee 0.5 Oe<br>2.0 3.0 4.0 5.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180<br>VGS, Gate-to-Source Voltage (V) TJ , Junction Temperature (°C)<br>ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A)<br>RDS(on) , Drain-to-Source On Resistance                        (Normalized)<br>)(Α<br>ID, Drain-to-Source Current<br>**----- End of picture text -----**<br>


**Fig 3.** Typical Transfer Characteristics 

**Fig 4.** Normalized On-Resistance vs. Temperature 

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**----- Start of picture text -----**<br>
100000 12<br>VGS   = 0V,       f = 1 MHZ I = 12A<br>Ciss    = Cgs + Cgd,   C ds    SHORTED D VDS= 24V<br>C   = C 10 VDS= 15V<br>rss   gd<br>C  = C + C<br>oss   ds  gd<br>10000 e e eee eee 8 mi a<br>Ciss<br>6<br>ee eeeee<br>Coss 4<br>1000<br>e e | oe<br>Crss 2<br>ee ee<br>ee | 0 Am<br>100<br>0 20 40 60 80<br>1 10 100<br> QG  Total Gate Charge (nC)<br>VDS, Drain-to-Source Voltage (V)<br>Fig 5.   Typical Capacitance vs. Fig 6.   Typical Gate Charge vs.<br>Drain-to-Source Voltage Gate-to-Source Voltage<br>1000.0 10000<br>OPERATION IN THIS AREA<br>LIMITED BY R DS(on)<br>100.0 1000<br>T = 175°C<br>J<br>10.0 100<br>pf f HERSRL<br>100µsec<br>1.0 10<br>TJ = 25°C Tc = 25°C 1msec<br>VGS = 0V Tj = 175°CSingle Pulse 10msec<br>0.1 Lr 1<br>0.0 0.5 1.0 1.5 0.1 1.0 10.0 100.0 1000.0<br>VSD, Source-toDrain Voltage (V) VDS  , Drain-toSource Voltage (V)<br>ISD, Reverse Drain Current (A) ID,  Drain-to-Source Current (A)<br>VGS, Gate-to-Source Voltage (V)<br>C, Capacitance (pF)<br>**----- End of picture text -----**<br>


**Fig 7.** Typical Source-Drain Diode Forward Voltage 

**Fig 8.** Maximum Safe Operating Area 

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**==> picture [438 x 482] intentionally omitted <==**

**----- Start of picture text -----**<br>
160 2.5<br>LIMITED BY PACKAGE<br>2.0<br>120<br>ID = 250µA<br>a .. 1.5 P RRPA  GL E<br>80<br>. Sw<br>1.0 :<br>.<br>x<br>40<br>0.5<br>0<br>0.0<br>25 50 75 100 125 150 175<br>-75 -50 -25 0 25 50 75 100 125 150 175<br> TC , Case Temperature (°C)<br>TJ , Temperature ( °C )<br>Fig 9.   Maximum Drain Current vs. Fig 10.   Threshold Voltage vs. Temperature<br>Case Temperature<br>10<br>a 0<br>1 n l<br>D = 0.50<br>R H<br>O 0.20 ee ea gg seet eeeeee ee ee ee ee<br>0.1 e 0.10 er R1 R1 R2 R2 Ri (°C/W)    Sn  τi (sec) |<br>0.05 τJ τJ τCτ 0.5084      0.000392<br>SS 0.02 ert τ1 τ1 z OH τ2τ2 -— 0.5423      0.011108 H<br>0.01 —e ee) 0.01 | | eHa eetn | tTetT Ci=  T Ci e τi/Rii/Ri T eeee|1 |<br>Notes:<br>SINGLE PULSE 1. Duty Factor D = t1/t2<br>( THERMAL RESPONSE ) 2. Peak Tj = P dm x Zthjc + Tc<br>0.001 pep— | | || f mainep I1<br>1E-006 1E-005 0.0001 0.001 0.01 0.1<br>t1 , Rectangular Pulse Duration (sec)<br>VGS(th) Gate threshold Voltage (V)<br>ID , Drain Current (A)<br>Thermal Response ( Z thJC )<br>**----- End of picture text -----**<br>


**Fig 11.** Maximum Effective Transient Thermal Impedance, Junction-to-Case 

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**==> picture [147 x 116] intentionally omitted <==**

**----- Start of picture text -----**<br>
15V<br>VDS L DRIVER<br>RG D.U.T +<br>- [V][DD]<br>IAS<br>20VVGS<br>tp 0.01Ω<br>|<br>**----- End of picture text -----**<br>


**Fig 12a.** Unclamped Inductive Test Circuit 

**==> picture [164 x 115] intentionally omitted <==**

**----- Start of picture text -----**<br>
V(BR)DSS<br>rs tp<br>/ al<br>/y Ih<br>IAS -<br>**----- End of picture text -----**<br>


**Fig 12b.** Unclamped Inductive Waveforms 

**==> picture [158 x 160] intentionally omitted <==**

**----- Start of picture text -----**<br>
Current Regulator<br>Same Type as D.U.T.<br>50KΩ<br>12V .2µF<br>.3µF<br>LEjt +<br>D.U.T. -VDS<br>VGS<br>3mA<br>wi<br>IG ID<br>Current Sampling Resistors<br>**----- End of picture text -----**<br>


**Fig 13.** Gate Charge Test Circuit 

**==> picture [213 x 197] intentionally omitted <==**

**----- Start of picture text -----**<br>
6000<br>                 I<br>D<br>TOP         8.6A<br>5000<br>               9.6A<br>BOTTOM   12A<br>an n e<br>4000<br>30002000 N BR<br>1000<br>S NE<br>P S<br>0<br>25 50 75 100 125 150 175<br>Starting TJ, Junction Temperature (°C)<br>EAS, Single Pulse Avalanche Energy (mJ)<br>**----- End of picture text -----**<br>


**Fig 12c.** Maximum Avalanche Energy Vs. Drain Current 

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**----- Start of picture text -----**<br>
LD<br>VDS<br>a<br>+<br>VDD -<br>(=<br>D.U.T<br>VGS<br>Pulse Width < 1µs<br>5 Duty Factor < 0.1% *<br>Fig 14a.   Switching Time Test Circuit<br>V<br>DS<br>90%<br>10%<br>V<br>GS<br>td(on) tr td(off) tf<br>**----- End of picture text -----**<br>


**Fig 14a.** Switching Time Test Circuit 

**Fig 14b.** Switching Time Waveforms 

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**==> picture [415 x 164] intentionally omitted <==**

**----- Start of picture text -----**<br>
Driver Gate Drive<br>P.W.<br>D.U.T + {+ P.W. Period ——— + D = —— Period<br>) [©)]    • Circuit Layout Considerations | t V | GS=10V<br> •<br>| =] - LowGround StrayPla I n eductance<br>•   Low Leakage Inductance 2) D.U.T. ISD Waveform<br>+<br>Reverse<br>Recovery Body Diode Forward<br>oi - [l] Current Transformer - ® + Current r Current di/dt NN<br>® D.U.T. VDS Waveform Diode Recoverydv/dt ‘<br>00 +> VDD<br>ma<br>•   Re-Applied<br>•   Driver same type as D.U.T. + Voltage Body Diode  Forward Drop<br>Re ( A •   dvidt controlled by Re Vpp - Inductor Curent<br>•   D.U.T. - Device Under Test es ee<br>Isp controlled by Duty Factor "D" ® Ripple  ≤ 5% ISD<br>**----- End of picture text -----**<br>


**Fig 15.** 

Recovery dv/dt Test Circuit or N-Channel HEXFET ® Power MOSFETs 

**==> picture [245 x 198] intentionally omitted <==**

**----- Start of picture text -----**<br>
Id<br>Vds f'<br>1 Vgs<br>I<br>1<br>1<br>1<br>1<br>I<br>1<br>|<br>H \<br>Vgs(th) !! \\<br>! \<br>! \<br>H \<br>H \<br>1 H ! ' |<br>><1) o t<br>Qgs1 Qgs2 Qgd Qgodr<br>**----- End of picture text -----**<br>


**Fig 16.** Gate Charge Waveform 

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## **Power MOSFET Selection for Non-Isolated DC/DC Converters** 

## **Control FET** 

## **Synchronous FET** 

The power loss equation for Q2 is approximated by; 

_P = P + P + P + P loss conduction switching drive output_ 

This can be expanded and approximated by; 

**==> picture [207 x 109] intentionally omitted <==**

**==> picture [188 x 102] intentionally omitted <==**

*dissipated primarily in Q1. 

For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant.  Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. 

The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of  Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Q /Q must be minimized to reduce the gd gs1 potential for Cdv/dt turn on. 

Figure A:  Qoss Characteristic 

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8 

**Note: For the most current drawing please refer to IR website at http://www.irf.com/package/** www.irf.com 

9 

**Note: For the most current drawing please refer to IR website at http://www.irf.com/package/** 10 

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**==> picture [282 x 242] intentionally omitted <==**

**----- Start of picture text -----**<br>
TR TRR TRL<br>eeooooo\ | oeoo/4<br>16.3 ( .641 ) 16.3 ( .641 )<br>15.7 ( .619 ) 15.7 ( .619 )<br>CECE, Oo) ,<br>12.1 ( .476 ) FEED DIRECTION 8.1 ( .318 ) FEED DIRECTION<br>11.9 ( .469 ) 7.9 ( .312 )<br>NOTES :<br>1.  CONTROLLING DIMENSION : MILLIMETER.<br>2.  ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).<br>3.  OUTLINE CONFORMS TO EIA-481 & EIA-541.<br>|   13 INCH<br>16 mm<br>|X a<br>**----- End of picture text -----**<br>


NOTES : 1. OUTLINE CONFORMS TO EIA-481. 

o) Repetitive rating;  pulse width limited by @ Calculated continuous current based on maximum allowable max. junction temperature. junction temperature. Package limitation current is 30A. @© Starting TJ = 25°C, L = 20mH, RG = 25Ω, When mounted on 1" square PCB (FR-4 or G-10 Material). IAS = 12A. For recommended footprint and soldering techniques refer to ® Pulse width ≤ 400µs; duty cycle ≤ 2%. application note #AN-994. 

**Note: For the most current drawing please refer to IR website at http://www.irf.com/package/** 

Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. 

**IR WORLD HEADQUARTERS:** 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 

TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information **.** 04/2008 

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