# Power MOSFET, N Channel, 100 V, 180 A, 0.0034 ohm, TO-262, Through Hole

![Product image](https://novapart.co/image/farnell:2839501/)

**URL**: https://novapart.co/products/IRLSL4030PBF/power-mosfet-n-channel-100-v-180-a-00034-ohm-to
**SKU**: IRLSL4030PBF
**Manufacturer**: INFINEON
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.4700
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | HEXFET |
| Power Dissipation | 370W |
| Transistor Mounting | Through Hole |
| Transistor Polarity | N Channel |
| Power Dissipation Pd | 370W |
| Rds(On) Test Voltage | 10V |
| On Resistance Rds(On) | 0.0034ohm |
| Transistor Case Style | TO-262 |
| Drain Source Voltage Vds | 100V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 180A |
| Drain Source On State Resistance | 0.0034ohm |
| Gate Source Threshold Voltage Max | 2.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2839501/)

PD97370 

## IRLS4030PbF IRLSL4030PbF 

## **Applications** 

DC Motor Drive 

High Efficiency Synchronous Rectification in SMPS Uninterruptible Power Supply High Speed Power Switching Hard Switched and High Frequency Circuits 

## **Benefits** 

Optimized for Logic Level Drive Very Low RDS(ON) at 4.5V VGS Superior R*Q at 4.5V VGS Improved  Gate, Avalanche and Dynamic  dV/dt Ruggedness 

> . Fully Characterized Capacitance and Avalanche SOA 

Enhanced body diode dV/dt and dI/dt Capability Lead-Free 

HEXFET ® Power MOSFET 

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D VDSS 100V<br>RDS(on)   typ. 3.4m Ω<br>G               max. 4.3m Ω<br>S ID  180A<br>**----- End of picture text -----**<br>


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G [DS]<br>G [DS]<br>D [2] Pak TO-262<br>IRLS4030PbF IRLSL4030bF<br>**----- End of picture text -----**<br>


|**G**|**D**|**S**|
|---|---|---|
|Gate|Drain|Source|



|**Absolute Maximum Ratings**<br>**Symbol**<br>**Parameter**<br>**Units**<br>ID@ TC= 25°C<br>Continuous Drain Current,VGS@ 10V<br>ID@ TC= 100°C<br>Continuous Drain Current,VGS@ 10V<br>A<br>IDM<br>Pulsed Drain Current<br>PD@TC= 25°C<br>Maximum Power Dissipation<br>W<br>**Max.**<br>180<br>130<br>730<br>370<br>~~TF~~<br>~~oOo*FOo7~~<br>~~es~~<br>~~———~~<br>~~Oe~~<br>~~es~~<br>~~©~~<br>~~a~~|
|---|
|Linear DeratingFactor<br>W/°C<br>VGS<br>Gate-to-Source Voltage<br>V<br>dv/dt<br>Peak Diode Recovery<br>V/ns<br>TJ<br>Operating Junction and<br>°C<br>21<br>-55  to + 175<br>± 16<br>2.5<br>~~a OO~~<br>~~es~~<br>~~a~~<br>~~Ca~~|
|TSTG<br>Storage Temperature Range|
|Soldering Temperature, for 10 seconds<br>300|
|(1.6mm from case)|
|**Avalanche Characteristics**|
|EAS(Thermallylimited)<br>Single Pulse Avalanche Energy<br>mJ<br>IAR<br>Avalanche Current<br>A<br>EAR<br>Repetitive Avalanche Energy<br>mJ<br>**Thermal Resistance**<br>305<br>See Fig. 14, 15, 22a, 22b<br>~~es~~<br>~~I nn~~<br>~~(~~<br>~~ee~~<br>~~eee~~<br>~~a~~<br>~~|~~|
|**Symbol**<br>**Parameter**<br>**Typ.**<br>**Max.**<br>**Units**<br>RθJC<br>Junction-to-Case<br>–––<br>0.40<br>°C/W<br>RθJA<br>Junction-to-Ambient(PCB Mount)<br>–––<br>40<br>~~LO~~<br>~~es~~<br>~~>~~<br>~~S$~~|



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02/12/09 

**Static @ TJ = 25°C (unless otherwise specified)** 

|**Symbol**<br>**Parameter**<br>**Min. Typ. Max. Units**<br>**Conditions**<br>~~a QQ~~|
|---|
|V(BR)DSS<br>Drain-to-Source Breakdown Voltage<br>100<br>–––<br>–––<br>V<br>VGS= 0V, ID= 250µA<br>~~a Qs~~|
|∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient<br>–––<br>0.10<br>–––<br>V/°C<br>RDS(on)<br>Static Drain-to-Source On-Resistance<br>–––<br>3.4<br>4.3<br>mΩ<br>–––<br>3.6<br>4.5<br>VGS(th)<br>Gate Threshold Voltage<br>1.0<br>–––<br>2.5<br>V<br>IDSS<br>Drain-to-Source Leakage Current<br>–––<br>–––<br>20<br>–––<br>–––<br>250<br>IGSS<br>Gate-to-Source Forward Leakage<br>–––<br>–––<br>100<br>Gate-to-Source Reverse Leakage<br>–––<br>–––<br>-100<br>RG(int)<br>Internal Gate Resistance<br>–––<br>2.1<br>–––<br>Ω<br>VGS= 4.5V, ID= 92A<br>µA<br>nA<br>Reference to 25°C, ID= 5mA<br>VGS= 10V, ID= 110A<br>VDS= VGS, ID= 250µA<br>VDS= 100V, VGS= 0V<br>VDS= 100V, VGS= 0V, TJ= 125°C<br>VGS= 16V<br>VGS= -16V<br>~~a~~<br>~~Qs DN~~<br>~~©~~<br>~~ee ee~~<br>~~eee~~<br>~~a~~<br>~~a Qs~~<br>~~ee~~<br>~~a~~<br>~~a a~~<br>~~eeee~~<br>~~——————————_——~~<br>~~QS~~<br>~~GO Ge~~<br>~~a~~<br>~~Qs~~|
|**Dynamic @ TJ = 25°C (unless otherwise specified)**|
|**Symbol**<br>**Parameter**<br>**Min. Typ. Max. Units**<br>**Conditions**<br>~~aQs~~|
|gfs<br>Forward Transconductance<br>320<br>–––<br>–––<br>S<br>VDS= 25V, ID= 110A<br>~~a Qs~~|
|Qg<br>Total Gate Charge<br>–––<br>87<br>130<br>ID= 110A<br>~~a ee~~|
|Qgs<br>Gate-to-Source Charge<br>–––<br>27<br>–––<br>Qgd<br>Gate-to-Drain("Miller")Charge<br>–––<br>45<br>–––<br>Qsync<br>Total Gate Charge Sync. (Qg- Qgd)<br>–––<br>42<br>–––<br>td(on)<br>Turn-On DelayTime<br>–––<br>74<br>–––<br>nC<br>VGS= 4.5V<br>VDD= 65V<br>ID= 110A, VDS=0V, VGS= 4.5V<br>VDS= 50V<br>~~a ee~~<br>~~a ee~~<br>~~®~~<br>~~a QQ(ee~~<br>~~a ee~~|
|tr<br>Rise Time<br>–––<br>330<br>–––<br>td(off)<br>Turn-Off DelayTime<br>–––<br>110<br>–––<br>ns<br>ID= 110A<br>RG= 2.7Ω<br>~~a ee~~<br>~~a ee~~|
|tf<br>Fall Time<br>–––<br>170<br>–––<br>VGS= 4.5V<br>~~a a~~<br>~~®~~|
|Ciss<br>Input Capacitance<br>–––<br>11360<br>–––<br>Coss<br>Output Capacitance<br>–––<br>670<br>–––<br>Crss<br>Reverse Transfer Capacitance<br>–––<br>290<br>–––<br>Cosseff.(ER)<br>Effective Output Capacitance(EnergyRelated)<br>–––<br>760<br>–––<br>Cosseff.(TR)<br>Effective Output Capacitance(Time Related)<br>–––<br>1140<br>–––<br>**Diode Characteristics**<br>pF<br>VGS= 0V<br>VDS= 50V<br>ƒ= 1.0MHz<br>VGS= 0V,VDS= 0V to 80V<br>VGS= 0V,VDS= 0V to 80V<br>~~esRG~~<br>~~esRG~~<br>~~esRG~~<br>~~es~~<br>~~es~~|
|S<br>D<br>G<br>**Symbol**<br>**Parameter**<br>**Min. Typ. Max. Units**<br>IS<br>Continuous Source Current<br>(BodyDiode)<br>ISM<br>Pulsed Source Current<br>(BodyDiode)<br>VSD<br>Diode Forward Voltage<br>–––<br>–––<br>1.3<br>V<br>trr<br>Reverse Recovery Time<br>–––<br>50<br>–––<br>TJ= 25°C<br>VR= 85V,<br>–––<br>60<br>–––<br>TJ= 125°C<br>IF= 110A<br>Qrr<br>Reverse Recovery Charge<br>–––<br>88<br>–––<br>TJ= 25°C<br>di/dt = 100A/µs<br>–––<br>130<br>–––<br>TJ= 125°C<br>ns<br>nC<br>180<br>730<br>A<br>–––<br>–––<br>–––<br>–––<br>TJ= 25°C,IS= 110A,VGS= 0V<br>integral reverse<br>p-njunction diode.<br>MOSFET symbol<br>showing  the<br>**Conditions**<br>~~peOT~~<br>~~reee~~<br>~~a~~<br>~~a~~<br>~~|~~<br>.<br>~~a~~|
|IRRM<br>Reverse RecoveryCurrent<br>–––<br>3.3<br>–––<br>A<br>TJ= 25°C<br>ton<br>Forward Turn-On Time<br>Intrinsic turn-on time is negligible(turn-on is dominated byLS+LD)<br>~~es~~<br>~~es~~|



Repetitive rating;  pulse width limited by max. junction temperature. 

Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 

@ Limited by TJmax, starting TJ = 25°C, L = 0.05mH © Coss eff. (ER) is a fixed capacitance that gives the same energy as RG = 25 Ω , IAS = 110A, VGS =10V. Part not recommended for use 

Coss while VDS is rising from 0 to 80% VDSS. 

above this value . 

@ When mounted on 1" square PCB (FR-4 or G-10 Material). For ® ISD ≤ 110A, di/dt ≤ 1330A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. recommended   footprint and soldering techniquea refer to applocation ® Pulse width ≤ 400µs; duty cycle ≤ 2%. note # AN-  994 echniques refer to application note #AN-994. 

θ 

__ θ JC value shown is at time zero. 

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1000 1000<br>VGS VGS<br>See,etisiee sine TOP           15V10V Saini vanitiesF TOP           15V10V<br>8.0V 8.0V<br>4.5V 4.5V<br>3.5V 3.5V<br>ai 2st aa 3.0V Sails ieee 3.0V<br>100 2.7V 2.7V<br>BOTTOM 2.5V BOTTOM 2.5V<br>e e LL<br>100<br>stint o |a<br>10 2.5V<br>r Eeaiheata e my /Ml A r<br>2.5V<br>≤ 60µs PULSE WIDTH J ≤ 60µs PULSE WIDTH<br>Tj = 25°C Tj = 175°C<br>1 COM, Sit [tr] lll | I 10 “ANI |<br>0.1 1 10 100 1000 0.1 1 10 100 1000<br>VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)<br>Fig 1.   Typical Output Characteristics Fig 2.   Typical Output Characteristics<br>1000 2.5<br>ID = 110A<br>VGS = 10V<br>|ee| rr pp> 2.0 HYYA<br>100 TJ = 175°C<br>w/ e 1.5 1) LAT |<br>TJ = 25°C<br>f/ f | 1.0 H ELA<br>10<br>e o E AT<br>0.5<br>A f fy e T LEELA<br>VDS = 50V<br>≤ 60µs PULSE WIDTH PEELE<br>1.0 [ pt 0.0 LEE ERLE<br>1 2 3 4 5 -60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Junction Temperature (°C)<br>VGS, Gate-to-Source Voltage (V)<br>Fig 4.   Normalized On-Resistance vs. Temperature<br>Fig 3.   Typical Transfer Characteristics<br>100000 5.0<br>VGS   = 0V,       f = 1 MHZ<br>Ciss    = C gs + Cgd,  C ds SHORTED ID= 110AD= 110A= 110A VDS= 80VDS= 80V= 80V<br>: Crss    = Cgd  4.0 S VDSDS y = 50V<br>Coss   = Cds + Cgd<br>10000 e s Ciss or<br>3.0<br>in aa<br>Coss<br>ah PT HPFH 2.0 P f] | ff<br>1000<br>e e Crss ee<br>eT lil 1.0 r i<br>ener ee<br>ee Senn<br>100 ETE enilllmmimmncttlEET 0.0 ry TT]<br>1 10 100 0 20 40 60 80 100<br>VDS, Drain-to-Source Voltage (V)  QG,  Total Gate Charge (nC)<br>ID, Drain-to-Source Current (A)<br>ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A)<br>C, Capacitance (pF)<br>VGS, Gate-to-Source Voltage (V)<br>RDS(on) , Drain-to-Source On Resistance                        (Normalized)<br>**----- End of picture text -----**<br>


**Fig 4.** Normalized On-Resistance vs. Temperature 

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5.0<br>ID= 110AD= 110A= 110A VDS= 80VDS= 80V= 80V<br>4.0 S VDSDS y = 50V<br>3.0<br>aa<br>2.0 P f] | ff<br>1.0 r i<br>0.0 ry TT]<br>0 20 40 60 80 100<br> QG,  Total Gate Charge (nC)<br>VGS, Gate-to-Source Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 5.** Typical Capacitance vs. Drain-to-Source Voltage 

**Fig 6.** Typical Gate Charge vs. Gate-to-Source Voltage 

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1000<br>——<br>TJ = 175°C<br>100<br>ae e aa a na<br>aw ee TJ = 25°C ee ee ees<br>10<br>e s or<br>e y a ee<br>ae<br>1 oes ee a a ee<br>f y | |<br>a<br>VGS = 0V<br>0.1 2 Hh ee  f}—+—— =<br>0.0 0.5 1.0 1.5 2.0 2.5<br>VSD, Source-to-Drain Voltage (V)<br>ISD, Reverse Drain Current (A)<br>**----- End of picture text -----**<br>


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10000 =e OPERATION IN THIS AREA  eee<br>LIMITED BY RDS(on)<br>1000<br>Ty<br>100µsec tit<br>Sectieac t t pe<br>100 PAS<br>SSS |<br>10msec<br>ae 1msec e e<br>ae DC oe a<br>10<br>A SI esi s |<br>Tc = 25°C<br>e k ee e eet , Gene<br>Tj = 175°C<br>1 PRA Single Pulse fe<br>0 1 10 100 1000<br>VDS, Drain-to-Source Voltage (V)<br>Fig 8.   Maximum Safe Operating Area<br>125<br>Id = 5mA<br>120<br>T T<br>115 L EE<br>ar<br>110 P ee7777<br>105<br>B EDZARRRREEE<br>100<br>O LE<br>95<br>Z EEE<br>P EEL<br>90 TTP EEE EEE<br>-60 -40 -20 0 20 40 60 80 100120140160180120140160180140160180160180180<br>TJ , Temperature ( °C )<br>Fig 10.   Drain-to-Source Breakdown Voltage<br>V(BR)DSS, Drain-to-Source Breakdown Voltage (V)<br>ID,  Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 7.** Typical Source-Drain Diode Forward Voltage 

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200 125<br>Id = 5mA<br>180<br>120<br>160 2 T T<br>140 i 115 L EE<br>NX ar<br>120<br>100 H ees 110 P ee7777<br>105<br>80 F Y B EDZARRRREEE<br>60 100<br>40 P N O LE<br>95<br>20 P o Z EEE<br>a P EEL<br>0 90 TTP EEE EEE<br>25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180120140160180140160180160180180<br> TC , Case Temperature (°C) TJ , Temperature ( °C )<br>Fig 9.   Maximum Drain Current vs. Fig 10.   Drain-to-Source Breakdown Voltage<br>Case Temperature<br>4.5 1400<br>ID<br>4.0<br>1200 TOP         17A<br>3.5 o e a nt 40A<br>BOTTOM 110A<br>1000<br>3.0<br>2.5 800<br>C oE N f<br>2.0<br>600<br>C TT N TEEEL<br>1.5<br>400<br>1.0 o ae5 TT<br>200<br>0.5<br>0.0 PAWann 4am 0 S TET P NU PRS N IT SST<br>-20 0 20 40 60 80 100 120 25 50 75 100 125 150 175<br>Starting TJ , Junction Temperature (°C)<br>VDS, Drain-to-Source Voltage (V)<br>EAS , Single Pulse Avalanche Energy (mJ)<br>V(BR)DSS, Drain-to-Source Breakdown Voltage (V)<br>Energy (µJ)<br>ID,  Drain Current (A)<br>**----- End of picture text -----**<br>


**Fig 11.** Typical COSS Stored Energy 

**Fig 12.** Maximum Avalanche Energy vs. DrainCurrent 

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1<br>TT TT CE<br>D = 0.50<br>0.1 0.20<br>0.10<br>0.05<br>0.01 AE 0.010.02 ET)a τ J τ J τ PE 1 τ 1 R1 R1 τ 2 τ R22 R2 R τ 33R τ 33 τ C τ Ri (°C/W)   0.0477    0.0000710.1631    0.000881  τ i (sec) i<br>Ci=  τ i / Ri 0.1893    0.007457<br>0.001 Ci τ i / Ri<br>SINGLE PULSE Notes:<br>( THERMAL RESPONSE )<br>1. Duty Factor D = t1/t2<br>2. Peak Tj = P dm x Zthjc + Tc<br>0.0001<br>1E-006 1E-005 0.0001 0.001 0.01 0.1<br>t1 , Rectangular Pulse Duration (sec)<br>Fig 13.   Maximum Effective Transient Thermal Impedance, Junction-to-Case<br>1000<br>Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche<br>pulsewidth, tav, assuming  ∆ Tj = 150°C and<br>100 we IP Tstart =25°C (Single Pulse)<br>0.01<br>0.05<br>SS LE TH<br>10 0.10<br>e SVeeeeOr Spee fTee Bailloo<br>1<br>Allowed avalanche Current vs avalanche<br>pulsewidth, tav, assuming  ∆Τ j = 25°C and<br>0.1 a Tstart = 150°C. OOs| et<br>1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01<br>tav (sec)<br>Fig 14.   Typical Avalanche Current vs.Pulsewidth<br>350 Notes on Repetitive Avalanche Curves , Figures 14, 15:<br>TOP          Single Pulse<br>(For further info, see AN-1005 at www.irf.com)<br>300 BOTTOM   1.0% Duty Cycle 1. Avalanche failures assumption:<br>ID = 110A Purely a thermal phenomenon and failure occurs at a temperature far in<br>S e excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type.<br>250 N EL 2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded.<br>3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.<br>200 N NTP 4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse.<br>5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase<br>during avalanche).<br>150<br>B RNGNGHEEEEE 6. Iav = Allowable avalanche current.<br>7.  ∆ T = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as<br>100 L ENNIE 25°C in Figure 14, 15).<br>tav = Average time in avalanche.<br>50 D = Duty cycle in avalanche =  tav ·f<br>E LT ENN<br>ZthJC(D, tav) = Transient thermal resistance, see Figures 13)<br>D e NSNG<br>0<br>PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) = T/ ZthJCthJC<br>25 50 75 100 125 150 175<br>Iav =av == 2 A T/ [1.3·BV·Zth]th]]<br>Starting TJ , Junction Temperature (°C) EAS (AR) = PD (ave)·tavAS (AR) = PD (ave)·tav = PD (ave)·tavD (ave)·tav·tavav<br>EAR , Avalanche Energy (mJ)<br>Thermal Response ( Z  thJC ) °C/W<br>Avalanche Current (A)<br>**----- End of picture text -----**<br>


- Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type. 

2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded. 

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 

4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse. 

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 

7. ∆ T = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as 25°C in Figure 14, 15). 

**PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) = T/ ZthJCthJC Iav =av == 2** A **T/ [1.3·BV·Zth]th]] EAS (AR) = PD (ave)·tavAS (AR) = PD (ave)·tav = PD (ave)·tavD (ave)·tav·tavav** 

**Fig 15.** Maximum Avalanche Energy vs. Temperature 

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2.5<br>2.0<br>E sqnel<br>LSSSAU EPRPE<br>1.5 DANA<br>ID = 250µA LPR<br>1.0 ID = 1.0mA (2naNNG<br>ID = 1.0A<br>BREENN<br>0.5<br>P y yt PToNyyy yA<br>0.0<br>PEE EEE TY YY<br>-75 -50 -25 0 25 50 75 100 125 150 175<br>TJ , Temperature ( °C )<br>VGS(th), Gate threshold Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 16.** Threshold Voltage vs. Temperature 

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35<br>IF = 110A<br>30 V R = 85V | | | 7<br>TJ = 25°C<br>a<br>25<br>TJ = 125°C<br>20<br>|<br>|  LA<br>15<br>ly |<br>e T<br>10<br>4 mm<br>5 ,<br>0<br>t t [tt]<br>0 200 400 600 800 1000<br>diF /dt (A/µs)<br>IRRM (A)<br>**----- End of picture text -----**<br>


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40<br>IF = 73A<br>35<br>VR = 85V<br>30 TJ = 25°C<br>TT<br>TJ = 125°C<br>25 aa<br>/<br>20<br>_ | 7|<br>a ae<br>15 e a<br>10<br>5<br>o 4 A<br>0<br>pot tt<br>0 200 400 600 800 1000<br>diF /dt (A/µs)<br>Fig. 17 - Typical Recovery Current vs. di;/dt<br>800<br>IF = 73A<br>720 ae<br>VR = 85V<br>640 T J = 25°C ee ee<br>560 TJ = 125°C<br>480 ae<br>400 eT<br>C e<br>320<br>A a<br>240<br>S Z<br>P et]<br>160 i<br>80<br>|<br>0 200 400 600 800 1000<br>diF /dt (A/µs)<br>IRRM (A)<br>QRR (A)<br>**----- End of picture text -----**<br>


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880<br>IF = 110A | ||<br>800<br>VR = 85V ae<br>720 ee ed<br>TJ = 25°C a<br>640 T J = 125°C |ee ey,<br>560 Z|<br>e e<br>480<br>| ae<br>400 | teZ|<br>e a aa<br>320<br>240 p e |<br>P od |<br>160<br>| yi | | |<br>80<br>0 200 400 600 800 1000<br>diF /dt (A/µs)<br>QRR (A)<br>**----- End of picture text -----**<br>


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**==> picture [416 x 343] intentionally omitted <==**

**----- Start of picture text -----**<br>
Driver Gate Drive<br>P.W.<br>Period D =<br>+ P.W. Period<br>D.U.T {$$ | ————| —— |t<br>VGS=10V<br>) ©)    •  Circuit Layout Considerations |<br> •<br>| —| - LowGround StrayPla I n eductance<br> •   Low Leakage Inductance ® D.U.T. ISD Waveform<br>+<br>Reverse<br>Recovery Body Diode Forward<br>0) - a = Current Transformer - ® + Current r Current = di/dt /<br>00 ® D.U.T. VDS Waveform Diode Recovery =<br>dv/dt ‘ VDD<br>ma<br>•   Re-Applied<br>•   Driver same type as D.U.T. + Voltage Body Diode  Forward Drop<br>Re ( aA •   dv/dt controlled by Rg Vpp -<br>•<br>D.U.T. - Device Under Test es ae<br>Ripple  ≤ 5% ISD<br>Isp controlled by Duty Factor "D" iO) t<br>* Veg = 5V for Logic Level Devices<br>Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel<br>HEXFET ® Power MOSFETs<br>V(BR)DSS<br>15V < tp ><br>VDS L DRIVER<br>RG D.U.T +<br>- [V][DD]<br>IAS A<br>20VVGS<br>tp 0.01 Ω IAS<br>**----- End of picture text -----**<br>


**Fig 22a.** Unclamped Inductive Test Circuit 

## **Fig 22b.** Unclamped Inductive Waveforms 

**==> picture [130 x 58] intentionally omitted <==**

**----- Start of picture text -----**<br>
+<br>-<br>≤ 1  us<br>≤ 0.1 %<br>**----- End of picture text -----**<br>


## **Fig 23a.** Switching Time Test Circuit 

**==> picture [134 x 132] intentionally omitted <==**

**----- Start of picture text -----**<br>
Current Regulator<br>Same Type as D.U.T.<br>50K Ω<br>12V .2 µ F<br>.3 µ F<br>+<br>D.U.T. -VDS<br>VGS<br>3mA<br>WAN IG ID<br>Current Sampling Resistors<br>**----- End of picture text -----**<br>


**Fig 24a.** Gate Charge Test Circuit 

**==> picture [192 x 121] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDS<br>90%<br>\<br>10%<br>VGS |«le ys| |<br>td(on) tr td(off) tf<br>**----- End of picture text -----**<br>


**==> picture [164 x 10] intentionally omitted <==**

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Fig 23b.   Switching Time Waveforms<br>**----- End of picture text -----**<br>


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Id<br>Vds<br>Vgs<br>Vgs(th)<br>t [pie] g [p] [i] [e] w i e > !<br>Qgs1 Qgs2 Qgd Qgodr<br>**----- End of picture text -----**<br>


**Fig 24b.** Gate Charge Waveform 

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## TO-262 Package Outline 

Dimensions are shown in millimeters (inches) 

## TO-262 Part Marking Information 

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Dimensions are shown in millimeters (inches) 

**==> picture [454 x 192] intentionally omitted <==**

**----- Start of picture text -----**<br>
TRR<br>1.60 (.063)<br>1.50 (.059)<br>1.60 (.063)<br>4.10 (.161)<br>1.50 (.059)<br>3.90 (.153) 0.368 (.0145)<br>0.342 (.0135)<br>FEED DIRECTION 1.85 (.073) 11.60 (.457)<br>1.65 (.065) 11.40 (.449) 24.30 (.957)<br>15.42 (.609)<br>23.90 (.941)<br>15.22 (.601)<br>TRL<br>1.75 (.069)<br>10.90 (.429) 1.25 (.049)<br>4.72 (.136)<br>10.70 (.421)<br>16.10 (.634) 4.52 (.178)<br>15.90 (.626)<br>**----- End of picture text -----**<br>


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FEED DIRECTION<br>**----- End of picture text -----**<br>


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13.50 (.532) 27.40 (1.079)<br>12.80 (.504) 23.90 (.941)<br>4<br>/\\/\<br>330.00<br>60.00 (2.362)<br>(14.173)       MIN.<br>  MAX.<br>\\_/ \ 4% /<br>30.40 (1.197)<br>NOTES :       MAX.<br>1.   COMFORMS TO EIA-418.<br>26.40 (1.039) 4<br>2.   CONTROLLING DIMENSION: MILLIMETER. 24.40 (.961)<br>3.   DIMENSION MEASURED @ HUB.<br>3<br>**----- End of picture text -----**<br>


4.   INCLUDES FLANGE DISTORTION @ OUTER EDGE. 

Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. 

**IR WORLD HEADQUARTERS:** 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information **.** 02/09 

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## Links

- [View this product on Novapart](https://novapart.co/products/IRLSL4030PBF/power-mosfet-n-channel-100-v-180-a-00034-ohm-to)
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- [Supplier page](https://es.farnell.com/en-ES/infineon/irlsl4030pbf/mosfet-n-ch-100v-180a-to-262/dp/2839501)
---

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