# Power MOSFET, N Channel, 60 V, 270 A, 2400 µohm, TO-263 (D2PAK), Surface Mount

![Product image](https://novapart.co/image/farnell:2577183/)

**URL**: https://novapart.co/products/IRLS3036TRLPBF/power-mosfet-n-channel-60-v-270-a-2400-ohm-to-263
**SKU**: IRLS3036TRLPBF
**Manufacturer**: INFINEON
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.6400
**Stock**: 1000+
**Lead Time**: 99 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:270A; Drain Source Voltage Vds:60V; On Resistance Rds(on):0.0019ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:2.5V;

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | HEXFET |
| Qualification | - |
| Power Dissipation | 380W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-263 (D2PAK) |
| Drain Source Voltage Vds | 60V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 270A |
| Drain Source On State Resistance | 2400µohm |
| Gate Source Threshold Voltage Max | 2.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2577183/)

po 97358 IRLS3036PbF IRLSL3036PbF HEXFET ® Power MOSFET 

## **Applications** 

DC Motor Drive D **VDSS 60V** ° High Efficiency Synchronous Rectification in SMPS ~~ee eee~~ **RDS(on)   typ. 1.9m** Ω Uninterruptible Power Supply 3 ~~°°~~ High Speed Power SwitchingHard Switched and High Frequency Circuits G ~~FF~~ **max.ID (Silicon Limited) 270A2.4m** Ω ~~ee eon~~ S ~~ee~~ **ID (Package Limited) 195A Benefits** Optimized for Logic Level Drive Very Low RDS(ON) at 4.5V VGS Superior R*Q at 4.5V VGS Improved  Gate, Avalanche and Dynamic  dV/dt Ruggedness G[DS] G[DS] Fully Characterized Capacitance and Avalanche D[2] Pak TO-262 SOA IRLS3036PbF IRLSL3036PbF 

## **Benefits** 

Fully Characterized Capacitance and Avalanche SOA 

Enhanced body diode dV/dt and dI/dt Capability Lead-Free 

|**G**|**D**|**S**|
|---|---|---|
|Gate|Drain|Source|



## **Absolute Maximum Ratings** 

|**Symbol**|**Parameter**<br>**Units**<br>**Max.**|
|---|---|
|ID@ TC= 25°C<br>ID@ TC= 100°C<br>ID@ TC= 25°C<br>IDM<br>PD@TC= 25°C|Continuous Drain Current,VGS@ 10V(Silicon Limited)<br>Continuous Drain Current,VGS@ 10V(Silicon Limited)<br>Continuous Drain Current,VGS@ 10V(Package Limited)<br>Pulsed Drain Current<br>Maximum Power Dissipation<br>W<br>A<br>380<br>270<br>190<br>1100<br>195<br>~~a~~<br>~~a~~<br>~~a~~<br>~~————_—_————— ae~~<br>~~a~~|
||Linear DeratingFactor<br>W/°C<br>2.5<br>~~a~~|
|VGS<br>dv/dt<br>TJ<br>TSTG|Gate-to-Source Voltage<br>V<br>Peak Diode Recovery<br>V/ns<br>Operating Junction and<br>Storage Temperature Range<br>Soldering Temperature, for 10 seconds<br>(1.6mm from case)<br>°C<br>8.0<br>±16<br>-55  to + 175<br>300<br>~~GO~~<br>~~es re~~|
|**Avalanche Characteristics**||
|EAS(Thermallylimited)<br>Single Pulse Avalanche Energy<br>mJ<br>IAR<br>Avalanche Current<br>A<br>EAR<br>Repetitive Avalanche Energy<br>mJ<br>See Fig. 14, 15, 22a, 22b<br>290<br>~~a~~<br>~~——————~~||
|**Thermal Resistance**||
|**Symbol**|**Parameter**<br>**Typ.**<br>**Max.**<br>**Units**|
|RθJC|Junction-to-Case<br>–––<br>0.40<br>°C/W<br>11|
|RθJA|Junction-to-Ambient(PCB Mount,steadystate)<br>–––<br>40<br>~~7~~|



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**Static @ TJ = 25°C (unless otherwise specified)** 

|**Symbol**|**Parameter**<br>**Min. Typ. Max. Units**<br>**Conditions**|
|---|---|
|V(BR)DSS<br>∆V(BR)DSS/∆TJ<br>VGS(th)<br>IDSS<br>IGSS<br>RG(int)<br>RDS(on)|Drain-to-Source Breakdown Voltage<br>60<br>–––<br>–––<br>V<br>Breakdown Voltage Temp. Coefficient<br>–––<br>0.061<br>–––<br>V/°C<br>–––<br>1.9<br>2.4<br>–––<br>2.2<br>2.8<br>Gate Threshold Voltage<br>1.0<br>–––<br>2.5<br>V<br>Drain-to-Source Leakage Current<br>–––<br>–––<br>20<br>–––<br>–––<br>250<br>Gate-to-Source Forward Leakage<br>–––<br>–––<br>100<br>Gate-to-Source Reverse Leakage<br>–––<br>–––<br>-100<br>Internal Gate Resistance<br>–––<br>2.0<br>–––<br>Ω<br>VGS= -16V<br>VGS= 0V, ID= 250µA<br>Reference to 25°C, ID= 5mA<br>VGS= 10V, ID= 165A<br>VDS= VGS, ID= 250µA<br>VDS= 60V, VGS= 0V<br>VDS= 60V, VGS= 0V, TJ= 125°C<br>VGS= 16V<br>µA<br>nA<br>Static Drain-to-Source On-Resistance<br>VGS= 4.5V, ID= 140A<br>mΩ<br>~~GN~~<br>~~GO~~<br>~~Gs~~<br>~~OO”~~<br>~~ce~~<br>~~eee Oe~~<br>~~ee~~<br>~~||~~<br>~~GN~~<br>~~DG~~<br>~~Ne~~<br>~~ee eee~~<br>~~A~~<br>~~——————~~<br>~~eS~~<br>~~GCC~~<br>~~GG~~<br>~~DO~~|
|**Dynamic @ TJ = 25°C (unless otherwise specified)**||
|**Symbol**|**Parameter**<br>**Min. Typ. Max. Units**<br>**Conditions**|
|gfs<br>Qg|Forward Transconductance<br>340<br>–––<br>–––<br>S<br>Total Gate Charge<br>–––<br>91<br>140<br>VDS= 10V, ID= 165A<br>ID= 165A<br>~~GO~~<br>~~eG~~<br>~~a~~|
|Qgs<br>Qgd<br>Qsync<br>td(on)|Gate-to-Source Charge<br>–––<br>31<br>–––<br>Gate-to-Drain("Miller")Charge<br>–––<br>51<br>–––<br>Total Gate Charge Sync. (Qg- Qgd)<br>–––<br>40<br>–––<br>Turn-On DelayTime<br>–––<br>66<br>–––<br>VDS= 30V<br>nC<br>VGS= 4.5V<br>VDD= 39V<br>ID= 165A, VDS=0V, VGS= 4.5V<br>~~a~~<br>~~a~~<br>®<br>~~GO~~<br>~~OC~~<br>~~a~~|
|tr<br>td(off)|Rise Time<br>–––<br>220<br>–––<br>Turn-Off DelayTime<br>–––<br>110<br>–––<br>ns<br>ID= 165A<br>RG= 2.1Ω<br>~~a~~<br>~~a~~|
|tf|Fall Time<br>–––<br>110<br>–––<br>VGS= 4.5V<br>~~a~~<br>®|
|Ciss|Input Capacitance<br>–––<br>11210<br>–––<br>VGS= 0V<br>~~a~~|
|Coss|Output Capacitance<br>–––<br>1020<br>–––<br>VDS= 50V<br>~~a~~|
|Crss|Reverse Transfer Capacitance<br>–––<br>500<br>–––<br>ƒ= 1.0MHz<br>pF<br>~~a~~|
|Cosseff.(ER)|Effective Output Capacitance(EnergyRelated)<br>–––<br>1430<br>–––<br>VGS= 0V, VDS= 0V to 48V<br>~~a”)~~|
|Cosseff.(TR)|Effective Output Capacitance(Time Related)<br>–––<br>1880<br>–––<br>VGS= 0V, VDS= 0V to 48V<br>~~a~~|
|**Diode Characteristics**||
|**Symbol**<br>IS<br>ISM|S<br>D<br>G<br>**Parameter**<br>**Min. Typ. Max. Units**<br>Continuous Source Current<br>–––<br>–––<br>(BodyDiode)<br>Pulsed Source Current<br>–––<br>–––<br>(BodyDiode)<br>showing  the<br>**Conditions**<br>MOSFET symbol<br>integral reverse<br>p-njunction diode.<br>A<br>270<br>1100<br>~~Pe~~<br>~~oT~~<br>||
|VSD|Diode Forward Voltage<br>–––<br>–––<br>1.3<br>V<br>TJ= 25°C, IS= 165A, VGS= 0V<br>~~GQ~~|
|trr<br>Qrr<br>IRRM<br>ton|Reverse Recovery Time<br>–––<br>62<br>–––<br>TJ= 25°C<br>VR= 51V,<br>–––<br>66<br>–––<br>TJ= 125°C<br>IF= 165A<br>Reverse Recovery Charge<br>–––<br>310<br>–––<br>TJ= 25°C<br>di/dt = 100A/µs<br>–––<br>360<br>–––<br>TJ= 125°C<br>Reverse RecoveryCurrent<br>–––<br>4.4<br>–––<br>A<br>TJ= 25°C<br>Forward Turn-On Time<br>Intrinsic turn-on time is negligible(turn-on is dominated byLS+LD)<br>ns<br>nC<br>~~a~~<br>~~ee~~<br>~~||~~<br>~~es~~<br>~~**|**~~<br>~~a~~<br>~~a~~<br>~~G~~|



> Notes: ~~)a~~ Calcuted continuous current based on maximum allowable junction ~~©~~ Coss eff. (TR) is a fixed capacitance that gives the same charging time as temperature Bond wire current limit is 195A. Note that current Coss while VDS is rising from 0 to 80% VDSS. limitation arising from heating of the device leds may occur with @ Coss eff. (ER) is a fixed capacitance that gives the same energy asoss eff. (ER) is a fixed capacitance that gives the same energy as eff. (ER) is a fixed capacitance that gives the same energy as some lead mounting arrangements. 

- @ Coss eff. (ER) is a fixed capacitance that gives the same energy asoss eff. (ER) is a fixed capacitance that gives the same energy as eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. 

® Repetitive rating;  pulse width limited by max. junction . When mounted on 1" square PCB (FR-4 or G-10 Material). For temperature. recommended   footprint and soldering techniquea refer to applocation Limited by TJmax, starting TJ = 25°C, L = 0.021mH note # AN-  994 echniques refer to application note #AN-994. ®@ RG = 25 Ω , IAS = 165A, VGS =10V. Part not recommended for use R θ is measured at T, approximately 90°C. above this value . 

ISD ≤ 165A, di/dt ≤ 430A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. 

Pulse width ≤ 400µs; duty cycle ≤ 2%. O 11 R θ 

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1000 1000<br>VGS VGS<br>TOP           15V TOP           15V<br>10V 10V<br>gr 4.5V A 4.5V<br>4.0V 4.0V<br>100 3.5V 3.5V<br>3.3V 3.3V<br>3.0V 3.0V<br>BOTTOM 2.7V BOTTOM 2.7V<br>10 e el 100 a n) ee<br>a ee ell Nha<br>1 2.7V<br>2.7V<br>a Seti Po e t<br>≤ 60µs PULSE WIDTH ≤ 60µs PULSE WIDTH<br>Tj = 25°C Tj = 175°C<br>0.1 PEN to rertl 10 /<br>0.1 1 10 100 1000 0.1 1 10 100 1000<br>VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)<br>Fig 1.   Typical Output Characteristics Fig 2.   Typical Output Characteristics<br>1000 2.5<br>ID = 165A<br>VGS = 10V<br>100 TJ = 175°C 2.0<br>e/ a SeeeeeeP<br>10 1.5<br>TJ = 25°C<br>1 tt 1.0 PEELE<br>n / ann Pl Ly<br>VDS = 25V<br>≤ 60µs PULSE WIDTH<br>0.1 in 0.5 TLE EELLLL | EI<br>1 2 3 4 5 6 -60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Junction Temperature (°C)<br>VGS, Gate-to-Source Voltage (V)<br>Fig 4.   Normalized On-Resistance vs. Temperature<br>Fig 3.   Typical Transfer Characteristics<br>100000 5.0<br>VCGS  iss   = C = 0V,       f = 1 MHZgs + Cgd,  C ds SHORTED ID= 165A VDS= 48V<br>C  = C VDS= 30V<br>=— Crss   = C gd + C 4.0 ty LL<br>oss   ds  gd<br>C<br>10000 iss<br>E i FTP 3.0<br>PSH<br>C<br>oss<br>San i naii 2.0 f t<br>1000 Crss<br>1.0<br>100 a 0 ll 0.0 Py) ty yf.<br>1 10 100 0 20 40 60 80 100 120<br>VDS, Drain-to-Source Voltage (V)  QG,  Total Gate Charge (nC)<br>ID, Drain-to-Source Current (A)<br>ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A)<br>RDS(on) , Drain-to-Source On Resistance                        (Normalized)<br>C, Capacitance (pF)<br>VGS, Gate-to-Source Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 4.** Normalized On-Resistance vs. Temperature 

**Fig 5.** Typical Capacitance vs. Drain-to-Source Voltage 

**Fig 6.** Typical Gate Charge vs. Gate-to-Source Voltage 

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10000<br>OPERATION IN THIS AREA<br>LIMITED BY R DS(on)(on)<br>1000<br>100µsec<br>1 msecsec<br>100<br>Limited by<br>package<br>10msec<br>10<br>Tc = 25°C DC<br>Tj = 175°C<br>Single Pulse<br>1 | PP<br>0 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 8.   Maximum Safe Operating Area<br>75<br>Id = 5mA<br>70<br>e n n n)!<br>A T<br>65<br>ae<br>60 A LLELE<br>T ELAT<br>55<br>-60 -40 -20 0 20 40 60 80 100120140160180120140160180140160180<br>TJ , Temperature ( °C )<br>Fig 10.   Drain-to-Source Breakdown Voltage<br>1200<br>ID<br>TOP         27A<br>1000<br>50A<br>BOTTOM 165A<br>M E<br>800<br>N OLL<br>600<br>I NET<br>400<br>N AN EEE<br>200<br>S URSONCUEEEE<br>0 ||| CESS<br>25 50 75 100 125 150 175<br>Starting TJ , Junction Temperature (°C)<br>ID,  Drain-to-Source Current (A)<br>EAS , Single Pulse Avalanche Energy (mJ)<br>V(BR)DSS, Drain-to-Source Breakdown Voltage (V)<br>**----- End of picture text -----**<br>


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1000 10000<br>OPERATION IN THIS AREA<br>LIMITED BY R DS(on)(on)<br>T = 175°C<br>J<br>100 1000<br>100µsec<br>1 msecsec<br>10 TJ = 25°C 100<br>Limited by<br>package<br>10msec<br>1 10<br>Tc = 25°C DC<br>Tj = 175°C<br>VGS = 0V Single Pulse<br>0.1 th 1 | PP<br>0.0 0.5 1.0 1.5 2.0 2.5 0 1 10<br>VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)<br>Fig 7.   Typical Source-Drain Diode Fig 8.   Maximum Safe Operating Area<br>Forward Voltage<br>300 75<br>Id = 5mA<br>250 Limited By Package<br>70<br>200 Se e e n n n)!<br>Es A T<br>150 65<br>TTT ATT ae<br>100<br>t tt At 60 A LLELE<br>50<br>e eeeeN} T ELAT<br>0 P| Et [LIN] 55<br>25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180120140160180140160180<br> TC , Case Temperature (°C) TJ , Temperature ( °C )<br>Fig 9.   Maximum Drain Current vs. Fig 10.   Drain-to-Source Breakdown Voltage<br>Case Temperature<br>3.0 1200<br>ID<br>TOP         27A<br>2.5 1000<br>50A<br>BOTTOM 165A<br>2.0 Ea 800 M E<br>T it A N OLL<br>1.5 600<br>{ itt Ts I NET<br>1.0 400<br>T EL AT N AN EEE<br>0.5 200<br>AT T S URSONCUEEEE<br>0.0 eT tL 0 ||| CESS<br>-10 0 10 20 30 40 50 60 70 25 50 75 100 125 150<br>Starting TJ , Junction Temperature (°C)<br>VDS, Drain-to-Source Voltage (V)<br>ID,  Drain-to-Source Current (A)<br>EAS , Single Pulse Avalanche Energy (mJ)<br>Energy (µJ)<br>ISD, Reverse Drain Current (A)<br>ID,  Drain Current (A)<br>V(BR)DSS, Drain-to-Source Breakdown Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 11.** Typical COSS Stored Energy 

**Fig 12.** Maximum Avalanche Energy vs. DrainCurrent 

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1<br>a a ee ee ee<br>D = 0.50<br>OE eee ee<br>0.1 0.20 e e<br>0.10 a ee real R1 R1 R2 R2 R3 R3 R4R4 Ri (°C/W)     τ i (sec) |<br>0.01 0.020.05 Se τ J τ n J τ 1 τ 1 en τ 2 τ 2 τ 3 τ 3 ae τ 4 τ 4 τ C τ — 0.01115     0.0000090.08360     0.0000800.18950     0.001295<br>S 0.01 S SSS eee Ci= Ci τ i / Rii / Ri | 0.11519     0.006726<br>FT a 2 ee ee eee<br>Ee ee ee ee eee ee eee Notes: 0 ee eeel<br>nae SINGLE PULSE | ee 1. Duty Factor D = t1/t2 Baan<br>( THERMAL RESPONSE ) 2. Peak Tj = P dm x Zthjc + Tc<br>0.001 WAGE HLL EEL ll<br>1E-006 1E-005 0.0001 0.001 0.01 0.1<br>t1 , Rectangular Pulse Duration (sec)<br>Fig 13.   Maximum Effective Transient Thermal Impedance, Junction-to-Case<br>1000<br>Duty Cycle = Single Pulse<br>PT a<br>aa<br>a Allowed avalanche Current vs avalanche<br>A pulsewidth, tav, assuming  ∆ Tj = 150°C and  THT<br>100 S 0.01 p | Tstart =25°C (Single Pulse) Hl<br>PE RRASSNEEESNEEEEEEE<br>0.05<br>S H AH HH<br>0.10 CSSA<br>10 a ee es<br>| Allowed avalanche Current vs avalanche  ee a<br>pulsewidth, tav, assuming  ∆Τ j = 25°C and  a<br>1 P Tstart = 150°C. eEE ooo<br>1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01<br>tav (sec)<br>Fig 14.   Typical Avalanche Current vs.Pulsewidth<br>300 Notes on Repetitive Avalanche Curves , Figures 14, 15:<br>KL Ld TOP          Single Pulse                 (For further info, see AN-1005 at www.irf.com)<br>250 INLI BOTTOM   1.0% Duty Cycle 1. Avalanche failures assumption:<br>ID = 165A Purely a thermal phenomenon and failure occurs at a temperature far in<br>NIN excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type.<br>200 a N [NERS] | 2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded.<br>B ANE 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.<br>4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse.<br>150 P ITINAEELELE 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase<br>during avalanche).<br>100 PP | | EPEIN AE [EEE] | 6. I7.  ∆ av T = = Allowable avalanche current.Allowable rise in junction temperature, not to exceed Tjmax jmax (assumed as<br>P TT INN NE EEE 25°C in Figure 14, 15).<br>tav = Average time in avalanche.<br>50 F i tT |>]| I | NSAN N E EEL-EE D = Duty cycle in avalanche =  tav ·f<br>ZthJC(D, tav) = Transient thermal resistance, see Figures 13)<br>Pt} LI<br>0 Ft tetEETttLINET N ASMEI<br>PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) = A T/ ZthJCthJC<br>25 50 75 100 125 150 175<br>Iav =av == 2 A T/ [1.3·BV·Zth]th]]<br>Starting TJ , Junction Temperature (°C) EAS (AR) = PD (ave)·tavAS (AR) = PD (ave)·tav = PD (ave)·tavD (ave)·tav·tavav<br>EAR , Avalanche Energy (mJ)<br>Avalanche Current (A)<br>Thermal Response ( Z thJC ) °C/W<br>**----- End of picture text -----**<br>


- Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type. 

2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded. 

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 

4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse. 

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 

7. ∆ Allowable rise in junction temperature, not to exceed Tjmax jmax (assumed as 25°C in Figure 14, 15). 

**PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) =** A **T/ ZthJCthJC Iav =av == 2** A **T/ [1.3·BV·Zth]th]] EAS (AR) = PD (ave)·tavAS (AR) = PD (ave)·tav = PD (ave)·tavD (ave)·tav·tavav** 

**Fig 15.** Maximum Avalanche Energy vs. Temperature 

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3.0 PEt TE EE ty<br>2.5 P ENGRSPA ETE<Ge000<br>2.0<br>P L SN PAT<br>ID = 250µA Sat| PS<br>1.5 ID = 1.0mA<br>AST<br>ID = 1.0A EEaNNEE<br>1.0 S ERENEBERANE<br>0.5 PT ELT TT [tN] |<br>-75 -50 -25 0 25 50 75 100 125 150 175 200<br>TJ , Temperature ( °C )<br>VGS(th), Gate threshold Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 16.** Threshold Voltage vs. Temperature 

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12<br>IF = 165A<br>VR = 51V | Le<br>10<br>TJ = 25°C<br>ps<br>TJ = 125°C<br>Bea<br>8 Z en<br>6 e “ T<br>4<br>P ET<br>2<br>0 100 200 300 400 500<br>diF /dt (A/µs)<br>IRRM (A)<br>**----- End of picture text -----**<br>


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14<br>IF = 110A<br>12 VR = 51V Pf<br>TJ = 25°C<br>10 TJ = 125°C |<br>Cy<br>8 T y<br>6<br>i vi<br>4<br>| |<br>2 T y Tt | [.<br>0 100 200 300 400 500<br>diF /dt (A/µs)<br>Fig. 17 - Typical Recovery Current vs. di;/dt<br>900<br>IF = 110A<br>800<br>VR = 51V —<br>700 TJ = 25°C<br>Te<br>TJ = 125°C<br>600 7<br>500<br>He<br>a<br>400<br>300 a ne?<br>ae<br>200<br>=<br>100 | [F] [T] | |<br>0 100 200 300 400 500<br>diF /dt (A/µs)<br>IRRM (A)<br>QRR (A)<br>**----- End of picture text -----**<br>


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600<br>IF = 165A<br>VR = 51V<br>500 TJ = 25°C<br>TJ = 125°C<br>ea ee<br>400<br>eZ an<br>300<br>n anan<br>200<br>0 100 200 300 400 500<br>diF /dt (A/µs)<br>QRR (A)<br>**----- End of picture text -----**<br>


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Driver Gate Drive<br>P.W.<br>D.U.T + {+ P.W. Period ——— — D = —— Period<br>) [©)]    •  CircuitLow  LayoutStray ConsiderationsInduct | t V t GS=10<br> •<br>- •   Low Leakage Inductance @ D.U.T. ISD Waveform<br>+<br>Reverse<br>Recovery Body Diode Forward<br>oi - [1] Current Transformer - ® + Current r Current di/dt AN<br>® D.U.T. VDS Waveform Diode Recoverydv/dt ‘<br>00 a VDD<br>ma<br>•   Re-Applied<br>•   Driver same type as D.U.T. + Voltage Body Diode  Forward Drop<br>Re ( 4 •   dv/dt controlled by Rg Vpp -<br>•<br>D.U.T. - Device Under Test SOO |<br>Ripple  ≤ 5% ISD<br>Isp controlled by Duty Factor "D" @| t<br>* Vg = 5V for Logic Level Devices<br>Fig 21.  Peak Diode Recovery dv/dt Test Circuit for N-Channel<br>HEXFET ® Power MOSFETs<br>V(BR)DSS(BR)DSS<br>15V —_ tp -><br>VDS L DRIVER<br>RG D.U.T +<br>- [V][DD]<br>IAS A<br>¢ 20VVGS dt<br>tp 0.01 Ω<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
V(BR)DSS(BR)DSS<br>—_ tp -><br>IAS<br>**----- End of picture text -----**<br>


## **Fig 22b.** Unclamped Inductive Waveforms 

**Fig 22a.** Unclamped Inductive Test Circuit 

**==> picture [130 x 58] intentionally omitted <==**

**----- Start of picture text -----**<br>
+<br>-<br>≤ 1<br>≤ 0.1 %<br>**----- End of picture text -----**<br>


## **Fig 23a.** Switching Time Test Circuit 

**==> picture [134 x 132] intentionally omitted <==**

**----- Start of picture text -----**<br>
Current Regulator<br>Same Type as D.U.T.<br>50K Ω<br>12V .2 µ F .3 µ F ||<br>+<br>D.U.T. -VDS<br>VGS<br>3mA<br>WAV IG ID<br>Current Sampling Resistors<br>**----- End of picture text -----**<br>


**Fig 24a.** Gate Charge Test Circuit 

**==> picture [192 x 121] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDS<br>90%<br>\<br>10% /\<br>VGS «le ys<br>td(on) tr td(off) tf<br>**----- End of picture text -----**<br>


**==> picture [164 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig 23b.   Switching Time Waveforms<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Id<br>Vds<br>fl Vgs<br>i<br>Vgs(th)<br>a plag [p] [l] [e] w i e » !<br>Qgs1 Qgs2 Qgd Qgodr<br>**----- End of picture text -----**<br>


**Fig 24b.** Gate Charge Waveform 

www.irf.com 

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## Dimensions are shown in millimeters (inches) 

www.irf.com 

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## TO-262 Package Outline 

Dimensions are shown in millimeters (inches) 

## TO-262 Part Marking Information 

www.irf.com 

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Dimensions are shown in millimeters (inches) 

**==> picture [21 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
TRR<br>**----- End of picture text -----**<br>


**==> picture [454 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.60 (.063)<br>1.50 (.059)<br>1.60 (.063)<br>4.10 (.161)<br>1.50 (.059)<br>3.90 (.153) 0.368 (.0145)<br>0.342 (.0135)<br>— oT<br>—* OOF SO |G -<br>FEED DIRECTION 1.85 (.073) 11.60 (.457)<br>1.65 (.065) 11.40 (.449) 24.30 (.957)<br>15.42 (.609)<br>23.90 (.941)<br>15.22 (.601)<br>TRL<br>| x<br>1.75 (.069)<br>10.90 (.429) 1.25 (.049)<br>4.72 (.136)<br>10.70 (.421)<br>16.10 (.634) 4.52 (.178)<br>15.90 (.626)<br>**----- End of picture text -----**<br>


**==> picture [83 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
FEED DIRECTION<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
13.50 (.532) 27.40 (1.079)<br>12.80 (.504) 23.90 (.941) 1<br>4<br>330.00<br>(14.173) Y\ g 60.00 (2.362)      MIN.<br>  MAX.<br>x<br>30.40 (1.197)<br>      MAX.<br>26.40 (1.039) I 4<br>24.40 (.961)<br>3<br>**----- End of picture text -----**<br>


NOTES : 

1.   COMFORMS TO EIA-418. 

2.   CONTROLLING DIMENSION: MILLIMETER. 

3.   DIMENSION MEASURED @ HUB. 

4.   INCLUDES FLANGE DISTORTION @ OUTER EDGE. 

Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. 

**IR WORLD HEADQUARTERS:** 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information **.** 12/2008 

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10 

## **IMPORTANT NOTICE** 

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) . 

With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. 

In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. 

The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. 

For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office ( **www.infineon.com** ). 

## **WARNINGS** 

Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. 

Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. 



## Links

- [View this product on Novapart](https://novapart.co/products/IRLS3036TRLPBF/power-mosfet-n-channel-60-v-270-a-2400-ohm-to-263)
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- [Supplier page](https://es.farnell.com/infineon/irls3036trlpbf/mosfet-n-ch-60v-270a-to-263-3/dp/2577183)
---

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