# Power MOSFET, N Channel, 60 V, 240 A, 1900 µohm, TO-263 (D2PAK), Surface Mount

![Product image](https://novapart.co/image/farnell:2726030/)

**URL**: https://novapart.co/products/IRLS3036TRL7PP/power-mosfet-n-channel-60-v-240-a-1900-ohm-to-263
**SKU**: IRLS3036TRL7PP
**Manufacturer**: INFINEON
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.5400
**Stock**: 500+
**Lead Time**: 64 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:240A; Drain Source Voltage Vds:60V; On Resistance Rds(on):0.0015ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:2.5V; P

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 7Pins |
| Channel Type | N Channel |
| Product Range | HEXFET |
| Qualification | - |
| Power Dissipation | 380W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-263 (D2PAK) |
| Drain Source Voltage Vds | 60V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 240A |
| Drain Source On State Resistance | 1900µohm |
| Gate Source Threshold Voltage Max | 2.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2726030/)

## IRLS3036-7PPbF 

HEXFET Power MOSFET 

## **Applications** 

DC Motor Drive 

High Efficiency Synchronous Rectification in SMPS Uninterruptible Power Supply High Speed Power Switching Hard Switched and High Frequency Circuits 

> D **VDSS 60V RDS(on)   typ. 1.5m** ~~a~~ **max. 1.9m** G **ID (Silicon Limited) 300A** ~~er ee~~ S **ID (Package Limited) 240A** 

## **Benefits** 

Optimized for Logic Level Drive Very Low RDS(ON) at 4.5V VGS Superior R*Q at 4.5V VGS Improved  Gate, Avalanche and Dynamic  dV/dt . RuggednessFully Characterized Capacitance and Avalanche SOA 

Enhanced body diode dV/dt and dI/dt Capability Lead-Free 

|**G**<br>**D**<br>**S**|
|---|
|Gate<br>Drain<br>Source|
|**Absolute Maximum Ratings**<br>**Symbol**<br>**Parameter**<br>**Units**<br>ID@ TC= 25°C<br>Continuous Drain Current, VGS@ 10V(Silicon Limited)<br>ID@ TC= 100°C<br>Continuous Drain Current, VGS@ 10V(Silicon Limited)<br>ID@ TC= 25°C<br>Continuous Drain Current, VGS@ 10V(Package Limited)<br>IDM<br>Pulsed Drain Current<br>PD@TC= 25°C<br>Maximum Power Dissipation<br>W<br>Linear DeratingFactor<br>W/°C<br>**Max.**<br>300<br>210<br>1000<br>240<br>A<br>380<br>2.5<br>~~OOOO~~<br>~~eeeeey,§}:~~<br>~~esA~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~>en~~<br>~~es~~<br>~~a~~|
|VGS<br>Gate-to-Source Voltage<br>V<br>dv/dt<br>Peak Diode Recovery<br>V/ns<br>TJ<br>Operating Junction and<br>TSTG<br>Storage Temperature Range<br>SolderingTemperature,for 10 seconds(1.6mm from case)<br>300<br>°C<br>8.1<br>± 16<br>-55  to + 175<br>~~a~~<br>~~es~~<br>~~©~~<br>~~Sen~~<br>~~ee~~<br>~~eee~~|
|**Avalanche Characteristics**|
|EAS(Thermallylimited)<br>Single Pulse Avalanche Energy<br>mJ<br>IAR<br>Avalanche Current<br>A<br>EAR<br>Repetitive Avalanche Energy<br>mJ<br>See Fig. 14, 15, 22a, 22b<br>300<br>~~es~~<br>~~a sees~~<br>~~es~~<br>~~rT~~|
|**Thermal Resistance**|
|**Symbol**<br>**Parameter**<br>**Typ.**<br>**Max.**<br>**Units**<br>~~a~~|
|RθJC<br>Junction-to-Case<br>–––<br>0.40<br>°C/W<br>RθJA<br>Junction-to-Ambient(PCB Mount,steadystate)<br>–––<br>40<br>~~$$~~<br>~~esI~~|



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10/28/10 

**Static @ TJ = 25°C (unless otherwise specified)** 

|**Symbol**<br>**Parameter**<br>**Min. Typ. Max. Units**<br>V(BR)DSS<br>Drain-to-Source Breakdown Voltage<br>60<br>–––<br>–––<br>V<br>ΔV(BR)DSS/ΔTJBreakdown Voltage Temp. Coefficient<br>–––<br>0.059<br>–––<br>V/°C<br>–––<br>1.5<br>1.9<br>–––<br>1.7<br>2.2<br>VGS(th)<br>Gate Threshold Voltage<br>1.0<br>–––<br>2.5<br>V<br>IDSS<br>Drain-to-Source Leakage Current<br>–––<br>–––<br>20<br>–––<br>–––<br>250<br>IGSS<br>Gate-to-Source Forward Leakage<br>–––<br>–––<br>100<br>Gate-to-Source Reverse Leakage<br>–––<br>–––<br>-100<br>RG(int)<br>Internal Gate Resistance<br>–––<br>1.9<br>–––<br>Ω<br>VGS= -16V<br>**Conditions**<br>VGS= 0V,ID= 250μA<br>Reference to 25°C,ID= 5mA<br>VGS= 10V,ID= 180A<br>VDS= VGS,ID= 250μA<br>VDS= 60V,VGS= 0V<br>VDS= 60V,VGS= 0V,TJ= 125°C<br>VGS= 16V<br>μA<br>nA<br>RDS(on)<br>Static Drain-to-Source On-Resistance<br>VGS= 4.5V,ID= 150A<br>mΩ<br>~~a a~~<br>~~GS GO~~<br>~~GO OO~~<br>~~esa~~<br>~~GO~~<br>~~GO~~<br>~~GO OO~~<br>~~a~~<br>~~GO~~<br>~~GO~~<br>~~GO OO”~~<br>~~a~~<br>~~aeeee~~<br>~~esa~~<br>~~GS GO~~<br>~~GO OO~~<br>~~a~~<br>~~aeeee~~<br>~~|esrs~~<br>~~esGD~~<br>~~GO~~<br>~~GO GO~~|
|---|
|**Dynamic @ TJ = 25°C(unless otherwise specified)**|
|**Symbol**<br>**Parameter**<br>**Min. Typ. Max. Units**<br>gfs<br>Forward Transconductance<br>390<br>–––<br>–––<br>S<br>Qg<br>Total Gate Charge<br>–––<br>110<br>160<br>Qgs<br>Gate-to-Source Charge<br>–––<br>33<br>–––<br>Qgd<br>Gate-to-Drain("Miller")Charge<br>–––<br>53<br>–––<br>Qsync<br>Total Gate Charge Sync.(Qg- Qgd)<br>–––<br>57<br>–––<br>td(on)<br>Turn-On DelayTime<br>–––<br>81<br>–––<br>tr<br>Rise Time<br>–––<br>540<br>–––<br>td(off)<br>Turn-Off DelayTime<br>–––<br>89<br>–––<br>tf<br>Fall Time<br>–––<br>170<br>–––<br>Ciss<br>Input Capacitance<br>–––<br>11270<br>–––<br>VDS= 30V<br>VGS= 4.5V<br>VGS= 0V<br>nC<br>ns<br>ID= 180A<br>RG= 2.1Ω<br>VGS= 4.5V<br>VDD= 39V<br>ID= 180A,VDS=0V,VGS= 4.5V<br>**Conditions**<br>VDS= 10V,ID= 180A<br>ID= 180A<br>~~a a~~<br>~~GO~~<br>~~GO~~<br>~~QO OO~~<br>~~a a~~<br>~~GO GS OO OO~~<br>~~aa~~<br>~~es~~~~**a**~~<br>~~a®~~<br>~~a~~<br>~~a~~<br>~~I ODGO GesOO~~<br>~~es~~<br>~~a ee~~<br>~~aeee~~<br>~~a~~<br>~~ee~~<br>~~®~~<br>~~a ee~~|
|Coss<br>Output Capacitance<br>–––<br>1025<br>–––<br>Crss<br>Reverse Transfer Capacitance<br>–––<br>520<br>–––<br>Cosseff.(ER)<br>Effective Output Capacitance(EnergyRelated)<br>–––<br>1460<br>–––<br>Cosseff.(TR)<br>Effective Output Capacitance(Time Related)<br>–––<br>1630<br>–––<br>VDS= 50V<br>ƒ= 1.0MHz<br>VGS= 0V,VDS= 0V to 48V<br>VGS= 0V,VDS= 0V to 48V<br>pF<br>~~a ee~~<br>~~aeee~~<br>~~a ee)~~<br>~~eeee~~|



## **Diode Characteristics** 

|**Symbol**<br>~~le~~|**Parameter**<br>|**Min. **<br>|**Typ. **|**Max. **|**Units**|**Units**<br>**Conditions**|
|---|---|---|---|---|---|---|
|IS<br>~~leoo~~|Continuous Source Current<br>(Body Diode)<br>~~oo~~|–––<br>~~oo~~|–––|300|A<br>~~|~~<br>~~GD~~<br>~~GO OO~~|S<br>D<br>G<br>showing  the<br>MOSFET symbol<br>integral reverse<br>p-n junction diode.<br>~~GD~~<br>~~OO~~|
|ISM<br>~~leoo~~<br>~~es~~<br>~~a~~|Pulsed Source Current<br>(Body Diode)<br>~~oo~~<br>~~GD~~|–––<br>~~oo~~<br>~~GD~~|–––<br>~~GD~~|1000<br>~~GD~~<br>~~GO~~|||
|VSD<br>~~oo~~<br>~~es~~<br>~~a~~|Diode Forward Voltage<br>~~oo~~<br>~~GD~~|–––<br>~~oo~~<br>~~GD~~|–––<br>~~GD~~|1.3<br>~~GD~~<br>~~GO~~|V<br>~~|~~<br>~~GD~~<br>~~GO OO~~|TJ= 25°C,IS= 180A,VGS= 0V<br>~~GD~~<br>~~OO~~|
|trr<br>~~es~~<br>~~a~~|Reverse Recovery Time<br>~~GD~~|–––<br>~~GD~~|57<br>~~GD~~|–––<br>~~GD~~<br>~~GO~~|ns<br>~~GD~~<br>~~GO OO~~|TJ= 25°C<br>VR= 51V,<br>TJ= 125°C<br>IF= 180A<br>TJ= 25°C<br>di/dt = 100A/μs<br>TJ= 125°C<br>TJ= 25°C<br>~~GD~~<br>~~OO~~|
|||–––<br>~~a~~|60<br>~~a~~|–––<br>~~GO~~<br>~~a~~|||
|Qrr<br>~~a~~<br>~~a~~<br>~~es~~|Reverse Recovery Charge|–––<br>~~a~~<br>~~a~~|140<br>~~a~~<br>~~a~~|–––<br>~~GO ~~<br>~~a~~<br>~~a~~|nC<br> ~~GO OO~~||
|||–––<br>~~a~~|160<br>~~a~~|–––<br>~~a~~|||
|IRRM<br>~~a~~<br>~~es~~|Reverse RecoveryCurrent|–––<br>~~a~~|4.6<br>~~a~~|–––<br>~~a~~|A||
|ton<br>~~es~~<br>~~a~~|Forward Turn-On Time|Intrinsic turn-on time is negligible(turn-on is dominated byLS+LD)|||||



Calculated continuous current based on maximum allowable junction temperature Bond wire current limit is 240A. Note that current limitation arising from heating of the device leds may occur with some lead mounting arrangements. 

Repetitive rating;  pulse width limited by max. junction temperature. 

Limited by TJmax, starting TJ = 25°C, L = 0.018mH 

RG = 25 Ω , IAS = 180A, VGS =10V. Part not recommended for use above this value . 

## Pulse width ≤ 400μs; duty cycle ≤ 2%. 

Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 

Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. 

When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended   footprint and soldering techniquea refer to applocation note # AN-  994 echniques refer to application note #AN-994. 

θ 

ISD ≤ 180A, di/dt ≤ 1070A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. 

θ JC 

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1000<br>VGS<br>TOP           15V<br>10V<br>4.5V<br>4.0V<br>100 3.5V<br>3.3V<br>3.0V<br>BOTTOM 2.7V<br>10<br>1<br>2.7V<br>alii alii all<br>≤  60μs PULSE WIDTH<br>Tj = 25°C<br>BullSallie |<br>0.1<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 1.   Typical Output Characteristics<br>1000<br>TJ = 175°C<br>100 i” a —<br>aan<br>TJ = 25°C<br>10 Sy |<br>poof<br>VDS = 25V<br>≤  60μs PULSE WIDTH<br>1 ff<br>2.0 3.0 4.0 5.0<br>VGS, Gate-to-Source Voltage (V)<br>ID, Drain-to-Source Current (A)<br>) (Α<br>ID, Drain-to-Source Current<br>**----- End of picture text -----**<br>


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Fig 3.   Typical Transfer Characteristics<br>20000<br>VGS   = 0V,       f = 100 kHz<br>Ciss   = Cgs + Cgd,  Cds SHORTED<br>Crss   = Cgd<br>15000 t C oss   = C ds  + C gd T<br>Ciss ]<br>10000 ~ TTT<br>HE<br>5000<br>Coss<br>SU Crss<br>a |||<br>0<br>1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>C, Capacitance (pF)<br>**----- End of picture text -----**<br>


**Fig 5.** Typical Capacitance vs. Drain-to-Source Voltage 

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1000<br>VGS<br>TOP           15V<br>10V<br>4.5V<br>4.0V<br>3.5V<br>3.3V<br>3.0V<br>BOTTOM 2.7V<br>100<br>2.7V<br>7 aa al<br>≤  60μs PULSE WIDTH<br>Tj = 175°C<br>Tl q<br>10<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 2.   Typical Output Characteristics<br>2.5<br>ID = 180A<br>VGS = 10V<br>2.0<br>LELLLLLD<br>1.5 ELLA<br>4<br>we<br>1.00.5 LATTALE<br>-60 -40 -20 0 20 40 60 80 100 120 140 160 180<br>TJ , Junction Temperature (°C)<br>Fig 4.   Normalized On-Resistance vs. Temperature<br>5<br>ID= 180A VDS= 48V<br>VDS= 30V<br>4<br>Po s<br>3<br>TTT<br>2 ITT TT<br>1<br>f|<br>0 AAPLTTT ET<br>0 20 40 60 80 100 120 140<br> QG  Total Gate Charge (nC)<br>VGS, Gate-to-Source Voltage (V)<br>ID, Drain-to-Source Current (A)<br>RDS(on) , Drain-to-Source On Resistance                        (Normalized)<br>**----- End of picture text -----**<br>


**Fig 4.** Normalized On-Resistance vs. Temperature 

**Fig 6.** Typical Gate Charge vs. Gate-to-Source Voltage 

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1000 10000<br>OPERATION IN THIS AREA<br>TT. | | p=) Sr<br>LIMITED BY R DS(on)<br>TJ = 175°C 1000<br>100 Bap aee aril<br>100 μsec<br>f f meer eni<br>— ee ey<br>100<br>TJ = 25°C<br>10 1m sec<br>LIMITED BY PACKAGE<br>10<br>a a ee SS SSS 58S a eaee 1 0m se en c ed<br>1<br>1<br>Tc = 25°C<br>Tj = 175°C DC<br>VGS = 0V Single Pulse<br>E p rr<br>0.1 0.1<br>0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.1 1 10 100<br>VSD, Source-to-Drain Voltage (V) VDS, Drain-toSource Voltage (V)<br>Fig 7.   Typical Source-Drain Diode Fig 8.   Maximum Safe Operating Area<br>Forward Voltage<br>300 80<br>LIMITED BY PACKAGE ID = 5mA<br>250 he |<br>TI N<br>200 70<br>150<br>PL [TIN]<br>100 are<br>Eaaeew 60<br>50<br>0<br>pL} TIN 50<br>25 50 75 100 125 150 175<br>-60 -40 -20 0 20 40 60 80 100 120 140 160 180<br> TC , Case Temperature (°C)<br>TJ , Junction Temperature (°C)<br>Fig 9.   Maximum Drain Current vs. Fig 10.   Drain-to-Source Breakdown Voltage<br>Case Temperature<br>4.0 1200<br>                 I D<br>TOP          22A<br>1000<br>                37A<br>3.0 BOTTOM   180A<br>Ton =f<br>800<br>2.0 Z 600 EN<br>TAR S sRE<br>400<br>1.0 Tea NEE<br>200<br>iT} GSSS&<br>0.0 0<br>a || | SS<br>0 10 20 30 40 50 60 70 25 50 75 100 125 150 175<br>VDS, Drain-to-Source Voltage (V) Starting TJ, Junction Temperature (°C)<br>ISD, Reverse Drain Current (A)<br>Energy (μJ)<br>EAS, Single Pulse Avalanche Energy (mJ)<br>ID , Drain Current (A)<br>ID,  Drain-to-Source Current (A)<br>V(BR)DSS , Drain-to-Source Breakdown Voltage<br>**----- End of picture text -----**<br>


**Fig 10.** Drain-to-Source Breakdown Voltage 

**Fig 11.** Typical COSS Stored Energy 

**Fig 12.** Maximum Avalanche Energy Vs. DrainCurrent 

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TOR Rectifier<br>1<br>ee<br>D = 0.50 CRE EAeety ae ee ee el<br>0.1<br>0.20 comes<br>ELT<br>0.10<br>0.05 S eT oo TE R1 R1 OE R2 R EE 2 R3R3 PT Ri (°C/W) τι  (sec)<br>0.01 ( 0.02 0.01 teeear τ J τ J τ 1 τ 1 ] τ 2 τ 2 ] τ 3 τ 3 τ C τ a 0.103731 0.196542 0.000184 0.001587<br>esi) Ci= Ci=  τ i /τ Rii / Ri 0.098271 0.006721<br>P| e e |<br>0.001 SINGLE PULSE<br>( THERMAL RESPONSE )<br>Zag eerAEE || EEE EEI||| SERA Notes: ————— |<br>a a ee ee ee ee ee 1. Duty Factor D = t1/t2<br>2. Peak Tj = P dm x Zthjc + Tc<br>0.0001 ee<br>1E-006 1E-005 0.0001 0.001 0.01 0.1<br>t1 , Rectangular Pulse Duration (sec)<br>Fig 13.   Maximum Effective Transient Thermal Impedance, Junction-to-Case<br>1000 po<br>eras Duty Cycle = Single Pulse  Oo | Allowed avalanche Current vs avalanche  |<br>Ee es ee ee ee se ee ee ee es pulsewidth, tav, assuming  Δ Tj = 150°C and  Ty<br>Tstart =25°C (Single Pulse)<br>Se |<br>100 EI SAU Loo<br>0.01<br>PTA SNOUT TTT TP<br>PEE HE SSE PSA<br>0.05<br>0.10<br>10 PET» PRATT SE[THE<br>FL  LT A/T SSS TW<br>Allowed avalanche Current vs avalanche<br>pulsewidth, tav, assuming  ΔΤ j = 25°C and<br>Tstart = 150°C.<br>1 CIE Pn SH<br>1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01<br>tav (sec)<br>Fig 14.   Typical Avalanche Current vs.Pulsewidth<br>300 Notes on Repetitive Avalanche Curves , Figures 14, 15:<br>TOP          Single Pulse                 (For further info, see AN-1005 at www.irf.com)<br>250 NE BOTTOM   1% Duty Cycle I D  = 180A 1. Avalanche failures assumption:Purely a thermal phenomenon and failure occurs at a temperature far in<br>CN excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type.<br>200 2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded.<br>3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.<br>NA 4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse.<br>150 INNELELEL 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase<br>during avalanche).<br>6. Iav = Allowable avalanche current.<br>TINANON ELLE<br>100 7.  Δ T = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as<br>25°C in Figure 14, 15).<br>LL NNE LL tav = Average time in avalanche.<br>50<br>D = Duty cycle in avalanche =  tav ·f<br>ZthJC(D, tav) = Transient thermal resistance, see Figures 13)<br>ELLE ASSN LANSKY<br>0<br>25 50 75 100 125 150 175 PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) = A T/ ZthJCthJC<br>Starting TJ , Junction Temperature (°C) Iav =av == 2 A T/ [1.3·BV·Zth]th]]<br>EAR , Avalanche Energy (mJ)<br>Thermal Response ( Z thJC )<br>Avalanche Current (A)<br>**----- End of picture text -----**<br>


- Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type. 

2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded. 

3. Equation below based on circuit and waveforms shown in Figures 22a, 22b. 

4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse. 

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 

7. Δ T = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as 25°C in Figure 14, 15). 

**PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) =** A **T/ ZthJCthJC Iav =av == 2** A **T/ [1.3·BV·Zth]th]] EAS (AR) = PD (ave)·tav** 

**Fig 15.** Maximum Avalanche Energy vs. Temperature 

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3.0<br>ID = 1.0A<br>ID = 1.0mA<br>2.5 ID = 250μA<br>2.0 ARRNS = mS Z<br>1.5<br>RNS<br>1.0<br>-75 -50 -25 0 25 50 75 100 125 150 175<br>TJ , Temperature ( °C )<br>VGS(th) Gate threshold Voltage (V)<br>**----- End of picture text -----**<br>


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24<br>1812 Rane¢ LH | 2a Wa<br>IF = 120A<br>6<br>VR = 51V<br>TJ = 125°C<br>TJ =  25°C<br>0<br>100 200 300 400 500 600 700 800 900<br>dif / dt - (A / μs)<br>IRRM - (A)<br>**----- End of picture text -----**<br>


**Fig 16.** Threshold Voltage Vs. Temperature 

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24 TTT TLb<br>18<br>12 snanecan<br>a<br>oY<br>6 A | IF = 180A<br>VR = 51V<br>TJ = 125°C<br>TJ =  25°C<br>=<br>0<br>100 200 300 400 500 600 700 800 900<br>dif / dt - (A / μs)<br>IRRM - (A)<br>**----- End of picture text -----**<br>


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1000<br>800<br>TTT<br>600<br>LLL LEY<br>BERRE<br>400<br>AE<br>ZO IF = 120A<br>200 V R  = 51V<br>TJ = 125°C<br>TJ =  25°C<br>0 PTTLee=<br>100 200 300 400 500 600 700 800 900<br>dif / dt - (A / μs)<br>QRR - (nC)<br>**----- End of picture text -----**<br>


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1000<br>IF = 180A<br>VR = 51V<br>800 TJ = 125 ° C<br>TJ =  25°C<br>600 ao Ley<br>400<br>RRREEZAE<br>ert<br>200<br>PTET Ed |  |<br>0<br>100 200 300 400 500 600 700 800 900<br>dif / dt - (A / μs)<br>QRR - (nC)<br>**----- End of picture text -----**<br>


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Driver Gate Drive<br>P.W.<br>Period D =<br>+ P.W. Period<br>D.U.T {$$ | ————| —— |t<br>VGS=10V<br>) ©)    •  Circuit Layout Considerations |<br> •<br>| —| - LowGround StrayPla I n eductance<br>+  •   CurrentLow LeakageTransformerInductance ® D.U.T. ISD Waveform<br>Reverse<br>@ - a | S - ® + RecoveryCurrent r Body Diode ForwardCurrent di/dt /\ —I<br>00 ® D.U.T. VDS Waveform Diode Recovery =<br>dv/dt ‘ VDD<br>ma<br>•   Re-Applied<br>•   Driver same type as D.U.T. + Voltage Body Diode  Forward Drop<br>Re ( aA •   dv/dt controlled by Rg Vpp -<br>•<br>D.U.T. - Device Under Test es ae<br>Isp controlled by Duty Factor "D" iO) t Ripple  ≤ 5% ISD<br>* Veg = 5V for Logic Level Devices<br>Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel<br>HEXFET ® Power MOSFETs<br>V(BR)DSS<br>15V < tp ><br>VDS L DRIVER<br>RG D.U.T +<br>- [V][DD]<br>IAS A<br>20VVGS<br>tp 0.01 Ω IAS<br>**----- End of picture text -----**<br>


**Fig 22a.** Unclamped Inductive Test Circuit 

## **Fig 22b.** Unclamped Inductive Waveforms 

**==> picture [130 x 58] intentionally omitted <==**

**----- Start of picture text -----**<br>
+<br>-<br>≤ 1  us<br>≤ 0.1 %<br>**----- End of picture text -----**<br>


## **Fig 23a.** Switching Time Test Circuit 

**==> picture [134 x 132] intentionally omitted <==**

**----- Start of picture text -----**<br>
Current Regulator<br>Same Type as D.U.T.<br>50K Ω<br>12V .2 μ F<br>.3 μ F<br>+<br>D.U.T. -VDS<br>VGS<br>3mA<br>NWA IG ID<br>Current Sampling Resistors<br>**----- End of picture text -----**<br>


**Fig 24a.** Gate Charge Test Circuit 

**==> picture [192 x 121] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDS<br>90%<br>\<br>10%<br>VGS |«le ys| |<br>td(on) tr td(off) tf<br>**----- End of picture text -----**<br>


**==> picture [164 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig 23b.   Switching Time Waveforms<br>**----- End of picture text -----**<br>


**==> picture [162 x 131] intentionally omitted <==**

**----- Start of picture text -----**<br>
Id<br>Vds<br>Vgs<br>Vgs(th)<br>t g p i e p!<br>Qgs1 Qgs2 Qgd Qgodr<br>**----- End of picture text -----**<br>


**Fig 24b.** Gate Charge Waveform 

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7 

D[2] Pak - 7 Pin Package Outline Dimensions are shown in millimeters (inches) 

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## D[2] Pak - 7 Pin Part Marking Information 

## D[2] Pak - 7 Pin Tape and Reel 

Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. 

**IR WORLD HEADQUARTERS:** 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information **.** 10/10 

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## Links

- [View this product on Novapart](https://novapart.co/products/IRLS3036TRL7PP/power-mosfet-n-channel-60-v-240-a-1900-ohm-to-263)
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- [Supplier page](https://es.farnell.com/infineon/irls3036trl7pp/mosfet-n-ch-60v-240a-to-263/dp/2726030)
---

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