# Power MOSFET, P Channel, 55 V, 20 A, 0.105 ohm, TO-252AA, Surface Mount

![Product image](https://novapart.co/image/farnell:2726028/)

**URL**: https://novapart.co/products/IRLR9343TRPBF/power-mosfet-p-channel-55-v-20-a-0105-ohm-to-252aa
**SKU**: IRLR9343TRPBF
**Manufacturer**: INFINEON
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.3110
**Stock**: 1000+
**Lead Time**: 113 days (indicative)

## Description

Transistor Polarity:P Channel; Continuous Drain Current Id:-20A; Drain Source Voltage Vds:-55V; On Resistance Rds(on):0.093ohm; Rds(on) Test Voltage Vgs:-10V; Threshold Voltage Vgs:-1V

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | P Channel |
| Product Range | HEXFET |
| Qualification | - |
| Power Dissipation | 79W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252AA |
| Drain Source Voltage Vds | 55V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 20A |
| Drain Source On State Resistance | 0.105ohm |
| Gate Source Threshold Voltage Max | 1V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2726028/)

## **Features** 

## PD - 95386A IRLR9343PbF IRLU9343PbF IRLU9343-701PbF 

Advanced Process Technology 

Key Parameters Optimized for Class-D Audio Amplifier Applications 

Low RDSON for Improved Efficiency 

> Efficiency ° Low Qg and Qsw for Better THD and Improved 

- Low Qrr for Better THD and Lower EMI 

- ° 175°C Operating Junction Temperature for Ruggedness 

- Repetitive Avalanche Capability for Robustness and 

- Reliability 

Multiple Package Options 

- Lead-Free 

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Key Parameters<br>VDS -55 V<br>RDS(ON) typ. @ VGS = -10V 93 m<br>ee ee<br>RDS(ON) typ. @ VGS = -4.5V ee 150 m<br>Qg typ. ee 31 nC<br>TJ max ee 175 ee °C<br>D<br>' ys ~<br>D-Pak I-Pak<br>G<br>IRLR9343 IRLU9343<br>I-Pak Leadform 701<br>S IRLU9343-701<br>Refer to page 10 for package outline<br>**----- End of picture text -----**<br>


## **Description** 

This Digital Audio HEXFET[®] is specifically designed for Class-D audio amplifier applications. This MosFET utilizes the latest processing techniques to achieve low on-resistance per silicon area. Furthermore, Gate charge, body-diode reverse recovery and internal Gate resistance are optimized to improve key Class-D audio amplifier performance factors such as efficiency, THD and EMI. Additional features of this MosFET are 175°C operating junction temperature and repetitive avalanche capability. These features combine to make this MosFET a highly efficient, robust and reliable device for Class-D audio amplifier applications. 

## **Absolute Maximum Ratings** 

|~~—————S~~|**Parameter**<br>~~—————S~~|**Max.**<br>~~—————S~~|**Units**|
|---|---|---|---|
|VDS<br>~~—————S~~|Drain-to-Source Voltage<br>~~—————S~~|-55<br>~~—————S~~|V<br>~~———~~|
|VGS<br>~~—————S~~<br>~~———~~|Gate-to-Source Voltage<br>~~—————S~~<br>~~es~~<br>~~———~~|±20<br>~~—————S~~<br>~~es~~<br>~~———~~||
|ID@ TC= 25°C<br>~~—————S~~<br>~~———~~|Continuous Drain Current, VGS@ -10V<br>~~—————S~~<br>~~es~~<br>~~a~~<br>~~———~~|-20<br>~~—————S~~<br>~~es~~<br>~~a~~<br>~~———~~|A<br>~~———~~|
|ID@ TC= 100°C<br>~~———~~|Continuous Drain Current, VGS@ 10V<br>~~es~~<br>~~———~~|-14<br>~~es~~<br>~~———~~||
|IDM<br>~~———~~|Pulsed Drain Current<br>~~———~~|-60<br>~~———~~||
|PD@TC= 25°C<br>~~———~~|Power Dissipation<br>~~———~~<br>~~es~~|79<br>~~———~~<br>~~es~~|W<br>~~———~~|
|PD@TC= 100°C|Power Dissipation<br>~~a~~|39||
||Linear DeratingFactor<br>~~es~~|0.53<br>~~es~~|W/°C<br>~~es~~|
|TJ<br>TSTG<br>~~**e**~~|Operating Junction and<br>Storage Temperature Range<br>~~**e**k~~|-40  to + 175|°C|
|~~**e**~~|ClampingPressure<br>~~**e**k~~<br>~~e~~|–––<br>~~e~~|N<br>~~e~~|



> Notes ® hrough (©) are on page 10 

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## **Electrical Characteristics @ TJ = 25°C (unless otherwise specified)** 

||**Parameter**|**Min.**|**Typ.**|**Max. **|**Units**|**Conditions**|
|---|---|---|---|---|---|---|
|BVDSS|Drain-to-Source Breakdown Voltage<br>~~a~~|-55<br>~~OB~~|–––<br>~~OB~~|–––|V|VGS= 0V, ID= -250µA<br>~~ee~~|
|∆ΒVDSS/∆TJ|Breakdown Voltage Temp. Coefficient<br>~~a~~|–––<br>~~OB~~|-52<br>~~OB~~|–––|mV/°C|Reference to 25°C, ID= -1mA<br>~~ee~~|
|RDS(on)|Static Drain-to-Source On-Resistance<br>~~a~~<br>~~pe~~|–––<br>~~OB~~<br>~~pe~~|93<br>~~OB~~<br>~~pe~~|105<br>~~pe~~|mΩ<br>~~pe~~|VGS= -10V, ID= -3.4A<br>~~ee~~<br>~~pe~~|
|||–––<br>~~pe~~|150<br>~~pe~~|170<br>~~pe~~||VGS= -4.5V, ID= -2.7A<br>~~pe~~|
|VGS(th)|Gate Threshold Voltage<br>~~A~~|-1.0<br>~~A~~|–––<br>~~A~~|–––<br>~~A~~|V<br>|VDS= VGS, ID= -250µA<br>~~|~~<br>~~eee~~|
|∆VGS(th)/∆TJ|Gate Threshold Voltage Coefficient<br>|–––<br>~~|~~<br>~~ee~~|-3.7<br>~~|~~<br>~~ee ee~~|–––<br>~~|~~<br>~~ee~~|mV/°C<br>~~|~~<br>~~ee~~||
|IDSS|Drain-to-Source Leakage Current<br><br>~~ee~~|–––<br>~~|~~<br>~~ee~~<br>~~ee~~|–––<br>~~|~~<br>~~|~~<br>~~ee~~<br>~~ee ee~~|-2.0<br>~~|~~<br>~~|~~<br>~~ee~~<br>~~ee~~|µA<br>~~|~~<br>~~ee~~<br>~~ee~~|VDS= -55V, VGS= 0V<br>~~|~~<br>~~ee~~<br>~~eee~~|
|||–––<br>~~|~~<br>~~ee~~<br>~~ee~~|–––<br>~~|~~<br>~~ee~~<br>~~ee ee~~|-25<br>~~|~~<br>~~ee~~<br>~~ee~~||VDS= -55V, VGS= 0V, TJ= 125°C<br>~~|~~<br>~~ee~~<br>~~eee~~|
|IGSS<br>~~po~~|Gate-to-Source Forward Leakage<br>~~ee~~<br>~~rr~~|–––<br>~~ee~~<br>~~ee~~<br>~~rr~~|–––<br>~~ee~~<br>~~ee ee~~<br>~~rr~~|-100<br>~~ee~~<br>~~ee~~<br>~~rr~~|nA<br>~~ee~~<br>~~ee ~~<br>~~rr~~|VGS= -20V<br>~~ee~~<br> ~~eee~~<br>~~rr~~|
||Gate-to-Source Reverse Leakage<br>~~rr~~<br>~~po~~|–––<br>~~rr~~<br>~~a~~|–––<br>~~rr~~<br>~~a~~|100<br>~~rr~~<br>~~a~~||VGS= 20V<br>~~rr~~|
|gfs<br>~~po~~|Forward Transconductance<br>~~rr~~<br>~~po~~|5.3<br>~~rr~~<br>~~a~~|–––<br>~~rr~~<br>~~a~~|–––<br>~~rr~~<br>~~a~~|S<br>~~rr~~|VDS= -25V, ID= -14A<br>~~rr~~|
|Qg<br>~~po~~|Total Gate Charge<br>~~po~~<br>~~a~~|–––<br>~~a~~<br>~~a~~|31<br>~~a~~<br>~~a~~|47<br>~~a~~<br>~~a~~||VGS= -10V<br>ID= -14A<br>See Fig. 6 and 19<br>VDS= -44V|
|Qgs|Gate-to-Source Charge<br>~~a~~|–––<br>~~a~~|7.1<br>~~a~~|–––<br>~~a~~|||
|Qgd|Gate-to-Drain Charge|–––|8.5|–––|||
|Qgodr|Gate Charge Overdrive<br>~~pO~~|–––<br>~~pO~~|15<br>~~pO~~|–––<br>~~pO~~|||
|td(on)|Turn-On DelayTime<br>~~pO~~<br>~~a~~|–––<br>~~pO~~<br>~~a~~|9.5<br>~~pO~~<br>~~a~~|–––<br>~~pO~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|ID= -14A<br>RG= 2.5Ω<br>VDD= -28V, VGS= -10V<br>~~a@~~<br>~~a~~|
|tr|Rise Time<br>~~a~~|–––<br>~~a~~|24<br>~~a~~|–––<br>~~a~~|||
|td(off)|Turn-Off DelayTime|–––|21|–––|||
|tf|Fall Time<br>~~pO~~|–––<br>~~pO~~|9.5<br>~~pO~~|–––<br>~~pO~~|||
|Ciss|Input Capacitance<br>~~pO~~<br>~~a~~|–––<br>~~pO~~<br>~~a~~|660<br>~~pO~~<br>~~a~~|–––<br>~~pO~~<br>~~a~~|pF|ƒ= 1.0MHz,          See Fig.5<br>VGS= 0V<br>VDS= -50V|
|Coss|Output Capacitance<br>~~a~~|–––<br>~~a~~|160<br>~~a~~|–––<br>~~a~~|||
|Crss|Reverse Transfer Capacitance|–––|72|–––|||
|Coss|Effective Output Capacitance<br>~~a~~|–––<br>~~a~~|280<br>~~a~~|–––<br>~~a~~||VGS= 0V, VDS= 0V to -44V|
|LD|Internal Drain Inductance<br>~~+4]~~<br>~~ee~~|–––<br>~~+4]~~<br>~~ee~~|4.5<br>~~+4]~~<br>~~ee~~|–––<br>~~+4]~~<br>~~ee~~|nH<br>~~+4]~~|Between  lead,<br>6mm (0.25in.)<br>from package<br>and center of die contact|
|LS|Internal Source Inductance<br>~~+4]~~<br>~~ee~~|–––<br>~~+4]~~<br>~~ee~~|7.5<br>~~+4]~~<br>~~ee~~|–––<br>~~+4]~~<br>~~ee~~|||



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100<br>VGS<br>TOP           -15V<br>-12V<br>-10V<br>-8.0V<br>nai Zan -5.5V<br>10 -4.5V<br>-3.0V<br>BOTTOM -2.5V<br>Jr |<br>1<br>Z ao |<br>-2.5V<br>≤ 60µs PULSE WIDTH<br>Tj = 25°C<br>0.1 Stillimart aa |<br>0.1 1 10 100<br>-VDS, Drain-to-Source Voltage (V)<br>-ID, Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 1.** Typical Output Characteristics 

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100.0<br>TJ = 25°C<br>a> TJ  am = 175°C<br>10.0 i aoe<br>_<br>1.0 ee<br>ff V = -25V<br>DS<br>≤ 60µs PULSE WIDTH<br>0.1<br>oli<br>0.0 5.0 10.0 15.0<br>-VGS, Gate-to-Source Voltage (V)<br>Fig 3.   Typical Transfer Characteristics<br>10000<br>VGS   = 0V,       f = 1 MHZ<br>Ciss   = C gs + Cgd,  C ds SHORTED<br>C  = C<br>rss   gd<br>= Coss  = Cds + Cgd<br>1000<br>Ciss<br>pf<br>Coss<br>PI E Crss EH TI<br>100 S E ee ll<br>ee ee<br>a ee ee<br>se<br>10<br>1 10 100<br>-VDS, Drain-to-Source Voltage (V)<br>C, Capacitance (pF)<br>)(Α<br>-ID, Drain-to-Source Current<br>**----- End of picture text -----**<br>


**Fig 5.** Typical Capacitance vs.Drain-to-Source Voltage 

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100<br>VGS<br>TOP           -15V<br>-12V<br>-10V<br>-8.0V<br>+H ag -5.5V<br>10 -4.5V<br>-3.0V<br>BOTTOM -2.5V<br>| Mme<br>1<br>F Za -2.5V<br>≤ 60µs PULSE WIDTH<br>Tj = 175°C<br>0.1 nteeililin een |<br>0.1 1 10 100<br>-VDS, Drain-to-Source Voltage (V)<br>Fig 2.   Typical Output Characteristics<br>2.0<br>ID = -14A<br>VGS = -10V ETL LLL<br>1.5 EEL ELLA.Wa<br>1.0 LAE<br>LLL<br>0.5 TEEELE EEL EL<br>-60 -40 -20 0 20 40 60 80 100 120 140 160 180<br>TJ , Junction Temperature (°C)<br>RDS(on) , Drain-to-Source On Resistance                        (Normalized)<br>-ID, Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 4.** Normalized On-Resistance vs. Temperature 

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20<br>I = -14A<br>D<br>VDS= -44V<br>16 VDS= -28V KE<br>VDS= -11V<br>12<br>Ay<br>8<br>ptTOYA|<br>4 Lf | FOR TEST CIRCUIT<br>SEE FIGURE 19<br>0 Aan<br>0 10 20 30 40 50<br> QG  Total Gate Charge (nC)<br>-VGS, Gate-to-Source Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 6.** Typical Gate Charge vs.Gate-to-Source Voltage 

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100.0<br>T = 175°C<br>J<br>A<br>10.0<br>|i Az |<br>a ee ee<br>TJ = 25°C<br>1.0 72 e ee<br>ee V = 0V<br>GS<br>0.1 Te<br>0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0<br>-VSD, Source-to-Drain Voltage (V)<br>-ISD, Reverse Drain Current (A)<br>**----- End of picture text -----**<br>


**Fig 7.** Typical Source-Drain Diode Forward Voltage 

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20<br>N EEL<br>16 T N<br>12<br>L ENE<br>8<br>P EEL<br>4 E N<br>E LLE ELLA<br>0<br>25 50 75 100 125 150 175<br>TJ , Junction Temperature (°C)<br>-ID  , Drain Current (A)<br>**----- End of picture text -----**<br>


**Fig 9.** Maximum Drain Current vs. Case Temperature 

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1000<br>OPERATION IN THIS AREA<br>LIMITED BY R DS(on)<br>700<br>100<br>nN<br>et PSC<br>100µsec<br>10<br>A Sy<br>Tc = 25°C<br>1msec<br>Tj = 175°C SW]<br>Single Pulse 10msec<br>1 ee asi<br>1 10 100 1000<br>-VDS  , Drain-toSource Voltage (V)<br>Fig 8.   Maximum Safe Operating Area<br>2.5<br>TITITIII<br>1.<br>2.0<br>H t<br>ID = -250µA<br>PR ET<br>1.5<br>P ANGS<br>BLEELLELLRENG<br>1.0<br>-75 -50 -25 0 25 50 75 100 125 150 175<br>TJ , Temperature ( °C )<br>-ID,  Drain-to-Source Current (A)<br>-VGS(th) Gate threshold Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 10.** Threshold Voltage vs. Temperature 

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10<br>FARE EEE<br>1 D = 0.50<br>CE eet<br>0.20<br>0.10 R1 R1 R2 R2 Ri (°C/W)    τi (sec)<br>0.1 0.05 τJ τJ τCτ 1.162        0.000512<br>0.020.01 τ1 τ1 τ2τ2 0.7370      0.002157<br>ee ee |<br>Ci= τi/Ri<br>0.01 Ci i/Ri<br>SINGLE PULSE Notes:<br>( THERMAL RESPONSE ) 1. Duty Factor D = t1/t2<br>ee 2. Peak Tj = P dm x Zthjc + Tc<br>0.001<br>1E-006 1E-005 0.0001 0.001 0.01 0.1<br>t1 , Rectangular Pulse Duration (sec)<br>Thermal Response ( Z thJC )<br>**----- End of picture text -----**<br>


**Fig 11.** Maximum Effective Transient Thermal Impedance, Junction-to-Case 

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600<br>I = -14A<br>D<br>500<br>400<br>300<br>200 T = 125°C<br>J<br>100<br>T = 25°C<br>J<br>0<br>4.0 6.0 8.0 10.0<br>-VGS, Gate-to-Source Voltage (V)<br>)Ω<br>RDS(on),  Drain-to -Source On Resistance (m<br>**----- End of picture text -----**<br>


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500<br>                 I<br>D<br>h | |<br>TOP          -4.0A<br>400 \ | |                -5.5A<br>BOTTOM   -14A<br>\|}<br>FAL<br>300<br>P Y |<br>200 K N A tf| ft| ff| |<br>P NA<br>100 N N eee<br>P SSST<br>e e<br>0 ee ee<br>25 50 75 100 125 150 175<br>Starting TJ, Junction Temperature (°C)<br>EAS, Single Pulse Avalanche Energy (mJ)<br>**----- End of picture text -----**<br>


## **Fig 12.** On-Resistance Vs. Gate Voltage 

**Fig 13.** Maximum Avalanche Energy Vs. Drain Current 

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1000<br>Allowed avalanche Current vs<br>Duty Cycle = Single Pulse avalanche  pulsewidth,  tav<br>100 assuming  ∆ Tj = 25°C due to<br>avalanche losses. Note: In no<br>case should Tj be allowed to<br>0.01 exceed Tjmax<br>10<br>0.05<br>0.10<br>1<br>0.1 en ee ee eee eel<br>1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02<br>tav (sec)<br>Fig 14.   Typical Avalanche Current Vs.Pulsewidth<br>Notes on Repetitive Avalanche Curves , Figures 14, 15:<br>140 (For further info, see AN-1005 at www.irf.com)<br>TOP          Single Pulse<br>1. Avalanche failures assumption:<br>120 BOTTOM   1% Duty Cycle   Purely a thermal phenomenon and failure occurs at a<br>ID = -14A     temperature far in excess of Tjmax. This is validated for<br>100 S oc     every part type.<br>W IL 2. Safe operation in Avalanche is allowed as long asTjmax is<br>  not exceeded.<br>80 3. Equation below based on circuit and waveforms shown in<br>C ST<br>  Figures 17a, 17b.<br>60 4. PD (ave) = Average power dissipation per single<br>A N     avalanche pulse.<br>5. BV = Rated breakdown voltage (1.3 factor accounts for<br>40 C OTES     voltage increase during avalanche).<br>6. Iav = Allowable avalanche current.<br>20 7. ∆T = Allowable rise in junction temperature, not to exceed<br>B ERR RRRANGEE<br>    Tjmax (assumed as 25°C in Figure 14, 15).<br>0 P ETE   tav = Average time in avalanche.<br>25 50 75 100 125 SS 150 175   D = Duty cycle in avalanche =  tav ·f<br>  ZthJC(D, tav) = Transient thermal resistance, see figure 11)<br>Starting TJ , Junction Temperature (°C) PD (ave) = 1/2 ( 1.3·BV·Iav) =  = 1/2 ( 1.3·BV·Iav) = ) = T/ ZthJC<br>EAR , Avalanche Energy (mJ)<br>-Avalanche Current (A)<br>**----- End of picture text -----**<br>


**PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC** 

**Iav = 2 T/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav** 

**Fig 15.** Maximum Avalanche Energy Vs. Temperature 

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Driver Gate Drive<br>P.W.<br>D.U.T + Period — D = ——<br>+ P.W. Period<br>VGS=10V<br>)    •  ] t<br> •<br>P| ©) - Circuit  •   GroundLow LayoutLeakage Plane ConsiderationsInductance ® D.U.T. ISD Waveform i<br>+<br>Reverse<br>Recovery Body Diode Forward<br>® - a = Current Transformer - ® + Current r Current ™=— di/dt /<br>O 00 ©) D.U.T. VDS Waveform Diode Recoverydv/dt \ ny VDD<br>•   Re-Applied<br>•   Driver same type as D.U.T. + Voltage Body Diode  Forward Drop<br>Re ( 4 •   dvidt controlled by Re Vpp - Inducto ee<br>•<br>D.U.T. - Device Under Test Cc es ee<br>Ripple  ≤ 5% ISD<br>O Isp controlled by Duty Factor "D" @ r<br>* Reverse Polarity of D.U.T for P-Channel * Vigg = 5V for Logic Level Devices<br>Fig 16. Peak Diode Recovery dv/dt Test Circuit for P-Channel<br>HEXFET ® Power MOSFETs<br>VDS L<br>Vpsy — R<br>RG D.U.T il VDD R<br>IAS ° A cS D.U.T.<br>5 aeTF DRIVER Re Vi<br>tp 0.01Ω -<br>+<br>i -10V<br>Pulse Width ≤ 1  ys<br>Duty Factor ≤ 0.1 %<br>15V<br>Fig 17a. Unclamped Inductive Test Circuit Fig 18a. Switching Time Test Circuit<br>IAS<br>td(on) tr td(off) tf<br>VGS<br>| fo<br>\ 10% il a >| |+>\<br>90%<br><—_ tp VDS JA\<br>V(BR)DSS<br>Fig 17b. Unclamped Inductive Waveforms Fig 18b. Switching Time Waveforms<br>Id<br>Vds<br>Vgs<br>L<br>VCC<br>DUT<br>0<br>Vgs(th)<br>1K<br>Qgs1 Qgs2 Qgd Qgodr<br>**----- End of picture text -----**<br>


**Fig 19b** Gate Charge Waveform 

**Fig 19a.** Gate Charge Test Circuit 

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EXAMPLE: THIS IS AN IRFR120<br>PART NUMBER<br>WITH ASSEMBLY<br>INTERNATIONAL<br>LOT CODE 1234 RECTIFIER IRFU120 DATE CODE<br>ASSEMBLED ON WW 16, 1999 LOGO 916A YEAR 9 =  1999<br>IN THE ASSEMBLY LINE "A" 12 34 WEEK 16<br>c a<br>LINE A<br>Note: "P" in assembly line position ASSEMBLY eat<br>indicates "Lead-Free" LOT CODE<br>OR<br>PART NUMBER<br>INTERNATIONAL A<br>RECTIFIER IRFU120 DATE CODE<br>LOGO IeaR P9i6A P =  DESIGNATES LEAD-FREE<br>PRODUCT (OPTIONAL)<br>12 34<br>YEAR 9 =  1999<br>ASSEMBLY<br>yu WEEK 16<br>LOT CODE<br>A =  ASSEMBLY SITE CODE<br>**----- End of picture text -----**<br>


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EXAMPLE: THIS IS AN IRFU120 PART NUMBER<br>INTERNATIONAL<br>WITH ASSEMBLY<br>LOT CODE 5678 RECTIFIER IRFU120 DATE CODE<br>LOGO 919A YEAR 9 =  1999<br>ASSEMBLED ON WW 19, 1999 56 78 WEEK 19<br>IN THE ASSEMBLY LINE "A"<br>LINE A<br>ASSEMBLY<br>Note:  "P" in assembly line  LOT CODE<br>position indicates "Lead-Free"<br>aT<br>OR<br>PART NUMBER<br>INTERNATIONAL ——<br>RECTIFIER IRFU120 DATE CODE<br>LOGO P =  DESIGNATES LEAD-FREE<br>56 78 PRODUCT (OPTIONAL)<br>YEAR 9 =  1999<br>ASSEMBLY WEEK 19<br>LOT CODE A =  ASSEMBLY SITE CODE<br>**----- End of picture text -----**<br>


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TR TRR TRL<br>eoGoooG od) | e$ooo/ 1<br>16.3 ( .641 ) 16.3 ( .641 )<br>15.7 ( .619 ) 15.7 ( .619 )<br>12.1 ( .476 ) FEED DIRECTION 8.1 ( .318 ) FEED DIRECTION<br>11.9 ( .469 ) od 7.9 ( .312 ) —_<br>**----- End of picture text -----**<br>


NOTES : 

1.  CONTROLLING DIMENSION : MILLIMETER. 

2.  ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 

3.  OUTLINE CONFORMS TO EIA-481 & EIA-541. 

**==> picture [38 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
  13 INCH<br>**----- End of picture text -----**<br>


**==> picture [27 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
16 mm<br>**----- End of picture text -----**<br>


NOTES : 

1. OUTLINE CONFORMS TO EIA-481. 

www.irf.com 

9 

Notes: ® Repetitive rating;  pulse width limited by © Contact factory for mounting information max. junction temperature. @ Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive avalanche information ® Starting TJ = 25°C, L = 1.24mH, When D-Pak mounted on 1" square PCB (FR-4 or G-10 Material) . RG = 25Ω, IAS = -14A. For recommended footprint and soldering techniques refer to @ Pulse width ≤ 400µs; duty cycle ≤ 2%. application note #AN-994 ® This only applies for I-Pak, LS of D-Pak is[@] Refer to D-Pak package for Part Marking, Tape and Reel information. measured between lead and center of die contact 

Rθ is measured at TJ of approximately 90°C. 

Data and specifications subject to change without notice. This product has been designed  for the Industrial market. Qualification Standards can be found on IR’s Web site. 

**IR WORLD HEADQUARTERS:** 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 

TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information **.** 12/04 

www.irf.com 

10 

Note:  For the most current drawings please refer to the IR website at: http://www.irf.com/package/ 



## Links

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- [Supplier page](https://es.farnell.com/infineon/irlr9343trpbf/mosfet-p-ch-55v-20a-to-252aa/dp/2726028)
---

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