# Power MOSFET, N Channel, 55 V, 25 A, 0.037 ohm, TO-252AA, Surface Mount

![Product image](https://novapart.co/image/farnell:2726016/)

**URL**: https://novapart.co/products/IRLR3105TRPBF/power-mosfet-n-channel-55-v-25-a-0037-ohm-to-252aa
**SKU**: IRLR3105TRPBF
**Manufacturer**: INFINEON
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.4720
**Stock**: 1000+
**Lead Time**: 190 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:25A; Drain Source Voltage Vds:55V; On Resistance Rds(on):0.03ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:3V; Power

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | HEXFET |
| Qualification | - |
| Power Dissipation | 57W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252AA |
| Drain Source Voltage Vds | 55V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 25A |
| Drain Source On State Resistance | 0.037ohm |
| Gate Source Threshold Voltage Max | 3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2726016/)

PD - 95553B 

## **Features** 

Logic-Level Gate Drive Advanced Process Technology Ultra Low On-Resistance 175°C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax Lead-Free 

## IRLR3105PbF IRLU3105PbF HEXFET[®] Power MOSFET 

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D<br>VDSS = 55V<br>R  = 0.037 Ω<br>DS(on)<br>G<br>ID = 25A<br>S<br>**----- End of picture text -----**<br>


## **Description** 

This HEXFET[®] Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable device for use in a wide variety of  applications. 

The D-Pak is designed for surface mounting using vapor  phase, infrared, or wave soldering techniques.  The straight lead version (IRLU series) is for through-hole mounting applications.  Power dissipation levels up to 1.5 watts are possible in typical surface mount applications. 

|'<br>¢|~~.|
|---|---|
|D-Pak|I-Pak|
|IRLR3105PbF|IRLU3105PbF|



## **Absolute Maximum Ratings** 

|iJ<br>~~a~~|**Parameter**<br>iJ<br>~~ee~~<br>|**Max.**<br>iJ<br>~~oe~~<br>|**Max.**<br>iJ<br>~~oe~~<br>|**Units**<br>iJ<br>~~oe~~<br>|
|---|---|---|---|---|
|ID@ TC= 25°C<br>—<br>~~a~~|Continuous Drain Current, VGS@ 10V<br>—<br>~~ee~~<br>|25<br>—<br>~~oe~~<br>||A<br>—<br>~~oe~~<br>©|
|ID@ TC= 100°C<br>—<br>~~a~~|Continuous Drain Current, VGS@ 10V<br>—<br>~~ee~~<br>|18<br>—<br>~~oe~~<br>|||
|IDM<br>~~a~~|Pulsed Drain Current<br>~~ee~~<br>©|100<br>~~oe~~<br>©|||
|PD@TC= 25°C<br>~~a ~~<br>~~a~~|Power Dissipation<br>~~ee~~<br> <br>~~a~~|57<br>~~oe~~<br><br>~~a~~||W<br>~~oe~~<br><br>~~a~~|
|~~a~~|Linear DeratingFactor<br>~~a~~|0.38<br>~~a~~||W/°C<br>~~a~~|
|VGS<br>~~a~~|Gate-to-Source Voltage<br>~~a~~|± 16<br>~~a~~||V<br>~~a~~|
|EAS<br>~~oo~~<br>~~ee~~|Single Pulse Avalanche Energy<br>~~oo~~<br>~~ee~~|61<br>~~oo~~<br>~~ee~~||mJ<br>~~ee~~<br>~~eee~~|
|EAS(tested)<br>~~ee~~<br>~~a~~|Single Pulse Avalanche EnergyTested Value<br>~~ee~~<br>|94<br>~~ee~~<br>|||
|IAR<br>~~ee~~<br>~~a~~|Avalanche Current<br>~~ee~~<br>|See Fig.12a, 12b, 15, 16<br>~~ee~~<br>||A<br>~~ee~~<br>~~eee~~|
|EAR<br>~~ee~~<br>~~a~~|Repetitive Avalanche Energy<br>~~ee~~<br>|||mJ<br>~~ee~~<br>~~eee~~|
|dv/dt<br>~~a~~|Peak Diode Recoverydv/dt<br>|3.4<br>||V/ns<br>~~eee~~|
|TJ<br>TSTG<br>~~a~~|Operating Junction and<br>Storage Temperature Range<br>~~a~~|-55  to + 175<br>~~a~~|||
|~~a~~|Soldering Temperature, for 10 seconds<br>~~a~~|300 (1.6mm from case )<br>~~a~~|||
|**Thermal Resistance**<br>~~a~~|||||
||**Parameter**|**Typ.**|**Max.**|**Units**|
|RθJC|Junction-to-Case|–––|2.65|°C/W|
|RθJA|Junction-to-Ambient (PCB mount)*|–––|50||
|RθJA|Junction-to-Ambient|–––|110||



## **Thermal Resistance** 

|||~~ee ed~~|~~ed~~||||
|---|---|---|---|---|---|---|
|~~oe~~|**Parameter**<br>ee<br>~~oe~~|**Min.**<br>ee<br>~~ee ed~~<br>~~ed~~<br>~~oe~~|**Typ. **<br>ee<br>~~ed~~<br>~~ed~~<br>~~oe~~|**Max. **<br>ee<br>~~oe~~|**Units**<br>ee<br>~~oe~~|**Conditions**<br>~~2~~|
|V(BR)DSS<br>~~oe~~|Drain-to-Source Breakdown Voltage<br>~~es~~<br>~~oe~~|55<br>~~ee ed~~<br>~~es~~<br>~~ed~~<br>~~oe~~|–––<br>~~ed~~<br>~~es~~<br>~~ed~~<br>~~oe~~|–––<br>~~es~~<br>~~oe~~|V<br>~~es~~<br>~~oe~~|VGS= 0V, ID= 250µA<br>~~2~~|
|∆V(BR)DSS/∆TJ<br>~~oe~~|Breakdown Voltage Temp. Coefficient<br>~~+};~~<br>~~oe~~|–––<br>~~ed~~<br>~~+};~~<br>~~oe~~|0.056<br>~~ed~~<br>~~+};~~<br>~~oe~~|–––<br>~~+};~~<br>~~oe~~|V/°C<br>~~+};—~~<br>~~oe~~|Reference to 25°C, ID= 1mA<br>~~7~~<br>~~2~~|
|RDS(on)<br>~~oe~~|Static Drain-to-Source On-Resistance<br>~~+};~~<br>~~oe~~|–––<br>~~+};~~<br>~~oe~~|30<br>~~+};~~<br>~~oe~~|37<br>~~+};~~<br>~~oe~~|mΩ<br>~~+}; —~~<br>~~oe~~|VGS= 10V, ID= 15A<br>~~7~~<br>~~2~~|
|||–––<br>~~+};~~<br>~~oe~~|35<br>~~+};~~<br>~~oe~~|43<br>~~+};~~<br>~~oe~~||VGS= 5.0V, ID= 13A<br>~~7~~<br>~~2~~|
|VGS(th)<br>~~oe~~<br>~~a~~|Gate Threshold Voltage<br>~~oe~~<br>~~es~~<br>~~a~~|1.0<br>~~oe~~<br>~~es~~|–––<br>~~oe~~<br>~~es~~|3.0<br>~~oe~~<br>~~es~~|V<br>~~oe~~<br>~~es~~|VDS= VGS, ID= 250µA<br>~~2~~<br>~~®~~|
|gfs<br>~~oe~~<br>~~a~~|Forward Transconductance<br>~~oe~~<br>~~a~~|15<br>~~oe~~|–––<br>~~oe~~|–––<br>~~oe~~|S<br>~~oe~~|VDS= 25V, ID= 15A<br>~~2~~<br>~~®~~|
|IDSS<br>~~oe~~<br>~~a~~|Drain-to-Source Leakage Current<br>~~oe~~<br>~~a~~<br>~~EE~~<br>~~**|**~~|–––<br>~~oe~~<br>~~EE~~<br>~~**|**~~|–––<br>~~oe~~<br>~~EE~~|20<br>~~oe~~<br>~~EE~~|µA<br>~~oe~~<br>~~EE~~|VDS= 55V, VGS= 0V<br>~~2~~<br>~~®~~|
|||–––<br>~~oe~~<br>~~EE~~<br>~~**|**~~|–––<br>~~oe~~<br>~~EE~~|250<br>~~oe~~<br>~~EE~~||VDS= 44V, VGS= 0V, TJ= 150°C<br>~~2~~|
|~~oe~~<br>~~less~~<br>~~a~~|Gate-to-Source Forward Leakage<br>~~oe~~<br>~~**|**~~<br>~~a~~|–––<br>~~oe~~<br>~~**|**~~<br>|–––<br>~~oe~~<br>|200<br>~~oe~~<br>|nA<br>~~oe~~<br>|VGS= 16V<br>~~2~~|
||Gate-to-Source Reverse Leakage<br>~~oe~~<br>~~a~~|–––<br>~~oe~~<br>|–––<br>~~oe~~<br>|-200<br>~~oe~~<br>||VGS= -16V<br>~~2~~|
|Qg<br>~~oe~~<br>~~less~~<br>~~a~~|Total Gate Charge<br>~~oe~~<br>~~a~~|–––<br>~~oe~~<br>|–––<br>~~oe~~<br>|20<br>~~oe~~<br>|nC<br>~~oe~~<br>~~ee~~|ID= 15A<br>VDS= 44V<br>VGS= 5.0V, See Fig. 6 and 13<br>~~2~~|
|Qgs<br><br>~~———————~~|Gate-to-Source Charge<br><br>~~———————~~|–––<br><br>~~———————~~|–––<br>|5.6<br>|||
|gs<br>Qgd<br><br>~~———————~~|Gate-to-Drain("Miller")Charge<br>~~ee~~<br>~~———————~~|–––<br>~~ee~~<br>~~———————~~|–––<br>~~ee~~|9.0<br>~~ee~~|||
|td(on)<br>~~———————~~<br>ee|Turn-On Delay Time<br>~~———————~~<br>~~ee~~|–––<br>~~———————~~<br>~~ee~~|8.0<br>~~ee~~|–––<br>~~ee~~|~~ee~~|VDD= 28V<br>ID= 15A<br>RG= 24Ω<br>VGS= 5.0V, See Fig. 10|
|tr<br>~~———————~~<br>ee<br>es|Rise Time<br>~~———————~~<br>~~ee~~|–––<br>~~———————~~<br>~~ee~~|57<br>~~ee~~|–––<br>~~ee~~|||
|td(off)<br>~~———————~~<br>ee<br>es|Turn-Off Delay Time<br>~~———————~~<br>~~ee~~|–––<br>~~———————~~<br>~~ee~~|25<br>~~ee~~|–––<br>~~ee~~|||
|d(off)<br>tf<br>~~———————~~<br>es|Fall Time<br>~~———————~~|–––<br>~~———————~~|37|–––|||
|LD<br>~~———————~~<br>~~po}~~|Internal Drain Inductance<br>~~———————~~<br>~~po}~~<br>~~ne~~|–––<br>~~———————~~|4.5|–––||Between lead,<br>6mm (0.25in.)<br>from package<br>and center of die contact<br>S<br>D<br>G<br>|<br>~~&~~|
|LS<br>~~po}~~<br>~~ee~~|Internal Source Inductanc<br>~~po}~~<br>~~ne~~<br>|–––<br>ee<br>|7.5<br>ee<br>|–––<br>|||
|Ciss<br>~~po}~~<br>~~ee~~|Input Capacitance<br>~~po}~~<br>~~ne~~<br>~~es~~<br>|–––<br>~~es~~<br>ee<br>|710<br>~~es~~<br>ee<br>|–––<br>~~es~~<br>|VGS= 0V<br>VDS= 25V<br>pF<br>ƒ = 1.0MHz, See Fig. 5<br>VGS= 0V,  VDS= 1.0V,  ƒ = 1.0MHz<br>VGS= 0V,  VDS= 44V,  ƒ = 1.0MHz<br>VGS= 0V, VDS= 0V to 44V<br>|<br>~~&~~<br>~~es~~<br>~~ee~~|VGS= 0V<br>VDS= 25V<br>ƒ = 1.0MHz, See Fig. 5<br>|<br>~~&~~|
|Coss<br>~~po}~~<br>~~ee~~<br>es|Output Capacitance<br>~~po}~~<br>~~ne~~<br>~~ee~~<br>|–––<br>ee<br>~~ee~~|150<br>ee<br>~~ee~~|–––<br>~~ee~~|||
|Crss<br>~~ee~~<br>esen|Reverse Transfer Capacitance<br>~~ee~~<br>en|–––<br>ee <br>~~ee~~|28<br> ee<br>~~ee~~|–––<br>~~ee~~|||
|Coss<br><br>esen|Output Capacitance<br>~~ee~~<br>en|–––<br>~~ee~~|890<br>~~ee~~|–––<br>~~ee~~||VGS= 0V,  VDS= 1.0V,  ƒ = 1.0MHz|
|Coss<br>en<br>a|Output Capacitance<br>en<br>ee|–––<br>ee|110<br>ee|–––<br>ee||VGS= 0V,  VDS= 44V,  ƒ = 1.0MHz|
|Cosseff.<br>en<br>a|Effective Output Capacitance<br>en<br>ee|–––<br>ee|210<br>ee|–––<br>ee|||



When mounted on 1" square PCB (FR-4 or G-10 Material) . For recommended footprint and soldering techniques refer to application note #AN-994 Notes through are  on page 11 

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1000 100<br>VGS VGS<br>TOP          15V TOP          15V<br>                  10V |                   10V eneo<br>                  5.0V                   5.0V<br>100              3.0V siti ail all                   3.0V H arry|<br>                  2.7V                   2.7V<br>                  2.5V                   2.5V<br>                  2.25V 10              2.25V<br>10 Pe BOTTOM 2.0V n ||oe| Ee BOTTOM 2.0V FHHH<br>F eae eee ae 7 Za or |<br>Cam di ———— ee | fy e o<br>AC eer Yi<br>1<br>o y 1 A a 2.0V al<br>0.1<br>S h PAA tH tH<br>2.0V 20µs PULSE WIDTH 20µs PULSE WIDTH<br>0.01 ctl Tj = 25°C Pith 0.1 Tj = 175°C<br>an ieee VARI |<br>0.1 1 10 100 0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)<br>Fig 1.   Typical Output Characteristics Fig 2.   Typical Output Characteristics<br>1000.00 30<br>TJ = 25°C TJ = 175°C<br>25<br>100.00<br>a a<br>eeeee eee TJ = 175°C 20<br>a L e<br>10.00 T = 25°C<br>J<br>a ————— 15 VA<br>yy |<br>1.00<br>rP ro] 10 L| f<br>rr ee ee ee ee eee /<br>0.10<br>S rrSSeee eee VDS  SS = 25V 5 VDS = 25V<br>— 20µs PULSE WIDTH 20µs PULSE WIDTH<br>0.01 0<br>2.0 4.0 6.0 8.0 0 10 20 30 40<br>VGS, Gate-to-Source Voltage (V) ID, Drain-to-Source Current (A)<br>A) Gfs, Forward Transconductance (S)<br> (<br>ID, Drain-to-Source Current<br>ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 3.** Typical Transfer Characteristics 

**Fig 4.** Typical Forward Transconductance Vs. Drain Current 

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1600<br>VGS   = 0V,       f = 1 MHZ<br>Ciss    = Cgs + Cgd,   C ds    SHORTED<br>C   = C<br>rss   gd<br>1200 Coss   = Cds + Cgd<br>Ciss<br>S n<br>800 X ——a<br>Coss<br>400<br>Crss<br>S |<br>0<br>1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 5.   Typical Capacitance Vs.<br>Drain-to-Source Voltage<br>100.0<br>TJ = 175°C<br>10.0<br>1.0 | Tf} Ay tt<br>T = 25°C<br>J<br>VGS = 0V<br>0.1 re<br>0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8<br>VSD, Source-toDrain Voltage (V)<br>ISD, Reverse Drain Current (A)<br>C, Capacitance (pF)<br>**----- End of picture text -----**<br>


**Fig 7.** Typical Source-Drain Diode Forward Voltage 

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20<br>ID= 15A<br>VDS= 44V<br>16 ee VDS= 28V<br>VDS= 11V<br>12<br>8 n /n<br>4<br>FOR TEST CIRCUIT<br>SEE FIGURE 13<br>0 [|<br>0 10 20 30 40<br> QG  Total Gate Charge (nC)<br>VGS, Gate-to-Source Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 6.** Typical Gate Charge Vs. Gate-to-Source Voltage 

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1000<br>OPERATION IN THIS AREA<br>LIMITED BY RDS(on)<br>100<br>10 100µsec<br>pi et 1msec<br>1<br>10msec<br>Tc = 25°C<br>Tj = 175°C<br>Single Pulse<br>0.1 TOC Con<br>1 10 100 1000<br>VDS  , Drain-toSource Voltage (V)<br>ID,  Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 8.** Maximum Safe Operating Area 

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30 3.0<br>ID = 25A<br>Pt tT | tt tt td P E<br>25 Pi} dt tt | | TT 2.5 PT tT tT ELEte tT EEttt ECEtt tl<br>PS tt EE PTT tT teeTy<br>20 Pi PN 2.0 PT tT tT eT tT tt tt yy<br>pit PN EEE ET ttt ttt tT yt<br>15 1.5<br>FEE RCEIN FECvA<br>10 CEEEECCCCENE 1.0 no>aeeeeeee—||<br>5 0.5<br>FEE EEEEEEN FARCE<br>V GS = 10V<br>0 ft ttt | ft | tT | | | 0.0 PiT tT tT ett [t] [t]<br>25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100 120 140 160 180<br>T   , Case TemperatureC (  C)° T  , Junction TemperatureJ (    C)°<br>Fig 9.   Maximum Drain Current Vs. Fig 10.   Normalized On-Resistance<br>Case Temperature Vs. Temperature<br> 10<br>a<br>D = 0.50<br> 1 p e | |<br>0.20<br>0.10<br>eg a Oe<br>0.05<br>e et SINGLE PULSE P DM<br>0.02 (THERMAL RESPONSE)<br>0.1 0.01<br>== ee | t 1<br>t 2<br>P e<br>Notes:<br>1. Duty factor D = t   / t1 2<br>ce 2. Peak T J = P DM x  Z thJC + T C<br>0.01 nih te<br>0.00001 0.0001 0.001 0.01 0.1<br>t  , Rectangular Pulse Duration (sec)1<br>(Normalized)<br>I   , Drain Current (A)D<br>DS(on)<br>R            , Drain-to-Source On Resistance<br>thJC<br>(Z          )<br>Thermal Response<br>**----- End of picture text -----**<br>


**Fig 11.** Maximum Effective Transient Thermal Impedance, Junction-to-Case 

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100<br>15V I D<br>Pt Tt<br>TOP 6.1A<br>11A<br>NESE<br>VDS L DRIVER 80 BOTTOM 15A<br>ENE<br>RG D.U.T + 60 NEf N<br>- [V][DD]<br>IAS A<br>aa 20VVGS RNGNSS<br>tp 0.01 Ω<br>40<br>*l PARR<br>Fig 12a.   Unclamped Inductive Test Circuit PtASA<br>V(BR)DSS<br>20<br>P| tT SSA<br>tp Pf | SS<br>0<br>25 50 75 100 125 150 175<br>//\ Pt Starting Tj, Junction Temperature ASN (   C)°<br>|<br>IAS 7<br>Fig 12c.   Maximum Avalanche Energy<br>Fig 12b.   Unclamped Inductive Waveforms<br>Vs. Drain Current<br> * QG<br>10 ve<br>QGS QGD 2.0<br>VG ID = 250µA<br>J S T<br>1.5<br>Charge : H is t<br>Fig 13a.   Basic Gate Charge Waveform 1.0<br>L EAT<br>Current Regulator<br>Same Type as D.U.T.<br>50K Ω 0.5<br>12V cp .2 µ F E LE EL<br>.3 µ F<br>+<br>D.U.T. -VDS<br>ET E<br>0.0<br>VGS -75 -50 -25 0 25 50 75 100 125 150 175<br>3mA TJ , Temperature ( °C )<br>ot<br>IG ID<br>Current Sampling Resistors<br>Fig 13b.   Gate Charge Test Circuit Fig 14.   Threshold Voltage Vs. Temperature<br>6 www.irf.com<br>AS<br>E     , Single Pulse Avalanche Energy (mJ)<br>VGS(th) Gate threshold Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 12a.** Unclamped Inductive Test Circuit 

**Fig 12b.** Unclamped Inductive Waveforms 

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1000<br>Duty Cycle = Single Pulse<br>100 Allowed avalanche Current vs<br>avalanche pulsewidth, tav<br>0.01 assuming  ∆ Tj = 25°C due to<br>avalanche losses. Note: In no<br>10 case should Tj be allowed to<br>0.05 exceed Tjmax<br>0.10<br>1<br>a<br>0.1 een ee ee ell<br>1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01<br>tav (sec)<br>Fig 15.   Typical Avalanche Current Vs.Pulsewidth<br>70 Notes on Repetitive Avalanche Curves , Figures 15, 16:<br>TOP          Single Pulse                 (For further info, see AN-1005 at www.irf.com)<br>60 BOTTOM   50% Duty Cycle 1. Avalanche failures assumption:<br>ID = 15A   Purely a thermal phenomenon and failure occurs at a<br>S e     temperature far in excess of Tjmax. This is validated for<br>50 N E     every part type.<br>2. Safe operation in Avalanche is allowed as long asTjmax is<br>  not exceeded.<br>40<br>N EEL 3. Equation below based on circuit and waveforms shown in<br>  Figures 12a, 12b.<br>30 4. PD (ave) = Average power dissipation per single<br>E AN ETT<br>    avalanche pulse.<br>20 5. BV = Rated breakdown voltage (1.3 factor accounts for<br>S ERRE NGREEE     voltage increase during avalanche).<br>10 6. Iav = Allowable avalanche current.<br>L TT NYT 7.  ∆ T = Allowable rise in junction temperature, not to exceed<br>pitETT     Tjmax (assumed as 25°C in Figure 15, 16).<br>0 AL   tav = Average time in avalanche.<br>25 50 75 100 125 150 175   D = Duty cycle in avalanche =  tav ·f<br>Starting TJ , Junction Temperature (°C)   ZthJC(D, tav) = Transient thermal resistance, see figure 11)<br>EAR , Avalanche Energy (mJ)<br>Avalanche Current (A)<br>**----- End of picture text -----**<br>


**Fig 16.** Maximum Avalanche Energy Vs. Temperature 

- **PD (ave) = 1/2 ( 1.3·BV·Iav) =** A **T/ ZthJC Iav = 2** A **T/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav** 

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Driver Gate Drive<br>P.W.<br>D.U.T + Period — D = ——<br>+ P.W. Period<br>) ©)    •  Circuit Layout Considerations fi V t GS=10V<br> •<br>| =] - LowGround StrayPla I n eductance<br> •   CurrentLow LeakageTransformerInductance ® D.U.T. ISD Waveform<br>+<br>Reverse<br>® - a 38c - ® + RecoveryCurrent r Body Diode ForwardCurrent di/dt /vy<br>® D.U.T. VDS Waveform Diode Recoverydv/dt ‘ '<br>00 _ VDD<br>iv<br>•   Re-Applied<br>•   Driver same type as D.U.T. + Voltage Body Diode  Forward Drop<br>Re ( 4 •   dvidt controlled by Re Vop - Inductor Curent<br>•   D.U.T. - Device Under Test es ee<br>Isp controlled by Duty Factor "D" ® Ripple  ≤ 5% ISD<br>**----- End of picture text -----**<br>


## **Fig 17.** Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET ® Power MOSFETs 

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-<br>≤ 1  ys<br>≤ 0.1 %<br>**----- End of picture text -----**<br>


**Fig 18a.** Switching Time Test Circuit 

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VDS<br>90%<br>10%<br>VGS |\< ve >!\ vie<br>td(on) tr td(off) tf<br>**----- End of picture text -----**<br>


**Fig 18b.** Switching Time Waveforms 

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**==> picture [255 x 136] intentionally omitted <==**

**----- Start of picture text -----**<br>
EXAMPLE: THIS IS AN IRFR120<br>WITH ASSEMBLY INTERNATIONAL a PART NUMBER<br>LOT CODE 1234 RECTIFIER IRFR120 DATE CODE<br>ASSEMBLED ON WW 16, 2001 LOGO 116A YEAR 1 =  2001<br>IN THE ASSEMBLY LINE "A" 12 34 WEEK 16<br>LINE A<br>Note: "P" in assembly line positionindicates "Lead-Free" ASSEMBLYLOT CODE i a t<br>"P" in assembly line position indicates<br>"Lead-Free" qualification to the consumer-level<br>PART NUMBER<br>INTERNATIONAL cS<br>OR RECTIFIER IRFR120 P =  DESIGNATES LEAD-FREEDATE CODE<br>LOGO PRODUCT (OPTIONAL)<br>12 34 P =  DESIGNATES LEAD-FREE<br>ASSEMBLYLOT CODE i iam t PRODUCT QUALIFIED TO THECONSUMER LEVEL (OPTIONAL)<br>YEAR 1 =  2001<br>WEEK 16<br>A =  ASSEMBLY SITE CODE<br>**----- End of picture text -----**<br>


## **Notes: 1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/ 2. For the most current drawing please refer to IR website at http://www.irf.com/package/** www.irf.com 

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**==> picture [239 x 129] intentionally omitted <==**

**----- Start of picture text -----**<br>
EXAMPLE: THIS IS AN IRFU120 PART NUMBER<br>WITH ASSEMBLYLOT CODE 5678ASSEMBLED ON WW 19, 2001 INTERNATIONALRECTIFIERLOGO a 56IRFU120119A78 DATE CODEYEAR 1 =  2001WEEK 19<br>IN THE ASSEMBLY LINE "A"<br>LINE A<br>ASSEMBLY<br>LOT CODE<br>Note: "P" in assembly line position<br>indicates Lead-Free"<br>OR<br>PART NUMBER<br>INTERNATIONAL co N<br>RECTIFIER IRFU120 DATE CODE<br>LOGO P =  DESIGNATES LEAD-FREE<br>56 78 PRODUCT (OPTIONAL)<br>ASSEMBLY YEAR 1 =  2001<br>LOT CODE WEEK 19<br>A =  ASSEMBLY SITE CODE<br>**----- End of picture text -----**<br>


## **Notes: 1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/ 2. For the most current drawing please refer to IR website at http://www.irf.com/package/** 10 

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**==> picture [282 x 242] intentionally omitted <==**

**----- Start of picture text -----**<br>
TR TRR TRL<br>16.3 ( .641 ) 16.3 ( .641 )<br>15.7 ( .619 ) 15.7 ( .619 )<br>12.1 ( .476 ) Cac FEED DIRECTION 8.1 ( .318 ) FEED DIRECTION -<br>11.9 ( .469 ) 7.9 ( .312 )<br>NOTES :<br>1.  CONTROLLING DIMENSION : MILLIMETER.<br>2.  ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).<br>3.  OUTLINE CONFORMS TO EIA-481 & EIA-541.<br>|   13 INCH<br>16 mm<br>ma =<br>**----- End of picture text -----**<br>


NOTES : 

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1. OUTLINE CONFORMS TO EIA-481.<br>**----- End of picture text -----**<br>


Repetitive rating;  pulse width limited by Cossoss eff. is a fixed capacitance that gives the same charging time max. junction temperature. as Coss while VDS is rising from 0 to 80% VDSS .oss while VDS is rising from 0 to 80% VDSS .while VDS is rising from 0 to 80% VDSS .DS is rising from 0 to 80% VDSS .is rising from 0 to 80% VDSS .DSS . . ®© Limited by TJmax, starting TJ = 25°C, L = 0.55mH Limited by TJmax ' Jmax ' see Fig 12a, 12b, 15, 16 for typical repetitive RG = 25 Ω , IAS = 15A, VGS =10V avalanche performance. ® ISD ≤ 25A, di/dt ≤ 290A/µs, VDD ≤ V(BR)DSS, ® This value determined from sample failure population. 100% TJ ≤ 175°C 

Cossoss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS .oss while VDS is rising from 0 to 80% VDSS .while VDS is rising from 0 to 80% VDSS .DS is rising from 0 to 80% VDSS .is rising from 0 to 80% VDSS .DSS . . 

Limited by TJmax ' Jmax ' see Fig 12a, 12b, 15, 16 for typical repetitive avalanche performance. 

® This value determined from sample failure population. 100% tested to this value in production. 

Pulse width ≤ 300µs; duty cycle ≤ 2%. 

Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. 

**IR WORLD HEADQUARTERS:** 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information **.** 10/2010 

www.irf.com 

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## **IMPORTANT NOTICE** 

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With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. 

In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. 

The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. 

For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office ( **www.infineon.com** ). 

## **WARNINGS** 

Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. 

Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. 



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---

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