# Power MOSFET, N Channel, 40 V, 327 A, 1700 µohm, TO-247AC, Through Hole

![Product image](https://novapart.co/image/farnell:1758306/)

**URL**: https://novapart.co/products/IRLP3034PBF/power-mosfet-n-channel-40-v-327-a-1700-ohm-to
**SKU**: IRLP3034PBF
**Manufacturer**: INFINEON
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.6100
**Stock**: 200+
**Lead Time**: 2 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:327A; Drain Source Voltage Vds:40V; On Resistance Rds(on):0.0014ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:2.5V;

## Specifications

| Parameter | Value |
|---|---|
| Msl | - |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 341W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-247AC |
| Drain Source Voltage Vds | 40V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 327A |
| Drain Source On State Resistance | 1700µohm |
| Gate Source Threshold Voltage Max | 2.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:1758306/)

96230 

## IRLP3034PbF 

HEXFET ® Power MOSFET 

## **Applications** 

DC Motor Drive D **VDSS 40V** High Efficiency Synchronous Rectification in SMPS **RDS(on)   typ. 1.4m** Uninterruptible Power Supply **max. 1.7m** ~~:e~~ High Speed Power SwitchingHard Switched and High Frequency Circuits G **ID (Silicon Limited)** ~~on~~ **327A** S **ID (Package Limited)** ~~|~~ **195A** 

## **Benefits** 

Optimized for Logic Level Drive Very Low RDS(ON) at 4.5V VGS Superior R*Q at 4.5V VGS 

Improved  Gate, Avalanche and Dynamic  dV/dt Ruggedness 

Fully Characterized Capacitance and Avalanche SOA 

Enhanced body diode dV/dt and dI/dt Capability Lead-Free 

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TO-247AC IRLP3034PbF 

|**G**<br>**D**<br>**S**|
|---|
|Gate<br>Drain<br>Source|
|**Absolute Maximum Ratings**|
|**Symbol**<br>**Parameter**<br>**Units**<br>ID@ TC= 25°C<br>Continuous Drain Current, VGS@ 10V(Silicon Limited)<br>ID@ TC= 100°C<br>Continuous Drain Current, VGS@ 10V(Silicon Limited)<br>ID@ TC= 25°C<br>Continuous Drain Current, VGS@ 10V(Package Limited)<br>IDM<br>Pulsed Drain Current<br>PD@TC= 25°C<br>Maximum Power Dissipation<br>W<br>Linear DeratingFactor<br>W/°C<br>VGS<br>Gate-to-Source Voltage<br>V<br>A<br>341<br>±20<br>2.3<br>**Max.**<br>327<br>232<br>1308<br>195<br>~~oT~~<br>~~TVv~~<br>~~TOS".~~<br>~~TT~~<br>~~M@§4-AWAT(0vVOTNT.Y—._~~<br>~~TT~~<br>~~ST~~<br>~~NHoowx+*.*t.w.~~<br>~~OT~~<br>~~o-.oNOoN~~<br>~~a~~|
|dv/dt<br>Peak Diode Recovery<br>V/ns<br>4.6<br>~~2G~~|
|TJ<br>Operating Junction and<br>TSTG<br>Storage Temperature Range<br>°C<br>-55  to + 175|
|Soldering Temperature, for 10 seconds<br>300|
|(1.6mm from case)|
|Mountingtorque,6-32 or M3 screw<br>**Avalanche Characteristics**<br>EAS(Thermallylimited)<br>Single Pulse Avalanche Energy<br>mJ<br>IAR<br>Avalanche Current<br>A<br>EAR<br>Repetitive Avalanche Energy<br>mJ<br>**Thermal Resistance**<br>**Symbol**<br>**Parameter**<br>**Typ.**<br>**Max.**<br>**Units**<br>RθJC<br>Junction-to-Case<br>–––<br>0.44<br>RθCS<br>Case-to-Sink,Flat,Greased Surface<br>0.24<br>–––<br>RθJA<br>Junction-to-Ambient<br>–––<br>40<br>See Fig. 14, 15, 22a, 22b,<br>°C/W<br>224<br>10lbf in(1.1N m)<br>~~a~~<br>~~NOa~~<br>~~ee oe ie~~<br>~~ooo~~<br>~~wN0W0wWW.]~~|



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04/21/09 

**Static @ TJ = 25°C (unless otherwise specified)** 

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|||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
|Symbol|Parameter|Min.|Typ.|Max.|Units|Conditions|
|V(BR)DSS|QO|Drain-to-Source Breakdown Voltage|40|–––|–––|GQ|V|VGS = 0V, ID = 250µA|
|∆V(BR)DSS/∆TJ|GQ|Breakdown Voltage Temp. Coefficient|–––|0.04|–––|OG|V/°C|Reference to 25°C, ID = 5mA|
|RDS(on)|||Static Drain-to-Source On-Resistance|––––––|1.41.6|1.72.0|mΩ|VVGSGS = 10V, I = 4.5V, IDD = 195A  = 172A|
|VIDSSGS(th)|a|Gate Threshold VoltaDrain-to-Source Leakage Currentge|–––1.0||QO|––––––|||2.520|GQ|V|VVDSDS = V = 40V, VGS, ID = 250GS = 0VµA|@|
|eS|–––|–––|250|µA|_—|VDS = 40V, VGS = 0V, TJ = 125°C|
|IGSS|Gate-to-Source Forward Leakage|–––|||–––|100|VGS = 20V|
|nA|
|Gate-to-Source Reverse Leakage|–––|–––|-100|VGS = -20V|
|RG(int)|——GQ|Internal Gate Resistance|||[|]|–––|||2.1|–––|GQ|Ω|
|Dynamic @ TJ = 25°C (unless otherwise specified)|
|Symbol|Parameter|Min.|Typ.|Max.|Units|Conditions|
|Qgfsg|eGa|Total Gate CharForward Transconductancege|286–––|–––108|QC|–––162|S|(|VIDDS = 185A = 10V, ID = 195A|
|Qgs|a|Gate-to-Source Charge|–––|29|–––|VDS = 20V|
|nC|
|Qgd|a|Gate-to-Drain ("Miller") Charge|–––|54|–––|VGS = 4.5V|®|
|Qsync|ee|Total Gate Charge Sync. (Qg - Qgd)|–––|54|–––|ID = 185A, VDS =0V, VGS = 4.5V|
|td(on)|a|Turn-On Delay Time|–––|65|–––|VDD = 26V|
|tr|a|Rise Time|–––|827|–––|ID = 195A|
|ns|
|td(off)|a|Turn-Off Delay Time|–––|97|–––|RG = 2.1Ω|
|tf|a|Fall Time|–––|355|–––|VGS = 4.5V|®|
|Ciss|a|Input Capacitance|–––|10315|–––|VGS = 0V|
|Coss|a|Output Capacitance|–––|1980|–––|VDS = 25V|
|Crss|a|Reverse Transfer Capacitance|–––|935|–––|pF|ƒ = 1.0MHz|
|Coss eff. (ER)|Effective Output Capacitance (Energy Related)|–––|2378|–––|VGS = 0V, VDS = 0V to 32V|
|Coss eff. (TR)|a)©|Effective Output Capacitance (Time Related)|–––|2986|–––|VGS = 0V, VDS = 0V to 32V|@|©|
|Diode|Characteristics|
|Symbol|Parameter|Min.|Typ.|Max.|Units|Conditions|
|IS|Continuous Source Current|–––|–––|MOSFET symbol|D|
|327|
|es|(Body Diode)|showing  the|
|ISM|Pulsed Source Current|–––|–––|A|integral reverse|G|
|1308|
|ee|(Body Diode)|p-n junction diode.|S|
|VSD|a|Diode Forward Voltage|–––|ee|–––|1.3|V|TJ = 25°C, IS = 195A, VGS = 0V|
|trr|Reverse Recovery Time|Gs|–––|GQ|39|–––|QO|TJ = 25°C|VR = 34V,|:|
|ns|
|ee|–––|41|–––|TJ = 125°C|IF = 195A|
|Qrr|Reverse Recovery Charge|–––|ee||39|–––|TJ = 25°C|ee|di/dt = 100A/µs|
|nC|
|–––|46|–––|TJ = 125°C|
|IRRM|a|Reverse Recovery Current|!|–––|||||1.7|–––|A|TJ = 25°C|
|ton|a|Forward Turn-On Time|Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)|

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Calcuted continuous current based on maximum allowable junction temperature Bond wire current limit is 195A. Note that current limitation arising from heating of the device leds may occur with some lead mounting arrangements. 

- Repetitive rating;  pulse width limited by max. junction temperature. 

Limited by TJmax, starting TJ = 25°C, L = 0.013mH 

## Pulse width ≤ 400µs; duty cycle ≤ 2%. 

© Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 

Coss eff. (ER) is a fixed capacitance that gives the same energy as 

Coss while VDS is rising from 0 to 80% VDSS. 

      - θ 

- RG = 25Ω, IAS = 195A, VGS =10V. Part not recommended for use above this value . 

   - ISD ≤ 195A, di/dt ≤ 841A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. 

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100000<br>VGS<br>TOP           15V ≤60µs PULSE WIDTH<br>10V<br>8.0V Tj = 25°C<br>10000 4.5V<br>3.5V<br>3.0V<br>2.7V<br>1000 BOTTOM 2.5V<br>100<br>o F<br>es ee A<br>10<br>S 2.5V e<br>1 a<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 1.   Typical Output Characteristics<br>10000<br>1000<br>r e ee eee<br>S T = 175°C S<br>100 J  TJ = 25°C<br>10<br>See =a 6 os<br>1 e y sy<br>VDS = 25V<br>≤60µs PULSE WIDTH<br>0.1 | f iy [y] Aa! y<br>1 2 3 4 5<br>VGS, Gate-to-Source Voltage (V)<br>ID, Drain-to-Source Current (A)<br>ID, Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 3.** Typical Transfer Characteristics 

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100000<br>VGS   = 0V,       f = 1 MHZ<br>— CCiss    = C = Cgs + Cgd,  C ds SHORTED<br>rss   gd<br>C = C + C<br>oss   ds  gd<br>C<br>iss e l<br>10000<br>C<br>oss<br>Paa ee<br>Crss<br>1000 — SS Hil<br>a<br>P H<br>rTa ee ee ee<br>100 ee |<br>1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>C, Capacitance (pF)<br>**----- End of picture text -----**<br>


**Fig 5.** Typical Capacitance vs. Drain-to-Source Voltage 

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100000<br>VGS<br>TOP           15V ≤60µs PULSE WIDTH<br>10V Tj = 175°C<br>8.0V<br>4.5V<br>10000 3.5V<br>3.0V<br>2.7V<br>BOTTOM 2.5V<br>1000<br>P H<br>100 | | ge<br>Fe 2.5V |<br>10 SSRlll<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 2.   Typical Output Characteristics<br>2.0<br>ID = 195A<br>VGS = 10V W<br>1.5 LL<br>1.0 ELLALZ<br>cd<br>0.5 PEE EL LE LE<br>-60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Junction Temperature (°C)<br>Fig 4.   Normalized On-Resistance vs. Temperature<br>5.0<br>4.5 ID= 185A VDS= 32V N\A<br>VDS= 20V<br>4.0<br>a<br>3.5 = =" 4 0<br>3.0 T A<br>2.5<br>2.0<br>o e<br>T LE<br>1.51.00.50.0 YPfP yi  | i || | || | ftct | ff<br>0 20 40 60 80 100 120 140<br> QG,  Total Gate Charge (nC)<br>RDS(on) , Drain-to-Source On Resistance                        (Normalized)<br>VGS, Gate-to-Source Voltage (V)<br>ID, Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 4.** Normalized On-Resistance vs. Temperature 

**Fig 6.** Typical Gate Charge vs. Gate-to-Source Voltage 

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10000<br>1000<br>TJ = 175°C<br>100<br>TJ = 25°C<br>10<br>JS =<br>VGS = 0V<br>1.0<br>0.0 0.5 1.0 1.5 2.0 2.5<br>VSD, Source-to-Drain Voltage (V)<br>Fig 7.   Typical Source-Drain Diode<br>Forward Voltage<br>ISD, Reverse Drain Current (A)<br>**----- End of picture text -----**<br>


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350<br>Limited By Package<br>300<br>ipa<br>250<br>200 S4aN a<br>TN T<br>150<br>100<br>+t 41\—<br>e w<br>50<br>0 LLL<br>25 50 75 100 125 150 175<br> TC , Case Temperature (°C)<br>Fig 9.   Maximum Drain Current vs.<br>Case Temperature<br>2.5<br>2.0 L LL EL<br>1.5 L EE<br>1.0 LEY<br>0.5<br>0.0 LLaeL EL<br>0 5 10 15 20 25 30 35 40 45<br>VDS, Drain-to-Source Voltage (V)<br>Energy (µJ)<br>ID,  Drain Current (A)<br>**----- End of picture text -----**<br>


**Fig 11.** Typical COSS Stored Energy 

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10000<br>OPERATION IN THIS AREA<br>LIMITED BY R DS(on)<br>1000<br>10 0µsec<br>100 1 msec<br>LIMITED BY PACKAGE<br>10 10 mse c<br>D C<br>1 T c = 25°C<br>S aaeemmai iiii M<br>Tj = 175°C s si<br>Single Pulse<br>0.1<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 8.   Maximum Safe Operating Area<br>50<br>Id = 5mA<br>o l<br>48<br>LL Ler<br>46<br>E DA<br>ne<br>44<br>42 A LLELELLEL<br>4<br>40 MELEE ELLE<br>-60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Temperature ( °C )<br>Fig 10.   Drain-to-Source Breakdown Voltage<br>1000<br>ID<br>TOP         36.5A<br>ELLE<br>800 61A<br>BOTTOM 195A<br>ALLEL<br>600<br>\<br>400<br>200<br>NTB EELSS.N<br>0<br>25 50 75 100 125 150 175<br>Starting TJ , Junction Temperature (°C)<br>EAS , Single Pulse Avalanche Energy (mJ)<br>ID,  Drain-to-Source Current (A)<br>V(BR)DSS, Drain-to-Source Breakdown Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 10.** Drain-to-Source Breakdown Voltage 

**Fig 12.** Maximum Avalanche Energy vs. DrainCurrent 

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TOR Rectifier<br>1<br>P — D = 0.50 ETT<br>THI HI<br>0.1 e 0.20 el<br>0.10<br>0.01 S A 0.010.020.05 TE=, LF | τJ τ coe Jτ1τ1 R1 R1 τ2 τR22 R2 Rτ33 R τ3 3 τR4τ4R4 4 τCτ Ri (°C/W)   0.02725     0.0000250.08804     0.0000770.20964     0.001656 τi (sec)<br>Ci= τi/Ri 0.11529     0.008408<br>P| TEE Ci i/Ri |<br>rT dL Uw | SINGLE PULSE | ty ry Notes: a ee ee<br>( THERMAL RESPONSE ) 1. Duty Factor D = t1/t2<br>0.001 |PAVLThi ih HE TPLEU 2. Peak Tj = P dm x Zthjc + Tc ECEll<br>1E-006 1E-005 0.0001 0.001 0.01 0.1<br>t1 , Rectangular Pulse Duration (sec)<br>Fig 13.   Maximum Effective Transient Thermal Impedance, Junction-to-Case<br>1000<br>P e S r<br>Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche<br>SS H PE TT<br>ee ee Se ee eee eee pulsewidth, tav, assuming ∆Tj = 150°C and  LU<br>Tstart =25°C (Single Pulse)<br>pa te I<br>100 m a 0.01 a |<br>0.05<br>Poo YS TT<br>0.10<br>ee e Se<br>10<br>| Allowed avalanche Current vs avalanche  a a ee<br>pulsewidth, tav, assuming ∆Τ j = 25°C and  SS<br>Tstart = 150°C.<br>1 aP eEE ee<br>1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01<br>tav (sec)<br>Fig 14.   Typical Avalanche Current vs.Pulsewidth<br>250 Notes on Repetitive Avalanche Curves , Figures 14, 15:<br>TOP          Single Pulse                 (For further info, see AN-1005 at www.irf.com)<br>BOTTOM   1.0% Duty Cycle 1. Avalanche failures assumption:<br>200 ID = 195A Purely a thermal phenomenon and failure occurs at a temperature far in<br>excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type.<br>2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded.<br>NVGs 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.<br>150 R RNGRERREEEE 4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse.<br>5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase<br>during avalanche).<br>100 N NN U 6. Iav = Allowable avalanche current.<br>7. ∆T = Allowable rise in junction temperature, not to exceed∆T = Allowable rise in junction temperature, not to exceedT = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as<br>25°C in Figure 14, 15).<br>50 L ANNE tav = Average time in avalanche.<br>D = Duty cycle in avalanche =  tav ·f<br>ZthJC(D, tav) = Transient thermal resistance, see Figures 13)<br>E LLEANSEEASA<br>0<br>PD (ave) = 1/2 ( 1.3·BV·Iav) = . T/ ZthJC<br>25 50 75 100 125 150 175 Iav = 2 A T/ [1.3·BV·Zth]<br>Starting TJ , Junction Temperature (°C) EAS (AR) = PD (ave)·tav<br>EAR , Avalanche Energy (mJ)<br>Thermal Response ( Z thJC ) °C/W<br>Avalanche Current (A)<br>**----- End of picture text -----**<br>


- Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type. 

2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded. 

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 

4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse. 

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 

7. ∆T = Allowable rise in junction temperature, not to exceed∆T = Allowable rise in junction temperature, not to exceedT = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as 25°C in Figure 14, 15). 

**Fig 15.** Maximum Avalanche Energy vs. Temperature 

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3.0<br>P EPE<br>2.5<br>2.0<br>P ERSE EEE<br>C SS CER<br>1.5 P t} tT | AN ee<br>CRT<br>ID = 250µA<br>1.0<br>ID = 1.0mA<br>ID = 1.0A<br>EE K<br>0.5<br>pt t TM<br>0.0<br>PEPE EEE EEE<br>-75 -50 -25 0 25 50 75 100 125 150 175<br>TJ , Temperature ( °C )<br>Fig 16.   Threshold Voltage vs. Temperature<br>14<br>IF = 117A<br>12 V R = 34V<br>TJ = 25°C<br>10<br>TJ = 125°C TY<br>8<br>ee<br>6<br>4<br>a re<br>a<br>2<br>0<br>| | | | ft<br>0 100 200 300 400 500<br>diF /dt (A/µs)<br>VGS(th), Gate threshold Voltage (V)<br>IRRM (A)<br>**----- End of picture text -----**<br>


**Fig 16.** Threshold Voltage vs. Temperature 

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14<br>IF = 78A<br>12 V R = 34V TT<br>TJ = 25°C<br>10<br>TJ = 125°C<br>ee<br>LT<br>8<br>6 | | ly |<br>4<br>T AT<br>2<br>Yt| |<br>0 | | |tf<br>0 100 200 300 400 500<br>diF /dt (A/µs)<br>Fig. 17 - Typical Recovery Current vs. di;/dt<br>400<br>IF = 78A<br>VR = 34V<br>300 TJ = 25°C<br>TJ = 125°C =<br>ee<br>200<br>lal |<br>100<br>J |<br>0 E4nnn<br>0 100 200 300 400 500<br>diF /dt (A/µs)<br>IRRM (A)<br>QRR (A)<br>**----- End of picture text -----**<br>


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400<br>IF = 117A<br>VR = 34V<br>300 TJ = 25°C aap<br>TJ = 125°C<br>ee e<br>200<br>EP 4nn<br>100<br>Eannn<br>0<br>0 100 200 300 400 500<br>diF /dt (A/µs)<br>QRR (A)<br>**----- End of picture text -----**<br>


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Driver Gate Drive<br>P.W.<br>D.U.T + {+ P.W. Period ——— — D = —— Period<br>) [©)]    •  CircuitLow  LayoutStray ConsiderationsInduct | t V t GS=10<br> •<br>- •   Low Leakage Inductance @ D.U.T. ISD Waveform<br>+<br>Reverse<br>Recovery Body Diode Forward<br>oi - [1] Current Transformer - ® + Current r Current di/dt AN<br>® D.U.T. VDS Waveform Diode Recoverydv/dt ‘<br>00 a VDD<br>•   Re-Applied<br>•   Driver same type as D.U.T. + Voltage Body Diode  Forward Drop<br>Re ( 4 •   dv/dt controlled by Rg Vpp - =<br>•<br>D.U.T. - Device Under Test SOO |<br>Ripple  ≤ 5% ISD<br>Isp controlled by Duty Factor "D" @| t<br>* Vg = 5V for Logic Level Devices<br>Fig 21.  Peak Diode Recovery dv/dt Test Circuit for N-Channel<br>HEXFET ® Power MOSFETs<br>V(BR)DSS<br>15V —_ tp -><br>VDS L DRIVER<br>RG D.U.T +<br>- [V][DD]<br>IAS A<br>¢ 20VVGS dt<br>tp 0.01Ω IAS<br>**----- End of picture text -----**<br>


**Fig 22a.** Unclamped Inductive Test Circuit 

## **Fig 22b.** Unclamped Inductive Waveforms 

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+<br>-<br>≤ 1  ys<br>≤ 0.1 %<br>**----- End of picture text -----**<br>


## **Fig 23a.** Switching Time Test Circuit 

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Current Regulator<br>Same Type as D.U.T.<br>50KΩ<br>12V .2µF .3µF ||<br>+<br>D.U.T. -VDS<br>VGS<br>3mA<br>WAV IG ID<br>Current Sampling Resistors<br>**----- End of picture text -----**<br>


**Fig 24a.** Gate Charge Test Circuit 

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VDS<br>90%<br>\<br>10% /\<br>VGS |«le ys| |<br>td(on) tr td(off) tf<br>**----- End of picture text -----**<br>


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Fig 23b.   Switching Time Waveforms<br>**----- End of picture text -----**<br>


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**Fig 24b.** Gate Charge Waveform 

www.irf.com 

7 

TO-247AC package is not recommended for Surface Mount Application. 

Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. 

**IR WORLD HEADQUARTERS:** 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information **.** 04/2009 

www.irf.com 

8 

## **IMPORTANT NOTICE** 

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) . 

With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. 

In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. 

The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. 

For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office ( **www.infineon.com** ). 

## **WARNINGS** 

Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. 

Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. 



## Links

- [View this product on Novapart](https://novapart.co/products/IRLP3034PBF/power-mosfet-n-channel-40-v-327-a-1700-ohm-to)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/infineon/irlp3034pbf/mosfet-n-ch-40v-327a-to-247ac/dp/1758306)
---

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