# Power MOSFET, N Channel, 100 V, 180 A, 4700 µohm, TO-262, Through Hole

![Product image](https://novapart.co/image/farnell:2580031/)

**URL**: https://novapart.co/products/IRFSL4010PBF/power-mosfet-n-channel-100-v-180-a-4700-ohm-to-262
**SKU**: IRFSL4010PBF
**Manufacturer**: INFINEON
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.3700
**Stock**: 10+

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:180A; Drain Source Voltage Vds:100V; On Resistance Rds(on):0.0039ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V;

## Specifications

| Parameter | Value |
|---|---|
| Msl | - |
| Svhc | No SVHC (21-Jan-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | HEXFET |
| Qualification | - |
| Power Dissipation | 375W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-262 |
| Drain Source Voltage Vds | 100V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 180A |
| Drain Source On State Resistance | 4700µohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2580031/)

96186A 

## IRFS4010PbF IRFSL4010PbF 

HEXFET ® Power MOSFET 

## **Applications** 

High Efficiency Synchronous Rectification in SMPS Uninterruptible Power Supply High Speed Power Switching Hard Switched and High Frequency Circuits 

> D **VDSS 100V RDS(on)   typ. 3.9m** 

> G **max. 4.7m** Q S **ID** ~~ps~~ **180A** 

## **Benefits** 

Improved  Gate, Avalanche and Dynamic  dV/dt Ruggedness 

> ; Fully Characterized Capacitance and Avalanche SOA 

Enhanced body diode dV/dt and dI/dt Capability Lead-Free 

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D D<br>S<br>S D<br>G G<br>D [2] Pak TO-262<br>IRFS4010PbF IRFSL4010PbF<br>**----- End of picture text -----**<br>


|**G**|**D**|**S**|
|---|---|---|
|Gate|Drain|Source|



## **Absolute Maximum Ratings** 

|**Symbol**<br>**Parameter**<br>**Units**<br>ID @ TC = 25°C<br>Continuous Drain Current,VGS@ 10V<br>ID@ TC= 100°C<br>Continuous Drain Current,VGS@ 10V<br>A<br>IDM<br>Pulsed Drain Current<br>PD @TC = 25°C<br>Maximum Power Dissipation<br>W<br>Linear DeratingFactor<br>W/°C<br>VGS<br>Gate-to-Source Voltage<br>V<br>dv/dt<br>Peak Diode Recovery<br>V/ns<br>TJ<br>Operating Junction and<br>**Max.**<br>180<br>127<br>720<br>375<br>31<br>-55  to + 175<br>± 20<br>2.5<br>~~ooW~~<br>~~ooW~~<br>~~ee~~<br>~~ee~~<br>~~ST,~~<br>~~x,~~<br>~~as~~<br>~~{XXX~~<br>~~as~~<br>~~{XXX~~<br>~~FS~~<br>~~{xX~~|
|---|
|TSTG<br>Storage Temperature Range<br>°C|
|Soldering Temperature, for 10 seconds<br>300|
|(1.6mm from case)|
|**Avalanche Characteristics**|
|EAS(Thermallylimited)<br>Single Pulse Avalanche Energy<br>mJ<br>IAR<br>Avalanche Current<br>A<br>EAR<br>Repetitive Avalanche Energy<br>mJ<br>318<br>See Fig. 14, 15, 22a, 22b,<br>~~a~~<br>~~es~~<br>~~ao~~<br>~~eee~~|
|**Thermal Resistance**|
|**Symbol**<br>**Parameter**<br>**Typ.**<br>**Max.**<br>**Units**<br>RθJC<br>Junction-to-Case<br>–––<br>0.40<br>RθJA<br>Junction-to-Ambient(PCB Mount)<br>–––<br>40<br>°C/W<br>~~a~~<br>~~a~~|



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**Static @ TJ = 25°C (unless otherwise specified)** 

|**Symbol**|**Parameter**<br>**Min. Typ. Max. Units**<br>**Conditions**|
|---|---|
|V(BR)DSS<br>ΔV(BR)DSS/ΔTJ|Drain-to-Source Breakdown Voltage<br>100<br>–––<br>–––<br>V<br>Breakdown Voltage Temp. Coefficient<br>–––<br>0.10<br>–––<br>V/°C<br>VGS= 0V, ID= 250μA<br>Reference to 25°C, ID= 5mA<br>~~GO~~<br>~~QO fO~~<br>~~GG~~<br>~~QO~~|
|RDS(on)|Static Drain-to-Source On-Resistance<br>–––<br>3.9<br>4.7<br>mΩ<br>VGS= 10V, ID= 106A<br>~~pf~~|
|VGS(th)<br>IDSS<br>IGSS<br>RG(int)|Gate Threshold Voltage<br>2.0<br>–––<br>4.0<br>V<br>Drain-to-Source Leakage Current<br>–––<br>–––<br>20<br>–––<br>–––<br>250<br>Gate-to-Source Forward Leakage<br>–––<br>–––<br>100<br>Gate-to-Source Reverse Leakage<br>–––<br>–––<br>-100<br>Internal Gate Resistance<br>–––<br>2.0<br>–––<br>Ω<br>VGS= 20V<br>VGS= -20V<br>VDS= VGS, ID= 250μA<br>VDS= 100V, VGS= 0V<br>VDS= 100V, VGS= 0V, TJ= 125°C<br>μA<br>nA<br>~~GG~~<br>~~QO~~<br>~~ee~~<br>~~elee~~<br>~~||~~<br>~~———————~~<br>~~a~~<br>~~a~~<br>~~GG~~<br>~~QO~~|
|**Dynamic @ TJ = 25°C (unless otherwise specified)**||
|**Symbol**|**Parameter**<br>**Min. Typ. Max. Units**<br>**Conditions**|
|gfs<br>Qg|Forward Transconductance<br>189<br>–––<br>–––<br>S<br>Total Gate Charge<br>–––<br>143<br>215<br>VDS= 25V, ID= 106A<br>ID= 106A<br>~~GD~~<br>~~(GO (OO~~<br>~~a~~|
|Qgs<br>Qgd|Gate-to-Source Charge<br>–––<br>38<br>–––<br>Gate-to-Drain("Miller")Charge<br>–––<br>50<br>–––<br>VDS= 50V<br>VGS= 10V<br>nC<br>~~a~~<br>~~a~~<br>@|
|Qsync|Total Gate Charge Sync. (Qg- Qgd)<br>–––<br>93<br>–––<br>ID= 106A, VDS=0V, VGS= 10V<br>~~ee~~|
|td(on)|Turn-On DelayTime<br>–––<br>21<br>–––<br>VDD= 65V<br>~~a~~|
|tr<br>td(off)|Rise Time<br>–––<br>86<br>–––<br>Turn-Off DelayTime<br>–––<br>100<br>–––<br>ID= 106A<br>RG= 2.7Ω<br>ns<br>~~a~~<br>~~a~~|
|tf|Fall Time<br>–––<br>77<br>–––<br>VGS= 10V<br>~~a~~<br>®|
|Ciss|Input Capacitance<br>–––<br>9575<br>–––<br>VGS= 0V<br>~~a~~|
|Coss|Output Capacitance<br>–––<br>660<br>–––<br>VDS= 50V<br>~~a~~|
|Crss<br>Cosseff. (ER)<br>Cosseff. (TR)|Reverse Transfer Capacitance<br>–––<br>270<br>–––<br>Effective Output Capacitance(EnergyRelated)<br>–––<br>757<br>–––<br>Effective Output Capacitance(Time Related)<br>–––<br>1112<br>–––<br>ƒ= 1.0MHz See Fig.5<br>VGS= 0V, VDS= 0V to 80V<br>See Fig.11<br>VGS= 0V, VDS= 0V to 80V<br>pF<br>~~a~~<br>~~**a**:~~<br>~~©®~~|
|**Diode Characteristics**||
|**Symbol**|**Parameter**<br>**Min. Typ. Max. Units**<br>**Conditions**|
|IS<br>ISM<br>VSD<br>trr<br>Qrr<br>IRRM|S<br>D<br>G<br>Continuous Source Current<br>(BodyDiode)<br>Pulsed Source Current<br>(BodyDiode)<br>Diode Forward Voltage<br>–––<br>–––<br>1.3<br>V<br>Reverse Recovery Time<br>–––<br>72<br>–––<br>TJ= 25°C<br>VR= 85V,<br>–––<br>81<br>–––<br>TJ= 125°C<br>IF= 106A<br>Reverse Recovery Charge<br>–––<br>210<br>–––<br>TJ= 25°C<br>di/dt = 100A/μs<br>–––<br>268<br>–––<br>TJ= 125°C<br>Reverse RecoveryCurrent<br>–––<br>5.3<br>–––<br>A<br>TJ= 25°C<br>MOSFET symbol<br>showing  the<br>TJ= 25°C, IS= 106A, VGS= 0V<br>integral reverse<br>p-njunction diode.<br>A<br>–––<br>–––<br>–––<br>–––<br>ns<br>nC<br>180<br>720<br>~~7~~<br>~~|~~<br>~~QO~~<br>~~GO  (~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~**|**~~<br>~~a~~<br>~~**|**~~<br>~~a~~|
|ton|Forward Turn-On Time<br>Intrinsic turn-on time is negligible(turn-on is dominated byLS+LD)<br>~~GO~~|



Notes: ® Repetitive rating;  pulse width limited by max. junction ® Coss eff. (TR) is a fixed capacitance that gives the same charging time temperature. as Coss while VDS is rising from 0 to 80% VDSS. @ Limited by TJmax, starting TJ = 25°C, L = 0.057mH © Coss eff. (ER) is a fixed capacitance that gives the same energy as RG = 25 Ω , IAS = 106A, VGS =10V. Part not recommended for use Coss while VDS is rising from 0 to 80% VDSS. above this value . 

When mounted on 1" square PCB (FR-4 or G-10 Material).  For recom mended footprint and soldering echniques refer to application note #AN-994. 

ISD ≤ 106A, di/dt ≤ 1319A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. Pulse width ≤ 400μs; duty cycle ≤ 2%. 

θ 

θ JC 

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1000<br>VGS<br>TOP           15V<br>10V<br>8.0V<br>7.0V<br>5.0V<br>4.5V<br>4.3V<br>BOTTOM 4.0V<br>100<br>4.0V ≤ 60μs PULSE WIDTH<br>10 |eatineatin Tj = 175°C<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>ID, Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


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1000 1000<br>VGS VGS<br>TOP           15V TOP           15V<br>10V 10V<br>8.0V 8.0V<br>7.0V 7.0V<br>100 5.0V 5.0V<br>4.5V 4.5V<br>4.3V 4.3V<br>BOTTOM 4.0V BOTTOM 4.0V<br>10 100<br>1<br>≤ 60μs PULSE WIDTH<br>Tj = 25°C 4.0V ≤ 60μs PULSE WIDTH<br>0.1 RT 4.0V ll 10 |eatineatin Tj = 175°C<br>0.1 1 10 100 0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)<br>Fig 1.   Typical Output Characteristics Fig 2.   Typical Output Characteristics<br>1000 2.5<br>ID = 106A<br>VGS = 10V<br>Tye 6<br>100 7 2.0<br>T = 175°C<br>= J  TTT<br>10 no [Ae] T J  = 25°C 1.5 PLETTTTTYAA<br>1 a 1.0 y<br>VDS = 50V<br>SS PLLA<br>≤ 60μs PULSE WIDTH<br>0.1 ee 0.5 2a4GReeeeeeee<br>2 3 4 5 6 7 -60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Junction Temperature (°C)<br>VGS, Gate-to-Source Voltage (V)<br>ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A)<br>RDS(on) , Drain-to-Source On Resistance                        (Normalized)<br>ID, Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 4.** Normalized On-Resistance vs. Temperature 

**Fig 3.** Typical Transfer Characteristics 

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100000<br>VGS   = 0V,       f = 1 MHZ<br>Ciss   = C gs + Cgd,  C ds SHORTED<br>C  = C<br>rss   gd<br>C = C + C<br>oss   ds  gd<br>10000 Ciss<br>on<br>PME EEE EA<br>PNET<br>C<br>oss<br>1000<br>NOI<br>ETE CC<br>Crss<br>100 PEE CETTE<br>1 10 100 1000<br>VDS, Drain-to-Source Voltage (V)<br>C, Capacitance (pF)<br>**----- End of picture text -----**<br>


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14.0<br>ID= 106A<br>12.0<br>VDS= 80V<br>VDS= 50V<br>10.0<br>W<br>8.0 4<br>PTT<br>6.0<br>TAWA TT<br>Tyr TT<br>4.0<br>2.00.0 Jit ttt td yl<br>0 25 50 75 100 125 150 175 200 225<br> QG,  Total Gate Charge (nC)<br>VGS, Gate-to-Source Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 5.** Typical Capacitance vs. Drain-to-Source Voltage 

**Fig 6.** Typical Gate Charge vs. Gate-to-Source Voltage 

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1000<br>TJ = 175°C<br>100<br>TJ = 25°C<br>10<br>V GS  = 0V<br>PPR<br>1.0<br>0.2 0.6 1.0 1.4 1.8<br>VSD, Source-to-Drain Voltage (V)<br>Fig 7.   Typical Source-Drain Diode<br>Forward Voltage<br>ISD, Reverse Drain Current (A)<br>**----- End of picture text -----**<br>


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200<br>180<br>160 Se<br>140<br>TST<br>120<br>oS<br>100<br>80 es es<br>60<br>PP iN<br>40<br>Ae<br>20<br>0 a<br>25 50 75 100 125 150 175<br> TC , Case Temperature (°C)<br>Fig 9.   Maximum Drain Current vs.<br>Case Temperature<br>4.0<br>3.5<br>/ | | tt<br>3.0<br>pj ft tf}<br>2.5<br>tj} 4 |<br>2.0<br>pf<br>1.5 a<br>1.0<br>Coe<br>0.5 a<br>0.0 ~~<br>0 20 40 60 80 100 120<br>VDS, Drain-to-Source Voltage (V)<br>ID,  Drain Current (A)<br>Energy (μJ)<br>**----- End of picture text -----**<br>


**Fig 11.** Typical COSS Stored Energy 

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10000<br>OPERATION IN THIS AREA<br>LIMITED BY RDS(on)<br>1000<br>100μsec<br>100<br>1msec<br>10<br>10msec<br>1<br>Tc = 25°C DC<br>0.1 Tj = 175°C<br>Single Pulse<br>0.01 HEH tt<br>0.1 1 10 100 1000<br>VDS, Drain-to-Source Voltage (V)<br>Fig 8.   Maximum Safe Operating Area<br>130<br>Id = 5mA<br>125<br>CTT<br>120<br>BERERRREDZ a6<br>115<br>CO<br>110<br>LEE AEEeT<br>105<br>AW<br>100<br>AL EE<br>95 PLP EE TTEET<br>-60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Temperature ( °C )<br>Fig 10.   Drain-to-Source Breakdown Voltage<br>1400<br>ID<br>1200 EEE TOP          12.5A<br> 17A<br>1000 BOTTOM  106A<br>NERD<br>800<br>ATT<br>CNC<br>600<br>ak<br>400<br>SOT<br>200<br>PENT<br>0 Se<br>25 50 75 100 125 150 175<br>Starting TJ , Junction Temperature (°C)<br>ID,  Drain-to-Source Current (A)<br>EAS , Single Pulse Avalanche Energy (mJ)<br>V(BR)DSS, Drain-to-Source Breakdown Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 12.** Maximum Avalanche Energy vs. DrainCurrent 

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Ter Rectifier<br>1<br>PEE<br>D = 0.50<br>pa ns it} tt<br>0.1<br>0.20<br>eg = cr<br>0.10<br>—— eee eo ee ee ee ee eee ee<br>0.05<br>seen ne nl<br>0.01 Per 0.010.02 Bh.. — aenllie τ J τ J R1R1 R2R2 τ C τ | Ri (0.17537      0.000343 el °C/W)     τ i (sec) a<br>a ee ee ee eee τ 1 τ 1 τ 2 τ 2 || 0.22547      0.006073 Ly<br>0.001 4| Ci=  τ i / Ri po<br>SINGLE PULSE Ci i / Ri Notes:<br>|ETT| ( THERMAL RESPONSE ) a ee ee eee 1. Duty Factor D = t1/t2 MELH<br>2. Peak Tj = P dm x Zthjc + Tc<br>0.0001 PIP ie il<br>1E-006 1E-005 0.0001 0.001 0.01 0.1<br>t1 , Rectangular Pulse Duration (sec)<br>Fig 13.   Maximum Effective Transient Thermal Impedance, Junction-to-Case<br>1000<br>Se<br>Duty Cycle = Single Pulse<br>ey ee Allowed avalanche Current vs avalanche  = meeeeei | ae emeeeit<br>100 pulsewidth, tav, assuming  Δ Tj  = 150°C and<br>0.01 Tstart =25°C (Single Pulse)<br>Se —si<br>po 0.05 CORSETS<br>10 0.10<br>CToor<br>Pf fA ff tt] HE<br>1<br>Oa<br>Allowed avalanche Current vs avalanche<br>!| pulsewidth, tav, assuming Tstart = 150°C. ΔΤ j = 25°C and  aa a aOOeeee eeee ee elee ee<br>eeeDEES ESE<br>0.1 OO 0<br>1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01<br>tav (sec)<br>Fig 14.   Typical Avalanche Current vs.Pulsewidth<br>350 Notes on Repetitive Avalanche Curves , Figures 14, 15:<br>TOP          Single Pulse                 (For further info, see AN-1005 at www.irf.com)<br>300 BOTTOM   1.0% Duty Cycle 1. Avalanche failures assumption:<br>ID = 106A Purely a thermal phenomenon and failure occurs at a temperature far in<br>excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type.<br>250 2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded.<br>3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.<br>200 INNO ~ N\ 4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse.<br>5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase<br>CIN NUELE during avalanche).<br>150<br>6. Iav = Allowable avalanche current.<br>7.  Δ T = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as<br>PL LLINGNNWN LEE<br>100 25°C in Figure 14, 15).<br>tav = Average time in avalanche.<br>50 INN NaN D = Duty cycle in avalanche =  tav ·f<br>ZthJC(D, tav) = Transient thermal resistance, see Figures 13)<br>ELL LEANNDN<br>0<br>PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) = A T/ ZthJCthJC<br>25 50 75 100 125 150 175<br>Iav =av == 2 A T/ [1.3·BV·Zth]th]]<br>Starting TJ , Junction Temperature (°C) EAS (AR) = PD (ave)·tavAS (AR) = PD (ave)·tav = PD (ave)·tavD (ave)·tav·tavav<br>EAR , Avalanche Energy (mJ)<br>Thermal Response ( Z thJC ) °C/W<br>Avalanche Current (A)<br>**----- End of picture text -----**<br>


- Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type. 

2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded. 

3. Equation below based on circuit and waveforms shown in Figures 22a, 22b. 

4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse. 

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 

7. Δ T = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as 25°C in Figure 14, 15). 

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PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) = A T/ ZthJCthJC<br>Iav =av == 2 A T/ [1.3·BV·Zth]th]]<br>EAS (AR) = PD (ave)·tavAS (AR) = PD (ave)·tav = PD (ave)·tavD (ave)·tav·tavav<br>**----- End of picture text -----**<br>


**Fig 15.** Maximum Avalanche Energy vs. Temperature 

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4.5<br>PES<br>4.0 P | PS tT tT tt<br>P wt | AE tt<br>3.5 P| ANE EN<br>-LPSSSEPRS<br>3.0 Pot ot | A EON<br>ID = 250μA TNA<br>2.5 AA INNE<br>ID = 1.0mA<br>ID = 1.0A EEERNS<br>2.0 aN<br>1.5 Pt ot | | PEEPcE rT TE TIN<br>PEEEEEEEE<br>1.0 Pp ot te TE [Tt]<br>-75 -50 -25 0 25 50 75 100 125 150 175<br>TJ , Temperature ( °C )<br>Fig 16.   Threshold Voltage vs. Temperature<br>35<br>IF = 106A<br>30 V R  = 85V Pt es<br>TJ = 25°C<br>| :<br>25<br>ele<br>TJ = 125°C ae<br>20<br>15<br>et<br>Pt |<br>10<br>5<br>AT | [TT] |<br>| | |<br>0 |<br>0 200 400 600 800 1000<br>diF /dt (A/μs)<br>VGS(th), Gate threshold Voltage (V)<br>IRR (A)<br>**----- End of picture text -----**<br>


**Fig 16.** Threshold Voltage vs. Temperature 

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35<br>IF = 70A<br>CTT<br>30 V R  = 85V ‘<br>TJ = 25°C<br>ars<br>25 “| A<br>TJ = 125°C am<br>20 Z|<br>er<br>15 Z|<br>ea<br>10 |<br>5 CATJ<br>PT<br>0<br>0 200 400 600 800 1000<br>diF /dt (A/μs)<br>Fig. 17 - Typical Recovery Current vs. di;/dt<br>1100<br>1000 I F  = 70A<br>VR = 85V |<br>900<br>TJ = 25°C<br>| |CT<br>800 T J  = 125°C a<br>700 eZ<br>600<br>500 Ste<br>400 Pet<br>300<br>ee<br>per<br>200 ae<br>100 i<br>| | |<br>0 200 400 600 800 1000<br>diF /dt (A/μs)<br>IRR (A)<br>QRR (A)<br>**----- End of picture text -----**<br>


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1100<br>IF = 106A<br>1000<br>VR = 85V<br>900 T  = 25°C<br>J<br>T  = 125°C<br>800 J<br>700 |a -EEE| [ole] LT<br>600<br>500<br>pt ae<br>400 | teta LT A<br>Pvt<br>300<br>200<br>0 200 400 600 800 1000<br>diF /dt (A/μs)<br>QRR (A)<br>**----- End of picture text -----**<br>


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Driver Gate Drive<br>P.W.<br>D.U.T + { P.W. + Period ——— — D = —— Period<br>) [©)]    •  CircuitLow  LayoutStray ConsiderationsInduct ) V t t GS=10<br> •<br>- •   Low Leakage Inductance @ D.U.T. ISD Waveform<br>+<br>Reverse<br>Recovery Body Diode Forward<br>oi - [1] Current Transformer - ® + Current r Current di/dt AN<br>® D.U.T. VDS Waveform Diode Recoverydv/dt ‘<br>00 we VDD<br>ma<br>•   Re-Applied<br>•   Driver same type as D.U.T. + Voltage Body Diode  Forward Drop<br>Re (A •   dv/dt controlled by Rg Vp p -<br>•<br>D.U.T. - Device Under Test SO O<br>Ripple  ≤ 5% ISD<br>Isp controlled by Duty Factor "D" @\ t<br>* Vg = 5V for Logic Level Devices<br>Fig 21.  Peak Diode Recovery dv/dt Test Circuit for N-Channel<br>HEXFET ® Power MOSFETs<br>V(BR)DSS<br>15V << tp -—><br>VDS L DRIVER<br>RG D.U.T +<br>- [V][DD]<br>IAS A<br>y 2V0VGS dt<br>tp 0.01 Ω IAS<br>**----- End of picture text -----**<br>


**Fig 22a.** Unclamped Inductive Test Circuit 

## **Fig 22b.** Unclamped Inductive Waveforms 

**==> picture [130 x 58] intentionally omitted <==**

**----- Start of picture text -----**<br>
+<br>-<br>≤ 1  ys<br>≤ 0.1 %<br>**----- End of picture text -----**<br>


## **Fig 23a.** Switching Time Test Circuit 

**==> picture [134 x 132] intentionally omitted <==**

**----- Start of picture text -----**<br>
Current Regulator<br>Same Type as D.U.T.<br>50K Ω<br>12V .2 μ F .3 μ F ||<br>+<br>D.U.T. -VDS<br>VGS<br>3mA<br>W IG A N ID<br>Current Sampling Resistors<br>**----- End of picture text -----**<br>


**Fig 24a.** Gate Charge Test Circuit 

**==> picture [192 x 121] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDS<br>90%<br>\<br>10% /\<br>VGS |a r e | |<br>td(on) tr td(off) tf<br>**----- End of picture text -----**<br>


**==> picture [164 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig 23b.   Switching Time Waveforms<br>**----- End of picture text -----**<br>


**==> picture [162 x 131] intentionally omitted <==**

**----- Start of picture text -----**<br>
Id<br>Vds<br>fl Vgs<br>i<br>Vgs(th)<br>‘e g pl a p l e w i e » !<br>Qgs1 Qgs2 Qgd Qgodr<br>**----- End of picture text -----**<br>


**Fig 24b.** Gate Charge Waveform 

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## TO-262 Package Outline 

Dimensions are shown in millimeters (inches) 

## TO-262 Part Marking Information 

**==> picture [375 x 90] intentionally omitted <==**

**----- Start of picture text -----**<br>
EXAMPLE: THIS IS AN IRL3103L<br>LOT CODE 1789 PART NUMBER<br>ASSEMBLED ON WW 19, 1997 INTERNATIONAL c S<br>RECTIFIER<br>IN THE ASSEMBLY LINE "C" IRL3103L<br>LOGO<br>IeaR 719C<br>DATE CODE<br>17 89<br>YEAR 7 =  1997<br>No te : "P” in assembly line posi t ion ASSEMBLY<br>WEEK 19<br>indica t es "Lead — F ree” LOT CODE<br>LINE C<br>**----- End of picture text -----**<br>


## OR 

**==> picture [251 x 101] intentionally omitted <==**

**----- Start of picture text -----**<br>
PART NUMBER<br>INTERNATIONAL c S<br>RECTIFIER<br>IRL3103L<br>LOGO<br>TEAR P7i9 A<br>DATE CODE<br>17 89<br>P =  DESIGNATES LEAD-FREE<br>ASSEMBLY<br>LOT CODE PRODUCT (OPTIONAL)<br>YEAR 7 =  1997<br>WEEK 19<br>A =  ASSEMBLY SITE CODE<br>**----- End of picture text -----**<br>


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**==> picture [365 x 231] intentionally omitted <==**

**----- Start of picture text -----**<br>
THIS IS AN IRF530S WITH<br>PART NUMBER<br>LOT CODE 8024 INTERNATIONAL<br>(a<br>ASSEMBLED ON WW 02, 2000 RECTIFIER F530S<br>IN THE ASSEMBLY LINE "L" LOGO IeaR 0021<br>DATE CODE<br>80 24<br>YEAR 0 =  2000<br>ASSEMBLY<br>assembly line position LOT CODE T ent , WEEK 02<br>t es "Lead — F ree” U u LINE L<br>OR<br>PART NUMBER<br>INTERNATIONAL<br>C Y<br>RECTIFIER F530S<br>LOGO I¢€aR P002 4 DATE CODE<br>P =  DESIGNATES LEAD - FREE<br>80 24<br>PRODUCT (OPTIONAL)<br>ASSEMBLY J U L<br>LOT CODE ranay YEAR 0 =  2000<br>U U WEEK 02<br>A =  ASSEMBLY SITE CODE<br>**----- End of picture text -----**<br>


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Dimensions are shown in millimeters (inches) 

**==> picture [404 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
TRR<br>1.60 (.063)<br>1.50 (.059)<br>1.60 (.063)<br>4.10 (.161)<br>1.50 (.059)<br>3.90 (.153) 0.368 (.0145)<br>!0 0°0Hd 0| i Te 0.342 (.0135)<br>24_____ OS OO 4/8 -<br>FEED DIRECTION 1.85 (.073) 11.60 (.457)<br>1.65 (.065) 11.40 (.449) 24.30 (.957)<br>15.42 (.609)<br>23.90 (.941)<br>15.22 (.601)<br>TRL<br>| x<br>1.75 (.069)<br>10.90 (.429) 1.25 (.049)<br>10.70 (.421) 4.72 (.136)<br>16.10 (.634) 4.52 (.178)<br>15.90 (.626)<br>**----- End of picture text -----**<br>


FEED DIRECTION 

**==> picture [395 x 198] intentionally omitted <==**

**----- Start of picture text -----**<br>
13.50 (.532) 27.40 (1.079)<br>12.80 (.504) 23.90 (.941) ls<br>4<br>330.00(14.173) \ 60.00 (2.362)      MIN.<br>  MAX.<br>i) x<br>30.40 (1.197)<br>NOTES :       MAX.<br>1.   COMFORMS TO EIA-418.<br>26.40 (1.039) 4<br>2.   CONTROLLING DIMENSION: MILLIMETER. 24.40 (.961)<br>3.   DIMENSION MEASURED @ HUB.<br>3<br>**----- End of picture text -----**<br>


4.   INCLUDES FLANGE DISTORTION @ OUTER EDGE. 

Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. 

**IR WORLD HEADQUARTERS:** 101N.Sepulveda blvd, El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information **.** 07/2011 

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10 

## **IMPORTANT NOTICE** 

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) . 

With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. 

In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. 

The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. 

For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office ( **www.infineon.com** ). 

## **WARNINGS** 

Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. 

Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. 



## Links

- [View this product on Novapart](https://novapart.co/products/IRFSL4010PBF/power-mosfet-n-channel-100-v-180-a-4700-ohm-to-262)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/infineon/irfsl4010pbf/mosfet-n-ch-100v-180a-to-262-3/dp/2580031)
---

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