# Power MOSFET, N Channel, 100 V, 61 A, 0.0139 ohm, TO-263 (D2PAK), Surface Mount

![Product image](https://novapart.co/image/farnell:3514438/)

**URL**: https://novapart.co/products/IRFS4510TRLPBF/power-mosfet-n-channel-100-v-61-a-00139-ohm-to-263
**SKU**: IRFS4510TRLPBF
**Manufacturer**: INFINEON
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.0900
**Stock**: 1000+
**Lead Time**: 2 days (indicative)

## Description

Available until stocks are exhausted Alternative available

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (21-Jan-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | HexFET |
| Qualification | - |
| Power Dissipation | 140W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-263 (D2PAK) |
| Drain Source Voltage Vds | 100V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 61A |
| Drain Source On State Resistance | 0.0139ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3514438/)

## IRFS4510PbF IRFSL4510PbF 

HEXFET Power MOSFET 

## **Applications** 

High Efficiency Synchronous Rectification in SMPS Uninterruptible Power Supply High Speed Power Switching Hard Switched and High Frequency Circuits 

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|||||
|---|---|---|---|
|D|VDSS|100V|
|RDS(on)   typ.|11.3m|Ω|
|G|max.|13.9m|Ω|
|S|ID (Silicon Limited)|61A|

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## **Benefits** 

Improved  Gate, Avalanche and Dynamic  dV/dt Ruggedness 

> : Fully Characterized Capacitance and Avalanche SOA 

Enhanced body diode dV/dt and dI/dt Capability Lead-Free 

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D<br>D<br>D S D S<br>G G<br>D [2] Pak TO-262<br>IRFS4510PbF IRFSL4510PbF<br>**----- End of picture text -----**<br>


**G D S** Gate Drain Source 

**Absolute Maximum Ratings** 

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||||||||||
|---|---|---|---|---|---|---|---|---|
|Symbol|a|Parameter|Max.|Units|
|ID @ TC = 25°C|es|Continuous Drain Current, VGS @ 10V (Silicon Limited)|61|
|ID @ TC = 100°C|es|Continuous Drain Current, VGS @ 10V (Silicon Limited)|43|A|
|IDM|Pulsed Drain Current|250|
|es|
|PD @TC = 25°C|nS|Maximum Power Dissipation|140|W|
|a|Linear Derating Factor|(O|0.95|W/°C|
|VGS|nD|Gate-to-Source Voltage|± 20|V|
|dv/dt|Peak Diode Recovery|3.2|V/ns|
|TJ|Operating Junction and|-55  to + 175|°C|
|TSTG|Storage Temperature Range|
|Soldering Temperature, for 10 seconds|300|
|(1.6mm from case)|
|a|Mounting torque, 6-32 or M3 screw|(|10lb|in (1.1N|m)|
|Avalanche|Characteristics|
|EAS (Thermally limited)|es|Single Pulse Avalanche Energy|130|mJ|
|IAR|Avalanche Current|See Fig. 14, 15, 22a, 22b,|A|
|EAR|Repetitive Avalanche Energy|mJ|
|ee|(|Fs|
|Thermal Resistance|
|a|Parameter|Typ.|Max.|Units|
|R|θ|JC|Junction-to-Case|–––|1.05|°C/W|
|R|θ|JA|SS[8|Junction-to-Ambient|Se|–––|a|40|

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4/10/12 

**Static @ TJ = 25°C (unless otherwise specified)** 

|**Symbol**<br>V(BR)DSS|**Parameter**<br>**Min. Typ. Max. Units**<br>Drain-to-Source Breakdown Voltage<br>100<br>–––<br>–––<br>V<br>**Conditions**<br>VGS= 0V,ID= 250μA<br>~~es~~<br>~~ee~~<br>~~es es~~<br>~~pe~~|**Parameter**<br>**Min. Typ. Max. Units**<br>Drain-to-Source Breakdown Voltage<br>100<br>–––<br>–––<br>V<br>**Conditions**<br>VGS= 0V,ID= 250μA<br>~~es~~<br>~~ee~~<br>~~es es~~<br>~~pe~~|
|---|---|---|
|ΔV(BR)DSS/ΔTJ|Breakdown Voltage Temp. Coefficient<br>–––<br>0.11<br>–––<br>V/°C<br>Reference to 25°C,ID= 5mA<br>~~Pe~~||
|RDS(on)<br>VGS(th)<br>IDSS<br>IGSS<br>RG|Static Drain-to-Source On-Resistance<br>–––<br>11.3<br>13.9<br>mΩ<br>Gate Threshold Voltage<br>2.0<br>–––<br>4.0<br>V<br>Drain-to-Source Leakage Current<br>–––<br>–––<br>20<br>μA<br>–––<br>–––<br>250<br>Gate-to-Source Forward Leakage<br>–––<br>–––<br>100<br>nA<br>Gate-to-Source Reverse Leakage<br>–––<br>–––<br>-100<br>Internal Gate Resistance<br>–––<br>0.6<br>–––<br>Ω<br>VGS= 10V,ID= 37A<br>VDS= VGS,ID= 100μA<br>VDS= 100V,VGS= 0V<br>VDS= 80V,VGS= 0V,TJ= 125°C<br>VGS= 20V<br>VGS= -20V<br>~~pe~~<br>~~ss~~<br>~~QO~~<br>~~| _~~<br>~~||~~<br>~~rr~~<br>~~|tT~~<br>~~ss~~<br>~~QO~~||
|**Dynamic @ TJ = 25°C(unless otherwise specified)**|||
|**Symbol**<br>gfs|**Parameter**<br>**Min. Typ. Max. Units**<br>Forward Transconductance<br>100<br>–––<br>–––<br>S<br>**Conditions**<br>VDS= 25V,ID= 37A<br>~~es~~<br>~~Pe~~<br>~~es ee Qs~~<br>~~QOD~~||
|Qg|Total Gate Charge<br>–––<br>58<br>87<br>nC<br>ID= 37A<br>~~a~~||
|Qgs|Gate-to-Source Charge<br>–––<br>14<br>–––<br>VDS=50V<br>~~es~~||
|Qgd|Gate-to-Drain("Miller")Charge<br>–––<br>18<br>VGS= 10V<br>~~a@~~|~~@~~|
|Qsync|Total Gate Charge Sync.(Qg- Qgd)<br>–––<br>40<br>–––<br>ID= 37A,VDS=0V,VGS= 10V<br>~~a~~<br>@||
|td(on)|Turn-On DelayTime<br>–––<br>13<br>–––<br>ns<br>VDD= 65V<br>~~a~~||
|tr|Rise Time<br>–––<br>32<br>–––<br>ID= 37A<br>~~a~~||
|td(off)|Turn-Off DelayTime<br>–––<br>28<br>–––<br>RG=2.7Ω<br>~~a~~||
|tf|Fall Time<br>–––<br>28<br>–––<br>VGS= 10V<br>~~a~~<br>@||
|Ciss|Input Capacitance<br>–––<br>3180<br>–––<br>pF<br>VGS= 0V<br>~~a~~||
|Coss|Output Capacitance<br>–––<br>220<br>–––<br>VDS= 50V<br>~~a~~||
|Crss|Reverse Transfer Capacitance<br>–––<br>120<br>–––<br>ƒ= 1.0MHz,See Fig.5<br>~~a~~||
|Cosseff.(ER)|Effective Output Capacitance(EnergyRelated)<br>––<br>260<br>–––<br>VGS= 0V,VDS= 0V to 80V<br>,See Fig.11<br>~~>~~<br>®||
|Cosseff.(TR)|Effective Output Capacitance(Time Related)<br>–––<br>325<br>–––<br>VGS= 0V,VDS= 0V to 80V<br>~~a@~~|~~@~~|
|**Diode Characteristics**|||
|**Symbol**<br>IS<br>ISM<br>VSD|S<br>D<br>G<br>**Parameter**<br>**Min. Typ. Max. Units**<br>Continuous Source Current<br>–––<br>–––<br>61<br>A<br>(Body Diode)<br>Pulsed Source Current<br>–––<br>–––<br>250<br>A<br>(Body Diode)<br>Diode Forward Voltage<br>–––<br>–––<br>1.3<br>V<br>TJ= 25°C,IS= 37A,VGS= 0V<br>integral reverse<br>p-n junction diode.<br>MOSFET symbol<br>showing  the<br>**Conditions**<br>~~a~~<br>~~es~~<br>~~ee~~<br>~~pe~~||
|trr<br>Qrr<br>IRRM|Reverse Recovery Time<br>–––<br>54<br>81<br>ns<br>TJ= 25°C<br>VR= 85V,<br>–––<br>60<br>90<br>TJ= 125°C<br>IF= 37A<br>Reverse Recovery Charge<br>–––<br>95<br>140<br>nC<br>TJ= 25°C<br>di/dt = 100A/μs<br>–––<br>130<br>195<br>TJ= 125°C<br>Reverse RecoveryCurrent<br>–––<br>3.3<br>–––<br>A<br>TJ= 25°C<br>~~eo~~<br>~~||~~<br>~~ee~~<br>~~||~~<br>~~ee~~||
|ton|Forward Turn-On Time<br>Intrinsic turn-on time is negligible(turn-on is dominated byLS+LD)<br>~~a~~||



Repetitive rating;  pulse width limited by max. junction Cossoss eff. (TR) is a fixed capacitance that gives the same charging time fe) temperature. as Coss while VDS is rising from 0 to 80% VDSS. 

Cossoss eff. (TR) is a fixed capacitance that gives the same charging time 

@ Limited by TJmax, starting TJ = 25°C, L = 0.192mH © Coss eff. (ER) is a fixed capacitance that gives the same energy as RG = 25 Ω , IAS = 37A, VGS =10V. Part not recommended for use Coss while VDS is rising from 0 to 80% VDSS. above this value. 

@R θ is measured at Ty approximately 90°C. When mounted on 1" square PCB (FR-4 or G-10 Material).  For recom mended footprint and soldering techniques refer to application note #AN-994. 

ISD ≤ 37A, di/dt ≤ 1550A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. Pulse width ≤ 400μs; duty cycle ≤ 2%. 

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1000<br>VGS<br>TOP           15V<br>                       10V<br>6.0V<br>100 5.0V<br>Sara ArT 4.8V<br>aaaete 4.5V<br>a  26o.                       4.3V<br>ea 4a i ee BOTTOM 4.0V<br>10 er nee<br>Re ae al<br>1 ce ll<br>4.0V<br>≤  60μs PULSE WIDTH<br>Tj = 25°C<br>0.1 PEETe| val|<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 1.   Typical Output Characteristics<br>1000<br>ee ee ee ee<br>100<br>TJ = 175°C<br>— 4 ——<br>a ee) 2 ee ee eee<br>10<br>T = 25°C<br>J<br>1<br>SoS VDS = 50V<br>a Gy, ≤  60μs PULSE WIDTH<br>0.1<br>iw.<br>2.0 3.0 4.0 5.0 6.0 7.0<br>VGS, Gate-to-Source Voltage (V)<br>Fig 3.   Typical Transfer Characteristics<br>100000<br>VGS   = 0V,       f = 1 MHZ<br>Ciss   = Cgs + Cgd,  Cds SHORTED<br>Crss   = Cgd<br>10000 C oss   = C ds  + C gd<br>|EEE<br>Ciss<br>rs a<br>1000<br>I<br>Coss<br>Crss<br>Pe SEE]<br>100<br>eee all<br>a ee ee ee ee<br>10 es<br>1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>) (Α<br>ID, Drain-to-Source Current<br>C, Capacitance (pF)<br>ID, Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 5.** Typical Capacitance vs. Drain-to-Source Voltage 

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1000<br>VGS<br>TOP           15V<br>                       10V<br>6.0V<br>5.0V<br>4.8V pee |<br>100 4.5V at ———<br>                      4.3V Aett<br>BOTTOM 4.0V ,, ae call<br>HyEE rE HH<br>10 Oei 4.0V<br>et eee eeeaaillll<br>≤  60μs PULSE WIDTH<br>Tj = 175°C<br>1 YLcrLLU | ll|<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 2.   Typical Output Characteristics<br>3.0<br>ID = 37A<br>2.5 V GS  = 10V L<br>2.0<br>van<br>y<br>1.5<br>1.0 eer LLL<br>0.50.0 TEL ELELELEL<br>-60 -40 -20 0 20 40 60 80 100 120 140 160 180<br>TJ , Junction Temperature (°C)<br>RDS(on) , Drain-to-Source On Resistance                        (Normalized)<br>ID, Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 4.** Normalized On-Resistance vs. Temperature 

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14<br>ID= 37A<br>12 VDS= 80V<br>VDS= 50V<br>10 | V DS = 20V >, LY.1 _|<br>8<br>pe LVn<br>6 | BY] |<br>4<br>{fT<br>20 74Yo<br>0 20 40 60 80<br> QG  Total Gate Charge (nC)<br>VGS, Gate-to-Source Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 6.** Typical Gate Charge vs. Gate-to-Source Voltage 

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1000<br>100<br>TJ = 175°C<br>10<br>TJ = 25°C<br>1<br>VGS = 0V<br>0.1<br>0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6<br>VSD, Source-to-Drain Voltage (V)<br>ISD, Reverse Drain Current (A)<br>**----- End of picture text -----**<br>


**Fig 7.** Typical Source-Drain Diode Forward Voltage 

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70<br>60 CAREEERU000R<br>50<br>PASSE<br>40<br>PEEPS<br>30 COPPA<br>20<br>COPE<br>10 CTT<br>0 BERERRERREEL<br>25 50 75 100 125 150 175<br>TJ,  Junction Temperature (°C)<br>**----- End of picture text -----**<br>


**Fig 9.** Maximum Drain Current vs. Case Temperature 

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1.2<br>1.0<br>pt | | le<br>0.8<br>Peery<br>0.6<br>Py<br>0.4<br>ven<br>0.2<br>40m<br>0.0<br>er | | |<br>0 20 40 60 80 100<br>VDS, Drain-to-Source Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 11.** Typical COSS Stored Energy 

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1000<br>OPERATION IN THIS AREA<br>LIMITED BY R DS(on)<br>100<br>100μsec<br>1msec<br>10<br>10msec<br>1<br>Tc = 25°C<br>Tj = 175°C DC<br>Single Pulse<br>0.1<br>1 10 100<br>VDS, Drain-toSource Voltage (V)<br>Fig 8.   Maximum Safe Operating Area<br>125<br>Id = 5mA<br>TTT<br>120<br>ATT<br>115<br>PEERDP Onn<br>110<br>Y<br>105<br>HERP AREER<br>100 ALTA<br>95<br>-60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Temperature ( °C )<br>Fig 10.   Drain-to-Source Breakdown Voltage<br>600<br>ID<br>500 TOP         4.7A<br>TE<br>12A<br>BOTTOM 37A<br>400<br>XCEL<br>300<br>NEL<br>200<br>SUISCUHEEERE<br>100<br>ONT<br>0 DUT PFSSSS<br>25 50 75 100 125 150 175<br>Starting TJ , Junction Temperature (°C)<br>V(BR)DSS, Drain-to-Source Breakdown Voltage (V)<br>EAS , Single Pulse Avalanche Energy (mJ)<br>ID,  Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 12.** Maximum Avalanche Energy vs. DrainCurrent 

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T@R Rectifier<br>10<br>1 Tt<br>D = 0.50<br>0.20<br>eeeee kl ee<br>0.10<br>0.1<br>0.05<br>ae 0.02<br>0.01<br>0.01 een a<br>Notes:<br>SINGLE PULSE<br>1. Duty Factor D = t1/t2<br>( THERMAL RESPONSE )<br>0.001 Fe Ot 2. Peak Tj = P dm x Zthjc + Tc ll<br>1E-006 1E-005 0.0001 0.001 0.01 0.1<br>t1 , Rectangular Pulse Duration (sec)<br>Fig 13.   Maximum Effective Transient Thermal Impedance, Junction-to-Case<br>100<br>FT Duty Cycle = Single Pulse CU Allowed avalanche Current vs avalanche<br>SS pulsewidth, tav, assuming  Δ Tj = 150 ° C and<br>Sn a Tstart =25°C (Single Pulse) HH<br>PRN 0.01 TPS TTI DTI LTT<br>10<br>0.05<br>PS HSS<br>Rt 0.10 SR<br>PISSPe<br>1<br>eee<br>cre Allowed avalanche Current vs avalanche  ee eee ee ee ee eer<br>pulsewidth, tav, assuming  ΔΤ j = 25°C and  EES EES<br>Tstart = 150°C.<br>Poa OO oe  er 0 0 | 0| ee ee ee|es<br>0.1<br>1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01<br>tav (sec)<br>Fig 14.   Typical Avalanche Current vs.Pulsewidth<br>140 Notes on Repetitive Avalanche Curves , Figures 14, 15:<br>TOP          Single Pulse                 (For further info, see AN-1005 at www.irf.com)<br>120 \ BOTTOM   1% Duty CycleID = 37A 1. Avalanche failures assumption:Purely a thermal phenomenon and failure occurs at a temperature far in<br>100 excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type.<br>2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded.<br>3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.<br>ENSNERRREEE<br>80 4. PD (ave) = Average power dissipation per single avalanche pulse.<br>5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase<br>60 during avalanche).<br>6. Iav = Allowable avalanche current.<br>ESN SCEREEEE<br>40 7.  Δ T = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as<br>25°C in Figure 14, 15).<br>LINN tav = Average time in avalanche.<br>20 D = Duty cycle in avalanche =  tav ·f<br>LLNS ZthJC(D, tav) = Transient thermal resistance, see Figures 13)<br>ELLE<br>0 EE MNA<br>25 50 75 100 125 150 175 PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) = A T/ ZthJCthJC<br>Iav =av == 2 A T/ [1.3·BV·Zth]th]]<br>Starting TJ , Junction Temperature (°C)<br>EAR , Avalanche Energy (mJ)<br>Avalanche Current (A)<br>Thermal Response ( Z thJC ) °C/W<br>**----- End of picture text -----**<br>


- Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type. 

2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded. 

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 

7. Δ T = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as 25°C in Figure 14, 15). 

**PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) =** A **T/ ZthJCthJC Iav =av == 2** A **T/ [1.3·BV·Zth]th]] EAS (AR) = PD (ave)·tav** 

**Fig 15.** Maximum Avalanche Energy vs. Temperature 

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4.5 pot | ft tt Et<br>4.0 |ENGR | T=~wy tt~SEeeett tt tt<br>ENGR ~SEeeett<br>3.5<br>ONE<br>Pt | RAL TE TE NL<br>3.0<br>RS<br>[[tT]] | ye<br>Pt [[tT]]<br>2.5<br>BAB OZANNSE<br>2.0 I D = 100μA 100μA TAZA NA<br>I D = 250μA 250μA A AZ| | AAIN<br>TAT| INAT<br>1.5 I D = 1.0mA 1.0mA ATAT| | | | | NN I<br>I D  = 1.0A 1.0A<br>SESEERE<br>1.0 | | | tt |<br>-75 -50 -25 0 25 50 75 100 125 150 175 200<br>TJ , Temperature ( °C )<br>VGS(th), Gate threshold Voltage (V)<br>**----- End of picture text -----**<br>


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4.5 pot | ft tt Et 24<br>4.0 |ENGR | T=~wy tt~SEeeett tt 20 ;<br>3.5<br>ONE CCA<br>16<br>Pt | RAL TE TE NL Po<br>3.0<br>RS [[tT]] | ye 12 PT| ot 4 |<br>Pt [[tT]] ee =<br>2.5<br>BAB OZANNSE EPC annnn<br>8<br>2.0 I D = 100μA 100μA TAZA NA aa IF = 24A<br>I D = 250μA 250μA A AZ| | AAIN Lor VR = 80V ——<br>1.5 I D = 1.0mA 1.0mA ATAT| | | INAT | NN I 4 p cA TJ = 125°C<br>I D  = 1.0A 1.0A TJ =  25°C<br>SESEERE PCO<br>1.0 | | | tt | 0<br>100 200 300 400 500 600 700 800 900 1000<br>-75 -50 -25 0 25 50 75 100 125 150 175 200<br>TJ , Temperature ( °C ) dif / dt - (A / μs)<br>Fig. 17 - Typical Recovery Current vs. di;/dt<br>Fig 16.   Threshold Voltage vs. Temperature<br>24 600<br>20 500<br>é<br>16128 ot SE EaeZaniewea pat]TT ||cd A" 400300200 PEEELTBib& |beee|erl? W4<br>IF = 37A IF = 24A<br>VR = 80V VR = 80V<br>4 iii 100<br>i TJ = 125°C  | rer TJ = 125°C<br>TJ =  25°C TJ =  25°C<br>0 Sanne 0 oo| =|<br>100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 700 800 900 1000<br>dif / dt - (A / μs) dif / dt - (A / μs)<br>VGS(th), Gate threshold Voltage (V)<br>QRR - (nC)<br>IRRM - (A)<br>IRRM - (A)<br>**----- End of picture text -----**<br>


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600<br>¢<br>500 BRR RREEE<br>¢<br>400 SERRE |<br>aD<br>7<br>300<br>SEREDZe<br>200<br>IF = 37A<br>LEE<br>VR = 80V<br>100<br>TJ = 125°C<br>T  =  25°C<br>J<br>0<br>100 200 300 400 500 600 700 800 900 1000<br>dif / dt - (A / μs)<br>QRR - (nC)<br>**----- End of picture text -----**<br>


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Driver Gate Drive<br>P.W.<br>D.U.T + {¢$ — P.W. ————— Period — + D = —— Period<br>) [©)]    •  CircuitLow  LayoutStray ConsiderationsInduct | V t t GS=10<br> •<br>- •   CurrentLow LeakageTransformerInductance @ D.U.T. ISD Waveform<br>+<br>® = ReverseRecovery Body Diode Forward \<br>- a - ® + Current r Current di/dt /<br>® D.U.T. VDS Waveform Diode Recoverydv/dt ‘<br>o) 00 > VDD<br>ma<br>•   Re-Applied<br>•   Driver same type as D.U.T. + Voltage Body Diode  Forward Drop<br>Re (A •   dv/dt controlled by Rg Vp p -<br>•<br>D.U.T. - Device Under Test SCO |<br>Ripple  ≤ 5% ISD<br>on Isp controlled by Duty Factor "D" @\ t<br>* Vg = 5V for Logic Level Devices<br>Fig 21.  Peak Diode Recovery dv/dt Test Circuit for N-Channel<br>HEXFET ® Power MOSFETs<br>V(BR)DSS<br>15V << tp ><br>VDS L DRIVER<br>RG D.U.T +<br>| IAS - [V][DD] A y |<br>20V<br>d k tp 0.01 Ω IAS |<br>Fig 22a.   Unclamped Inductive Test Circuit Fig 22b.   Unclamped Inductive Waveforms<br>LD<br>VDS V<br>DS<br>90%<br>+<br>VDD -<br>D.U.T 10%<br>i) VGS VGS ' \ f ewA H<br>Second Pulse Width < 1μs  IN on<br>Duty Factor < 0.1%<br>td(on) tr td(off) tf<br>Fig 23a.   Switching Time Test Circuit Fig 23b.   Switching Time Waveforms<br>Id<br>Vds<br>Vgs<br>L<br>VCC<br>DUT<br>0<br>S Vgs(th)<br>201 K<br>Sm: H Qgodr \ Qgd Qgs2 ' ‘ge Qgs1 !<br>Fig 24a.   Gate Charge Test Circuit Fig 24b.    Gate Charge Waveform<br>**----- End of picture text -----**<br>


**Fig 22b.** Unclamped Inductive Waveforms 

www.irf.com 

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**==> picture [365 x 230] intentionally omitted <==**

**----- Start of picture text -----**<br>
THIS IS AN IRF530S WITH<br>PART NUMBER<br>LOT CODE 8024 INTERNATIONAL<br>(A<br>ASSEMBLED ON WW 02, 2000 RECTIFIER F530S<br>IN THE ASSEMBLY LINE "L" LOGO T¢eaR 0021.<br>DATE CODE<br>80 24<br>YEAR 0 =  2000<br>ASSEMBLY<br>assembly line position LOT CODE T at , WEEK 02<br>t es "Lead — F ree” u uU LINE L<br>OR<br>PART NUMBER<br>INTERNATIONAL<br>C Y<br>RECTIFIER F530S<br>LOGO TéaR P002 A DATE CODE<br>P =  DESIGNATES LEAD - FREE<br>80 24<br>PRODUCT (OPTIONAL)<br>ASSEMBLY ( U L<br>LOT CODE 7, T , YEAR 0 =  2000<br>Ll U WEEK 02<br>A =  ASSEMBLY SITE CODE<br>**----- End of picture text -----**<br>


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## TO-262 Package Outline 

Dimensions are shown in millimeters (inches) 

## TO-262 Part Marking Information 

**==> picture [376 x 90] intentionally omitted <==**

**----- Start of picture text -----**<br>
EXAMPLE: THIS IS AN IRL3103L<br>LOT CODE 1789 PART NUMBER<br>ASSEMBLED ON WW 19, 1997 INTERNATIONAL c S<br>RECTIFIER<br>IN THE ASSEMBLY LINE "C" IRL3103L<br>LOGO<br>IeaR 719C<br>DATE CODE<br>17 89<br>YEAR 7 =  1997<br>No te : "P” in assembly line posi t ion ASSEMBLY<br>WEEK 19<br>indica t es "Lead — F ree” LOT CODE<br>LINE C<br>**----- End of picture text -----**<br>


## OR 

**==> picture [250 x 100] intentionally omitted <==**

**----- Start of picture text -----**<br>
PART NUMBER<br>INTERNATIONAL c S<br>RECTIFIER<br>IRL3103L<br>LOGO<br>IeaR P7i9 A<br>DATE CODE<br>17 89<br>P =  DESIGNATES LEAD-FREE<br>ASSEMBLY<br>LOT CODE PRODUCT (OPTIONAL)<br>YEAR 7 =  1997<br>WEEK 19<br>A =  ASSEMBLY SITE CODE<br>**----- End of picture text -----**<br>


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Dimensions are shown in millimeters (inches) 

**==> picture [18 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
TRR<br>**----- End of picture text -----**<br>


**==> picture [405 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.60 (.063)<br>1.50 (.059)<br>1.60 (.063)<br>4.10 (.161)<br>1.50 (.059)<br>3.90 (.153) 0.368 (.0145)<br>4 ! ___* 0 0°0Hd 0 | i GOS OO GE | @ T - e 0.342 (.0135)<br>FEED DIRECTION 1.85 (.073) 11.60 (.457)<br>1.65 (.065) 11.40 (.449) 24.30 (.957)<br>15.42 (.609)<br>23.90 (.941)<br>15.22 (.601)<br>TRL<br>| x<br>1.75 (.069)<br>10.90 (.429) 1.25 (.049)<br>10.70 (.421) 4.72 (.136)<br>16.10 (.634) 4.52 (.178)<br>15.90 (.626)<br>**----- End of picture text -----**<br>


**==> picture [74 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
FEED DIRECTION<br>**----- End of picture text -----**<br>


**==> picture [395 x 197] intentionally omitted <==**

**----- Start of picture text -----**<br>
13.50 (.532) 27.40 (1.079)<br>12.80 (.504) 23.90 (.941) ls<br>4<br>330.00(14.173) \ 60.00 (2.362)      MIN.<br>  MAX.<br>g x<br>30.40 (1.197)<br>NOTES :       MAX.<br>1.   COMFORMS TO EIA-418.<br>26.40 (1.039) 4<br>2.   CONTROLLING DIMENSION: MILLIMETER. 24.40 (.961)<br>3.   DIMENSION MEASURED @ HUB.<br>3<br>**----- End of picture text -----**<br>


4.   INCLUDES FLANGE DISTORTION @ OUTER EDGE. 

Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. 

**IR WORLD HEADQUARTERS:** 101N Sepulveda., El Segundo, California 90245, USA Tel: (310) 252- 

7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information **.** 04/2012 

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## Links

- [View this product on Novapart](https://novapart.co/products/IRFS4510TRLPBF/power-mosfet-n-channel-100-v-61-a-00139-ohm-to-263)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/infineon/irfs4510trlpbf/mosfet-n-ch-100v-61a-to-263/dp/3514438)
---

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