# Power MOSFET, N Channel, 150 V, 105 A, 0.0118 ohm, TO-263 (D2PAK), Surface Mount

![Product image](https://novapart.co/image/farnell:2839496/)

**URL**: https://novapart.co/products/IRFS4115TRL7PP/power-mosfet-n-channel-150-v-105-a-00118-ohm-to
**SKU**: IRFS4115TRL7PP
**Manufacturer**: INFINEON
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.5700
**Stock**: 500+
**Lead Time**: 2 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:105A; Drain Source Voltage Vds:150V; On Resistance Rds(on):0.01ohm; Available until stocks are exhausted Alternative available

## Specifications

| Parameter | Value |
|---|---|
| Msl | - |
| Svhc | No SVHC (21-Jan-2025) |
| No. Of Pins | 7Pins |
| Channel Type | N Channel |
| Product Range | HEXFET |
| Qualification | - |
| Power Dissipation | 380W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-263 (D2PAK) |
| Drain Source Voltage Vds | 150V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 105A |
| Drain Source On State Resistance | 0.0118ohm |
| Gate Source Threshold Voltage Max | 5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2839496/)

## IRFS4115-7PPbF 

HEXFET ® Power MOSFET 

## **Applications** 

High Efficiency Synchronous Rectification in SMPS Uninterruptible Power Supply High Speed Power Switching Hard Switched and High Frequency Circuits 

## **Benefits** 

|||D||**VDSS**|||**150V**|
|---|---|---|---|---|---|---|---|
|||||**RDS(on) typ.**|**typ.**||**10.0m**|
|||||||||
|G||||**max.**|**max. **||**11.8m**|
|||||||||
|||S||**ID **|||**105A**|



Improved  Gate, Avalanche and Dynamic  dV/dt Ruggedness 

Fully Characterized Capacitance and Avalanche SOA 

Enhanced body diode dV/dt and dI/dt Capability Lead-Free 

|**G**<br>**D**<br>**S**|
|---|
|Gate<br>Drain<br>Source|
|**Absolute Maximum Ratings**|
|**Symbol**<br>**Parameter**<br>**Units**<br>**Max.**<br>~~o_{1o---"eeeNo>o>OW~~|
|ID@ TC= 25°C<br>Continuous Drain Current, VGS@ 10V<br>105<br>~~a~~|
|ID@ TC= 100°C<br>Continuous Drain Current, VGS@ 10V<br>A<br>74<br>~~a~~|
|IDM<br>Pulsed Drain Current<br>420<br>~~a~~|
|PD@TC= 25°C<br>Maximum Power Dissipation<br>W<br>380<br>~~a~~|
|Linear DeratingFactor<br>W/°C<br>2.5<br>~~a~~|
|VGS<br>Gate-to-Source Voltage<br>V<br>± 20<br>~~a~~|
|dv/dt<br>Peak Diode Recovery<br>V/ns<br>32<br>~~TW~~|
|TJ<br>Operating Junction and<br>°C<br>-55  to + 175|
|TSTG<br>Storage Temperature Range|
|Soldering Temperature, for 10 seconds<br>300|
|(1.6mm from case)|
|Mountingtorque,6-32 or M3 screw<br>10lb in(1.1N m)<br>~~a~~|
|**Avalanche Characteristics**|
|EAS(Thermallylimited)<br>Single Pulse Avalanche Energy<br>mJ<br>IAR<br>Avalanche Current<br>A<br>EAR<br>Repetitive Avalanche Energy<br>mJ<br>230<br>See Fig. 14, 15, 22a, 22b,<br>~~a~~<br>~~ooo~~<br>~~eee~~<br>~~a~~<br>~~——~~|
|**Thermal Resistance**|
|**Symbol**<br>**Parameter**<br>**Typ.**<br>**Max.**<br>**Units**<br>RθJC<br>Junction-to-Case<br>–––<br>0.40<br>°C/W<br>RθJA<br>Junction-to-Ambient(PCB Mount)<br>–––<br>40<br>~~a~~<br>~~a~~<br>~~es~~<br>~~n°~~|
|www.irf.com<br>1|



11/7/08 

**Static @ TJ = 25°C (unless otherwise specified)** 

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||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Symbol|Parameter|Min.|Typ.|Max.|Units|Conditions|
|es|GO|GO|OO|
|V(BR)DSS|Drain-to-Source Breakdown Voltage|150|–––|–––|V|VGS = 0V, ID = 250μA|
|es|GO|OO|GO|
|pf|ΔV(BR)DSS/ΔTJ|Breakdown Voltage Temp. Coefficient|–––|0.18|–––|V/°C|Reference to 25°C, ID = 3.5mA|
|RDS(on)|Static Drain-to-Source On-Resistance|–––|10.|11.8|mΩ|VGS = 10V, ID = 63A|
|a|GO|QO|GO|©|
|sD|VGS(th)|Gate Threshold Voltage|GO|3.0|–––|GO|5.0|OO|V|VDS = VGS, ID = 250μA|
|IDSS|Drain-to-Source Leakage Current|–––|–––|20|μA|VDS = 150V, VGS = 0V|
|a|–––|–––|250|VDS = 150V, VGS = 0V, TJ = 125°C|
|a|ee|
|IGSS|Gate-to-Source Forward Leakage|–––|–––|100|nA|VGS = 20V|
|_——————GO|Gate-to-Source Reverse Leakage|–––|–––|-100|ee|VGS = -20V|
|a|RG(int)|Internal Gate Resistance|–––|2.1|QO|–––|Ge|Ω|
|DG|GO|GO|
|Dynamic @ TJ = 25°C (unless otherwise specified)|
|Symbol|Parameter|Min.|Typ.|Max.|Units|Conditions|
|es|GO|GO|OO|
|a|gfs|GD|Forward Transconductance|93|–––|–––|S|VDS = 50V, ID = 62A|
|a|Qg|Total Gate Charge|–––|73|OO|110|GO|nC|ID = 63A|
|a|Qgs|Gate-to-Source Charge|–––|28|–––|VDS = 75V|
|a|Qgd|Gate-to-Drain ("Miller") Charge|–––|28|–––|VGS = 10V|®|
|a|Qsync|GO|Total Gate Charge Sync. (Qg - Qgd)|–––|45|–––|ID = 63A, VDS =0V, VGS = 10V|
|a|td(on)|Turn-On Delay Time|–––|18|OO|–––|Ge|ns|VDD = 98V|
|a|tr|Rise Time|–––|50|–––|ID = 63A|
|a|td(off)|Turn-Off Delay Time|–––|37|–––|RG = 2.1Ω|
|a|tf|Fall Time|–––|23|–––|VGS = 10V|®|
|a|Ciss|Input Capacitance|–––|5320|–––|VGS = 0V|
|a|Coss|Output Capacitance|–––|490|–––|VDS = 50V|
|a|Crss|Reverse Transfer Capacitance|–––|110|–––|pF|ƒ = 1.0MHz|
|ec|Coss eff. (ER)|Effective Output Capacitance (Energy Related)|–––|450|–––|VGS = 0V, VDS = 0V to 120V|
|a|Coss eff. (TR)|Effective Output Capacitance (Time Related)|–––|520|–––|VGS = 0V, VDS = 0V to 120V|
|Diode Characteristics|
|a|Symbol|GD|Parameter|Min.|Typ.|QO|Max.|GO|Units|Conditions|
|IS|Continuous Source Current|–––|–––|104|A|MOSFET symbol|
|D|
|(Body Diode)|showing  the|
|ISM|Pulsed Source Current|–––|–––|420|integral reverse|
|G|
|(Body Diode)|p-n junction diode.|S|
|VSD|Diode Forward Voltage|–––|–––|1.3|V|TJ = 25°C, IS = 63A, VGS = 0V|
|esND|
|trr|Reverse Recovery Time|–––|82|–––|ns|TJ = 25°C|VR = 130V,|
|–––|99|–––|TJ = 125°C|IF = 63A|
|es|Qrr|Reverse Recovery Charge|–––|[=o]|271|GO|–––|GO|nC|TJ = 25°C|di/dt = 100A/μs|
|–––|385|–––|TJ = 125°C|
|e|IRRM|Reverse Recover|s|y Current|||–––|[=o]|||6.0|–––|A|TJ = 25°C|
|s|||||
|a|ton|Qe|Forward Turn-On Time|Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)|

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> Repetitive rating;  pulse width limited by max. junction © Coss eff. (TR) is a fixed capacitance that gives the same charging time temperature. as Coss while VDS is rising from 0 to 80% VDSS. @ Limited by TJmax, starting TJ = 25°C, L = 0.115mHJmax, starting TJ = 25°C, L = 0.115mH, starting TJ = 25°C, L = 0.115mHJ = 25°C, L = 0.115mH= 25°C, L = 0.115mH © Coss eff. (ER) is a fixed capacitance that gives the same energy asoss eff. (ER) is a fixed capacitance that gives the same energy as eff. (ER) is a fixed capacitance that gives the same energy as 

- @ Limited by TJmax, starting TJ = 25°C, L = 0.115mHJmax, starting TJ = 25°C, L = 0.115mH, starting TJ = 25°C, L = 0.115mHJ = 25°C, L = 0.115mH= 25°C, L = 0.115mH © Coss eff. (ER) is a fixed capacitance that gives the same energy asoss eff. (ER) is a fixed capacitance that gives the same energy as eff. (ER) is a fixed capacitance that gives the same energy as RG = 25Ω, IAS = 63A, VGS =10V. Part not recommended for 

Coss while VDS is rising from 0 to 80% VDSS. 

- use above this value. 

@ When mounted on 1" square PCB (FR-4 or G-10 Material).  For recom mended footprint and soldering techniques refer to application note #AN-994. Rθ is measured at TJ approximately 90°C. 

ISD ≤ 63A, di/dt ≤ 2510A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. Pulse width ≤ 400μs; duty cycle ≤ 2%. 

θJC 

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1000 1000<br>VGS VGS<br>TOP           15V TOP           15V<br>10V 10V<br>100 8.0V7.0V 8.0V7.0V<br>6.5V 6.5V<br>6.0V 6.0V<br>5.5V 100 5.5V<br>[ LA BOTTOM 5.0V | fe BOTTOM 5.0V<br>10<br>1<br>10<br>a p 5 Sh a a t r<br>5.0V<br>0.1 5.0V<br>a ≤60μs PULSE WIDTH ee ee ≤60μs PULSE WIDTH<br>Tj = 25°C Tj = 175°C<br>0.01 FF E _tHitt-FHiEl 1 FHA wt<br>0.1 1 10 100 1000 0.1 1 10 100 1000<br>VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)<br>Fig 1.   Typical Output Characteristics Fig 2.   Typical Output Characteristics<br>1000 3.0<br>ID = 63A<br>2.5 V GS  = 10V<br>100<br>faeSASS TJ = 175°C an 2.0 HTTLEELA<br>10<br>P| Vx | | 1.5 EEE LLL<br>TJ = 25°C<br>PAA y d LL DALLL<br>1.0<br>1<br>= 4<br>2 V aaa DS = 50V er ELL LL<br>0.5<br>≤ 60μs PULSE WIDTH<br>0.1<br>ai LELLELEL LEE<br>3.0 4.0 5.0 6.0 7.0 8.0 9.0 0.0<br>-60 -40 -20 0 20 40 60 80 100120140160180<br>VGS, Gate-to-Source Voltage (V)<br>TJ , Junction Temperature (°C)<br>Fig 4.   Normalized On-Resistance vs. Temperature<br>Fig 3.   Typical Transfer Characteristics<br>8000 16<br>VGS   = 0V,       f = 1 MHZ ID= 63A<br>Ciss   = Cgs + Cgd,  Cds SHORTED<br>Crss   = Cgd  VDS= 120V<br>6000 a a C oss   = CC ds  iss+ C gd 12 eo VVDSDS= 75V= 30V |<br>8<br>4000<br>Tim «= Fa<br>x iil eh<br>4<br>2000 Coss<br>eel Crss 0<br>0<br>0 20 40 60 80 100<br>1 10 100<br> QG  Total Gate Charge (nC)<br>VDS, Drain-to-Source Voltage (V)<br>VGS, Gate-to-Source Voltage (V)<br>ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A)<br>)(Α<br>ID, Drain-to-Source Current<br>RDS(on) , Drain-to-Source On Resistance                        (Normalized)<br>C, Capacitance (pF)<br>**----- End of picture text -----**<br>


**Fig 4.** Normalized On-Resistance vs. Temperature 

**Fig 5.** Typical Capacitance vs. Drain-to-Source Voltage 

**Fig 6.** Typical Gate Charge vs. Gate-to-Source Voltage 

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1000 10000<br>OPERATION IN THIS AREA<br>LIMITED BY R DS(on)<br>1000<br>100<br>TJ = 175°CJ = 175°C= 175°C<br>10 0 μsec<br>f e 100 Cr SSCE Ccl<br>10<br>1msec<br>pf f TJ = 25°CJ = 25°C= 25°C t 10 SS5rii ect s eee Eset<br>10ms ec<br>1<br>1<br>Tc = 25°C<br>—{-—_|—|— ee ee ee<br>Tj = 175°C<br>VGS = 0VGS = 0V= 0V Single Pulse D C<br>p p 0.1 a<br>0.1<br>ii on<br>0.1 1 10 100 1000<br>0.0 0.5 1.0 1.5 2.0<br>VDS,  Drain-toSource Voltage (V)<br>VSD, Source-to-Drain Voltage (V)<br>Fig 7.   Typical Source-Drain Diode Fig 8.   Maximum Safe Operating Area<br>Forward Voltage<br>120 190<br>Id = 3.5mA<br>100<br>TOT 180 PRINZ<br>80<br>ST ee<br>170<br>60<br>160<br>40 PEEPS Str A<br>ETL TTEN ara<br>20 TTT 150 ALLEL<br>0 LTTE PELE ELE<br>140<br>25 50 75 100 125 150 175<br>-60 -40 -20 0 20 40 60 80 100120140160180<br>TC , CaseTemperature (°C)<br>TJ , Temperature ( °C )<br>Fig 9.   Maximum Drain Current vs. Fig 10.   Drain-to-Source Breakdown Voltage<br>Case Temperature<br>4 1000<br>                 I D<br>TOP         14A<br>800                24A<br>3 BOTTOM   63A<br>600 NO<br>2<br>400<br>CREE<br>1<br>200<br>SACEE<br>ESS<br>0 0<br>0 20 40 60 80 100 120 140 25 50 75 100 125 150 175<br>VDS, Drain-to-Source Voltage (V) Starting TJ, Junction Temperature (°C)<br>ISD, Reverse Drain Current (A) ID,  Drain-to-Source Current (A)<br>ID  , Drain Current (A)<br>Energy (μJ)<br>EAS, Single Pulse Avalanche Energy (mJ)<br>V(BR)DSS, Drain-to-Source Breakdown Voltage (V)<br>**----- End of picture text -----**<br>


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1000<br>100<br>f TJ = 175°CJ = 175°C= 175°C e<br>10<br>pf f TJ = 25°CJ = 25°C= 25°C t<br>1<br>—{-—_|—|—<br>VGS = 0VGS = 0V= 0V<br>p p<br>0.1<br>0.0 0.5 1.0 1.5 2.0<br>VSD, Source-to-Drain Voltage (V)<br>ISD, Reverse Drain Current (A)<br>**----- End of picture text -----**<br>


**Fig 10.** Drain-to-Source Breakdown Voltage 

**Fig 11.** Typical COSS Stored Energy 

**Fig 12.** Maximum Avalanche Energy Vs. DrainCurrent 

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1 PF EEETAAR  FP<br>EEA AR<br>D = 0.50<br>ee eat ell<br>0.1 etaEEE [ee]<br>0.20<br>ee as ea ee ee eee| eee|eee<br>0.10 R1 R1 R2 R2 R3 R3 R4R4 Ri (°C/W) τι (sec)<br>0.05 τJ τJ τCτ 0.015402 0.00001<br>0.02 τ1 τ1 τ2 τ2 τ3 τ3 τ4 τ4 0.0569890.180208 0.0000650.001377<br>0.01 a 2 | ee ee<br>SS 0.01 Ci= Ciτi/Rii/Ri 0.146323 0.010705 |<br>ee SINGLE PULSE a ee oeeeeee| e e | Notes: a |<br>( THERMAL RESPONSE ) 1. Duty Factor D = t1/t2<br>2. Peak Tj = P dm x Zthjc + Tc<br>Zit Oe<br>0.001<br>1E-006 1E-005 0.0001 0.001 0.01 0.1<br>an i ca<br>t1 , Rectangular Pulse Duration (sec)<br>Fig 13.   Maximum Effective Transient Thermal Impedance, Junction-to-Case<br>1000<br>Allowed avalanche Current vs avalanche<br>pulsewidth, tav, assuming  ΔTj = 150°C and<br>a Duty Cycle = Single Pulse eee ||| | |<br>Tstart =25°C (Single Pulse)<br>100<br>Ss E<br>PA 0.01 TPRRELLET<br>10 | | | || 0.05 gE ee ne<br>SEE, 0.10 SSeS Sa<br>FF TT Sayan — ll ee<br>es ee 7 A |<br>1<br>I YATEerie<br>ITT<br>Allowed avalanche Current vs avalanche<br>pulsewidth, tav, assuming ΔΤ j = 25°C and<br>| Tstart = 150°C. | TE | EE<br>0.1<br>1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01<br>tav (sec)<br>Fig 14.   Typical Avalanche Current vs.Pulsewidth<br>240 Notes on Repetitive Avalanche Curves , Figures 14, 15:<br>TOP          Single Pulse                 (For further info, see AN-1005 at www.irf.com)<br>BOTTOM   1% Duty Cycle 1. Avalanche failures assumption:<br>200 I D  = 63A Purely a thermal phenomenon and failure occurs at a temperature far in<br>LL... excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type.<br>160 WNL 2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded.<br>3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.<br>AN PTT TT Ty Ty 4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse.<br>120 PNN EEE 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase<br>during avalanche).<br>6. Iav = Allowable avalanche current.<br>INA EEE<br>80 NaN 7. ΔT = Allowable rise in junction temperature, not to exceedΔT = Allowable rise in junction temperature, not to exceedT = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as<br>25°C in Figure 14, 15).<br>tav = Average time in avalanche.<br>40 D = Duty cycle in avalanche =  tav ·f<br>CONSETT ZthJC(D, tav) = Transient thermal resistance, see Figures 13)<br>tPA<br>0 KL<br>25 50 75 100 125 150 175 PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) = A T/ ZthJCthJC<br>Starting TJ , Junction Temperature (°C) IEav =Eav =av =AS (AR)= 2 A T/ [1.3·BV·Z = P = PD (ave)·tth]th]av] ·tth]th]av]<br>EAR , Avalanche Energy (mJ)<br>Thermal Response ( Z thJC )<br>Avalanche Current (A)<br>**----- End of picture text -----**<br>


- Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type. 

2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded. 

3. Equation below based on circuit and waveforms shown in Figures 22a, 22b. 

4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse. 

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 

7. ΔT = Allowable rise in junction temperature, not to exceedΔT = Allowable rise in junction temperature, not to exceedT = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as 25°C in Figure 14, 15). 

**PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) =** A **T/ ZthJCthJC IEav =Eav =av =AS (AR)= 2** A **T/ [1.3·BV·Z = P = PD (ave)·tth]th]av]** 

**Fig 15.** Maximum Avalanche Energy vs. Temperature 

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6.0 50<br>ID = 1.0A<br>5.0 coo eeoeeee ID = 1.0mA 40<br>ID = 250μA<br>-CRRHKR<br>4.03.0 TSSSSSNIN 3020<br>See BSN<br>2.0 eeeeeNY 10<br>1.0 0<br>-75 -50 -25 0 25 50 75 100 125 150 175 100<br>TJ , Temperature ( °C )<br>Fig.<br>Fig 16.   Threshold Voltage Vs. Temperature<br>50 2400<br>40 BRREEEEE va 20001600<br>30 BRRRDESZe<br>1200<br>20 nnp>zannl<br>t 800<br>IF = 63A<br>10 PZdil iee VR = 127V n<br>400<br>TJ = 125°C<br>TJ =  25°C<br>T=<br>0 0<br>100 200 300 400 500 600 700 800 900 1000 100<br>dif / dt - (A / μs)<br>Fig. 18 - Typical Recovery Current vs. di;/dt Fig.<br>2400<br>itty<br>2000<br>*<br>tt | eeLye<br>1600 ¢<br>"4  a<br>1200 BRRREAP<br>800 ERaee= 4a ann Ze<br>IF = 63A<br>VR = 127V<br>400 wert<br>a t TJ = 125°C  |<br>TJ =  25°C<br>0<br>Pitt tf =|<br>100 200 300 400 500 600 700 800 900 1000<br>dif / dt - (A / μs)<br>IRRM - (A)<br>IRRM - (A) QRR - (nC)<br>QRR - (nC)<br>VGS(th) Gate threshold Voltage (V)<br>**----- End of picture text -----**<br>


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50 BRRREEEDE<br>40<br>=<br>| ee<br>aara<br>203020<br>ae<br>IF = 42A<br>10 eZ40l  ae VR = 127V<br>TJ = 125°C<br>TJ =  25°C<br>0<br>100 200 300 400 500 600 700 800 900 1000<br>dif / dt - (A / μs)<br>Fig. 17 - Typical Recovery Current vs. di;/dt<br>2400<br>BRREEEEEE<br>160020001600 et ee<br>S<br>1200<br>ete<br>800 Beas aenn<br>IF = 42A<br>ATT VR = 127V<br>400<br>TJ = 125°C<br>TJ =  25°C<br>PTH =<br>0<br>100 200 300 400 500 600 700 800 900 1000<br>dif / dt - (A / μs)<br>IRRM - (A)<br>QRR - (nC)<br>**----- End of picture text -----**<br>


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Driver Gate Drive<br>P.W.<br>Period D =<br>+ P.W. Period<br>D.U.T {$$ | ————| —— |t<br>VGS=10V<br>) ©)    •  Circuit Layout Considerations |<br> •<br>| —| - LowGround StrayPla I n eductance<br> •   CurrentLow LeakageTransformerInductance ® D.U.T. ISD Waveform<br>+<br>Reverse<br>@ - a | S - ® + RecoveryCurrent r Body Diode ForwardCurrent di/dt /\ —I<br>00 ® D.U.T. VDS Waveform Diode Recovery =<br>dv/dt ‘ VDD<br>ma<br>•   Re-Applied<br>•   Driver same type as D.U.T. + Voltage Body Diode  Forward Drop<br>Re ( aA •   dv/dt controlled by Rg Vpp -<br>•<br>D.U.T. - Device Under Test es ae<br>Isp controlled by Duty Factor "D" iO) t Ripple  ≤ 5% ISD<br>* Veg = 5V for Logic Level Devices<br>Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel<br>HEXFET ® Power MOSFETs<br>V(BR)DSS<br>15V < tp ><br>VDS L DRIVER<br>RG D.U.T +<br>- [V][DD]<br>IAS A<br>20VVGS<br>tp 0.01Ω IAS<br>**----- End of picture text -----**<br>


**Fig 22a.** Unclamped Inductive Test Circuit 

## **Fig 22b.** Unclamped Inductive Waveforms 

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+<br>-<br>≤ 1  us<br>≤ 0.1 %<br>**----- End of picture text -----**<br>


## **Fig 23a.** Switching Time Test Circuit 

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Current Regulator<br>Same Type as D.U.T.<br>50KΩ<br>12V .2μF<br>.3μF<br>+<br>D.U.T. -VDS<br>VGS<br>3mA<br>NWA IG ID<br>Current Sampling Resistors<br>**----- End of picture text -----**<br>


**Fig 24a.** Gate Charge Test Circuit 

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**----- Start of picture text -----**<br>
VDS<br>90%<br>\<br>10%<br>VGS |«le ys| |<br>td(on) tr td(off) tf<br>**----- End of picture text -----**<br>


**==> picture [164 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig 23b.   Switching Time Waveforms<br>**----- End of picture text -----**<br>


**==> picture [162 x 131] intentionally omitted <==**

**----- Start of picture text -----**<br>
Id<br>Vds<br>Vgs<br>Vgs(th)<br>t g p i e p!<br>Qgs1 Qgs2 Qgd Qgodr<br>**----- End of picture text -----**<br>


**Fig 24b.** Gate Charge Waveform 

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7 

D[2] Pak - 7 Pin Package Outline Dimensions are shown in millimeters (inches) 

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## D[2] Pak - 7 Pin Part Marking Information 

## D[2] Pak - 7 Pin Tape and Reel 

Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. 

**IR WORLD HEADQUARTERS:** 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information **.** 11/08 

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- [View this product on Novapart](https://novapart.co/products/IRFS4115TRL7PP/power-mosfet-n-channel-150-v-105-a-00118-ohm-to)
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- [Supplier page](https://es.farnell.com/infineon/irfs4115trl7pp/mosfet-n-ch-150v-105a-to-263/dp/2839496)
---

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