# Power MOSFET, N Channel, 40 V, 240 A, 1250 µohm, TO-263 (D2PAK), Surface Mount

![Product image](https://novapart.co/image/farnell:2725977/)

**URL**: https://novapart.co/products/IRFS3004TRL7PP/power-mosfet-n-channel-40-v-240-a-1250-ohm-to-263
**SKU**: IRFS3004TRL7PP
**Manufacturer**: INFINEON
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.5200
**Stock**: 200+
**Lead Time**: 64 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:240A; Drain Source Voltage Vds:40V; On Resistance Rds(on):900µohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; Powe

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 7Pins |
| Channel Type | N Channel |
| Product Range | HEXFET |
| Qualification | - |
| Power Dissipation | 380W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-263 (D2PAK) |
| Drain Source Voltage Vds | 40V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 240A |
| Drain Source On State Resistance | 1250µohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2725977/)

## IRFS3004-7PPbF 

## HEXFET ® Power MOSFET 

## **Applications** 

High Efficiency Synchronous Rectification in SMPS Uninterruptible Power Supply High Speed Power Switching Hard Switched and High Frequency Circuits 

## **Benefits** 

Improved  Gate, Avalanche and Dynamic  dV/dt Ruggedness 

|**VDSS**|**40V**|
|---|---|
|**RDS(on)   typ.**<br>**max.**|**0.90m**Ω|
||**1.25m**Ω|
|**ID (Silicon Limited)**|**400A**|
|**ID (Package Limited)**|**240A**|



Fully Characterized Capacitance and Avalanche SOA 

Enhanced body diode dV/dt and dI/dt Capability Lead-Free 

|**G**|**D**|**S**|
|---|---|---|
|Gate|Drain|Source|



## **Absolute Maximum Ratings** 

|**Symbol**|**Parameter**<br>**Units**<br>**Max.**|
|---|---|
|ID@ TC= 25°C<br>Continuous Drain Current, VGS@ 10V(Silicon Limited)<br>ID@ TC= 100°C<br>Continuous Drain Current, VGS@ 10V(Silicon Limited)<br>ID@ TC= 25°C<br>Continuous Drain Current, VGS@ 10V(Wire Bond Limited)<br>IDM<br>Pulsed Drain Current<br>PD@TC= 25°C<br>Maximum Power Dissipation<br>W<br>Linear DeratingFactor<br>W/°C<br>2.5<br>400<br>280<br>1610<br>240<br>A<br>380<br>~~a~~<br>~~a~~<br>~~ne~~<br>~~a~~<br>~~a~~<br>~~nD~~<br>~~I~~<br>~~Pe~~||
|VGS|Gate-to-Source Voltage<br>V<br>± 20<br>~~a~~|
|dv/dt|Peak Diode Recovery<br>V/ns<br>2.0<br>~~GO~~|
|TJ<br>TSTG|Operating Junction and<br>Storage Temperature Range<br>SolderingTemperature,for 10 seconds(1.6mm from case)<br>-55  to + 175<br>°C<br>300<br>~~Ee eee~~|
|**Avalanche Characteristics**||
|EAS(Thermallylimited)<br>~~a~~|Single Pulse Avalanche Energy<br>mJ<br>290<br>~~a~~<br>~~a~~<br>~~i~~|
|IAR<br>Avalanche Current<br>A<br>EAR<br>Repetitive Avalanche Energy<br>mJ<br>**Thermal Resistance**<br>See Fig. 14, 15, 22a, 22b<br>~~ae —sFeeeeeseses—eH~~||
|**Symbol**<br>**Parameter**<br>**Typ.**<br>**Max.**<br>**Units**<br>RθJC<br>Junction-to-Case<br>–––<br>0.40<br>°C/W<br>RθJA<br>Junction-to-Ambient(PCB Mount)<br>–––<br>40<br>~~GO~~<br>~~eSSea~~<br>~~a~~||



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**Static @ TJ = 25°C (unless otherwise specified)** 

|**Symbol**<br>**Parameter**<br>**Min. Typ. Max. Units**<br>V(BR)DSS<br>Drain-to-Source Breakdown Voltage<br>40<br>–––<br>–––<br>V<br>∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient<br>–––<br>0.038<br>–––<br>V/°C<br>RDS(on)<br>Static Drain-to-Source On-Resistance<br>–––<br>0.90<br>1.25<br>mΩ<br>VGS(th)<br>Gate Threshold Voltage<br>2.0<br>–––<br>4.0<br>V<br>IDSS<br>Drain-to-Source Leakage Current<br>–––<br>–––<br>20<br>µA<br>–––<br>–––<br>250<br>IGSS<br>Gate-to-Source Forward Leakage<br>–––<br>–––<br>100<br>nA<br>Gate-to-Source Reverse Leakage<br>–––<br>–––<br>-100<br>**Conditions**<br>VGS= 0V,ID= 250µA<br>Reference to 25°C, ID= 5mA<br>VGS= 10V,ID= 195A<br>VDS= VGS,ID= 250µA<br>VDS= 40V,VGS= 0V<br>VDS= 40V,VGS= 0V,TJ= 125°C<br>VGS= 20V<br>VGS= -20V<br>~~ae~~<br>~~ss QO~~<br>~~QQ~~<br>~~a~~<br>~~GQ GG~~<br>~~Pe~~<br>~~Ge~~<br>~~GQ GQ~~<br>~~ee~~<br>~~||~~<br>~~———————————~~<br>~~a~~|
|---|
|RG<br>Internal Gate Resistance<br>–––<br>2.0<br>–––<br>Ω<br>~~es~~|
|**Dynamic @ TJ = 25°C (unless otherwise specified)**|
|**Symbol**<br>**Parameter**<br>**Min. Typ. Max. Units**<br>gfs<br>Forward Transconductance<br>1300<br>–––<br>–––<br>S<br>Qg<br>Total Gate Charge<br>–––<br>160<br>240<br>nC<br>**Conditions**<br>VDS= 10V,ID= 195A<br>ID= 180A<br>~~a~~<br>~~Pe GsGQ~~<br>~~QO~~<br>~~GO~~<br>~~a~~|
|Qgs<br>Gate-to-Source Charge<br>–––<br>42<br>–––<br>VDS=20V<br>~~a~~|
|Qgd<br>Gate-to-Drain("Miller")Charge<br>–––<br>65<br>–––<br>VGS= 10V<br>~~a~~<br>®|
|Qsync<br>Total Gate Charge Sync.(Qg- Qgd)<br>–––<br>95<br>–––<br>ID= 180A,VDS=0V,VGS= 10V<br>~~a~~|
|td(on)<br>Turn-On DelayTime<br>–––<br>23<br>–––<br>ns<br>VDD= 26V<br>~~a~~|
|tr<br>Rise Time<br>–––<br>240<br>–––<br>ID= 240A<br>~~a~~|
|td(off)<br>Turn-Off DelayTime<br>–––<br>91<br>–––<br>RG= 2.7Ω<br>~~a~~|
|tf<br>Fall Time<br>–––<br>160<br>–––<br>VGS= 10V<br>~~a~~<br>®|
|Ciss<br>Input Capacitance<br>–––<br>9130<br>–––<br>pF<br>VGS= 0V<br>~~a~~|
|Coss<br>Output Capacitance<br>–––<br>2020<br>–––<br>VDS= 25V<br>~~a~~|
|Crss<br>Reverse Transfer Capacitance<br>–––<br>990<br>–––<br>ƒ= 1.0 MHz,See Fig. 5<br>~~a~~|
|Cosseff.(ER)<br>EffectiveOutputCapacitance(EnergyRelated)<br>–––<br>2590<br>–––<br>VGS= 0V,VDS= 0V to 32V<br>,See Fig. 11<br>~~a~~<br>®|
|Cosseff.(TR)<br>EffectiveOutputCapacitance(Time Related)<br>–––<br>2650<br>–––<br>VGS= 0V,VDS= 0V to 32V<br>~~©~~<br>©|
|**Diode Characteristics**|
|S<br>D<br>G<br>**Symbol**<br>**Parameter**<br>**Min. Typ. Max. Units**<br>IS<br>Continuous Source Current<br>–––<br>–––<br>400<br>A<br>(BodyDiode)<br>ISM<br>Pulsed Source Current<br>–––<br>–––<br>1610<br>A<br>(BodyDiode)<br>VSD<br>Diode Forward Voltage<br>–––<br>–––<br>1.3<br>V<br>trr<br>Reverse Recovery Time<br>–––<br>49<br>–––<br>ns<br>TJ= 25°C<br>VR= 34V,<br>–––<br>51<br>–––<br>TJ= 125°C<br>IF= 240A<br>Qrr<br>Reverse Recovery Charge<br>–––<br>37<br>–––<br>nC<br>TJ= 25°C<br>di/dt = 100A/µs<br>–––<br>41<br>–––<br>TJ= 125°C<br>IRRM<br>Reverse RecoveryCurrent<br>–––<br>3.2<br>–––<br>A<br>TJ= 25°C<br>ton<br>Forward Turn-On Time<br>Intrinsic turn-on time is negligible(turn-on is dominated byLS+LD)<br>TJ= 25°C,IS= 195A,VGS= 0V<br>integral reverse<br>p-njunction diode.<br>MOSFET symbol<br>showing  the<br>**Conditions**<br>~~ae~~<br>~~eG GQ~~<br>~~ee eee~~<br>~~ee~~<br>~~QQ~~<br>~~GO CO~~<br>~~ee~~<br>~~||~~<br>~~eeeeee~~<br>;<br>~~fT~~<br>~~a~~<br>~~Cn~~|



Notes: ® Calculated continuous current based on maximum allowable junction ® ISD ≤ 240A, di/dt ≤ 740A/µs, VDD ≤ V(BR)DSS, TJ , TJ ≤ 175°C. 

> ® Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 240A. Note that current limitations arising from heating of the device leads may occur with 

® ISD ≤ 240A, di/dt ≤ 740A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. ® Pulse width ≤ 400µs; duty cycle ≤ 2%. © Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.oss while VDS is rising from 0 to 80% VDSS.while VDS is rising from 0 to 80% VDSS.DS is rising from 0 to 80% VDSS.is rising from 0 to 80% VDSS.DSS.. Coss eff. (ER) is a fixed capacitance that gives the same energy asoss eff. (ER) is a fixed capacitance that gives the same energy as eff. (ER) is a fixed capacitance that gives the same energy as 

some lead mounting arrangements. (Refer to AN-1140) as Coss while VDS is rising from 0 to 80% VDSS.oss while VDS is rising from 0 to 80% VDSS.while VDS is rising from 0 to 80% VDSS.DS is rising from 0 to 80% VDSS.is rising from 0 to 80% VDSS.DSS.. ®@ Repetitive rating;  pulse width limited by max. junction Coss eff. (ER) is a fixed capacitance that gives the same energy asoss eff. (ER) is a fixed capacitance that gives the same energy as eff. (ER) is a fixed capacitance that gives the same energy as temperature. Coss while VDS is rising from 0 to 80% VDSS. @ Limited by TJmax, starting TJ = 25°C, L = 0.01mH When mounted on 1" square PCB (FR-4 or G-10 Material).  For recom RG = 25 Ω , IAS = 240A, VGS =10V. Part not recommended for use mended footprint and soldering techniques refer to application note #AN-994. above this value . @R θ is measured at Ty approximately 90°C. 

When mounted on 1" square PCB (FR-4 or G-10 Material).  For recom mended footprint and soldering techniques refer to application note #AN-994. 

θ JC 

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1000<br>VGS<br>TOP           15V<br>10V<br>PO aaa 8.0V<br>7.0V<br>100 A y 6.0V<br>5.5V |<br>5.0V<br>BOTTOM 4.5V<br>10<br>YT TT TTT TTT TTT<br>ee ell<br>1<br>T IE I<br>4.5V ≤ 60µs PULSE WIDTH<br>0.1 ll Tj = 25°C all<br>0.1 1 10 100 1000<br>VDS, Drain-to-Source Voltage (V)<br>Fig 1.   Typical Output Characteristics<br>1000<br>ee en 7<br>100<br>—=S TJ = 175°C { aS<br>a<br>10 oi ee oe TJ  es = 25°C eee<br>ee 6 ee ee ee ee ee<br>1<br>= i Ae ee eee V . DS = 25V ;<br>≤ 60µs PULSE WIDTH<br>0.1 7-H if [jf][|]<br>3 4 5 6 7 8<br>VGS, Gate-to-Source Voltage (V)<br>ID, Drain-to-Source Current (A)<br>ID, Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 3.** Typical Transfer Characteristics 

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100000<br>VGS   = 0V,       f = 1 MHZ<br>Ciss   = C gs + Cgd,  C ds SHORTED<br>| [|] - F CCrss  oss   = C= Cds gd + Cgd E<br>10000 Ciss<br>Coss S e<br>=<br>; Se ee<br>Crss<br>S H<br>1000<br>G ah, Samal<br>fePTTee<br>100 PIE EEL<br>1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>C, Capacitance (pF)<br>**----- End of picture text -----**<br>


**Fig 5.** Typical Capacitance vs. Drain-to-Source Voltage 

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1000<br>VGS<br>TOP           15V<br>10V<br>WAel) 8.0V<br>7.0V<br>/Al 6.0V<br>ny Manag 5.5V<br>5.0V<br>BOTTOM 4.5V<br>100<br>A enn<br>PAI, SLT<br>ASAHT<br>4.5V ≤ 60µs PULSE WIDTH<br>10 L O. Tj = 175°C<br>0.1 1 10 100 1000<br>VDS, Drain-to-Source Voltage (V)<br>Fig 2.   Typical Output Characteristics<br>2.0<br>ID = 195A<br>VGS = 10V<br>1.5 2<br>a<br>LE ALLL4<br>1.0 e T LZ! LLLLT<br>PLEELL<br>0.5 LLL EEE<br>-60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Junction Temperature (°C)<br>Fig 4.   Normalized On-Resistance vs. Temperature<br>14.0<br>ID= 180A<br>12.0<br>VDS= 32V<br>10.0 P rto VDS= 20V Tp f T<br>8.0<br>| iz<br>6.0<br>e /a<br>4.0<br>A T<br>2.0 A y |]<br>0.0 PTtT ty<br>0 50 100 150 200 250<br> QG,  Total Gate Charge (nC)<br>ID, Drain-to-Source Current (A)<br>RDS(on) , Drain-to-Source On Resistance                        (Normalized)<br>VGS, Gate-to-Source Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 4.** Normalized On-Resistance vs. Temperature 

**Fig 6.** Typical Gate Charge vs. Gate-to-Source Voltage 

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1000<br>T = 175°C<br>J<br>100<br>T = 25°C<br>J<br>10<br>1<br>VGS = 0V<br>0.1<br>0.0 0.5 1.0 1.5 2.0<br>VSD, Source-to-Drain Voltage (V)<br>Fig 7.   Typical Source-Drain Diode<br>Forward Voltage<br>420<br>360 Limited By Package<br>Pee<br>300<br>o y<br>240<br>p2 4<br>180 aN<br>120<br>j ~it th<br>60 L LIN<br>E EL<br>0<br>25 50 75 100 125 150 175<br> TC , Case Temperature (°C)<br>Fig 9.   Maximum Drain Current vs.<br>Case Temperature<br>3.5<br>3.0 T ILL<br>2.5<br>P CCEETEE<br>2.0<br>S ERR E<br>1.5 P CO<br>1.00.5 TCT TP e A<br>P EC<br>0.0<br>-5 0 5 10 15 20 25 30 35 40 45<br>VDS, Drain-to-Source Voltage (V)<br>Energy (µJ)<br>ISD, Reverse Drain Current (A)<br>ID,  Drain Current (A)<br>**----- End of picture text -----**<br>


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420<br>360 Limited By Package<br>Pee<br>300<br>o y<br>240<br>p2 4<br>180 aN<br>120<br>j ~it th<br>60 L LIN<br>E EL<br>0<br>25 50 75 100 125 150 175<br> TC , Case Temperature (°C)<br>ID,  Drain Current (A)<br>**----- End of picture text -----**<br>


**Fig 11.** Typical COSS Stored Energy 

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10000<br>OPERATION IN THIS AREA<br>LIMITED BY R DS(on)<br>1000<br>1 00µsec<br>100<br>1msec<br>1 0mse c<br>10<br>Tc = 25°C<br>DC<br>Tj = 175°C<br>Single Pulse<br>1<br>0 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 8.   Maximum Safe Operating Area<br>50<br>Id = 5mA<br>48<br>S ALLE<br>E EE<br>46<br>a<br>L EAL.<br>44<br>42 W LLL<br>LY<br>ALLL LLL<br>40<br>-60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Temperature ( °C )<br>Fig 10.   Drain-to-Source Breakdown Voltage<br>1200<br>ID<br>L LL TOP         44A<br>1000<br>80A<br>BOTTOM 240A<br>800 N EE<br>T NE<br>600<br>E N<br>400<br>N UN<br>200 ETELTT<br>NP SBN<br>0<br>25 50 75 100 125 150 175<br>Starting TJ , Junction Temperature (°C)<br>V(BR)DSS, Drain-to-Source Breakdown Voltage (V)<br>ID,  Drain-to-Source Current (A)<br>EAS , Single Pulse Avalanche Energy (mJ)<br>**----- End of picture text -----**<br>


**Fig 10.** Drain-to-Source Breakdown Voltage 

**Fig 12.** Maximum Avalanche Energy vs. DrainCurrent 

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1<br>a a ee ee ee eee ee ee<br>D = 0.50<br>0.1 F o mr TTI<br>0.01 — Fa 0.200.100.050.02 =aerlee allleel τ J τ TTT J τ 1 τ 1 m R1 R1 τ 2 τ R22 R2 R τ 33 R τ 3 3 τ R4 τ 4R4 4  FI τ C τ | Ri (°C/W)   0.00757     0.0000060.06508     0.0000640.18313     0.001511  τ i (sec)<br>0.01 Ci=  τ i / Ri 0.14378     0.009800<br>pe aTea ee eeTTI ee Ci i / Ri —ee eee:<br>a es 0 ee 0 | Notes: Al|._+# osnn<br>SINGLE PULSE 1. Duty Factor D = t1/t2<br>( THERMAL RESPONSE )<br>2. Peak Tj = P dm x Zthjc + Tc<br>0.001 aVani te 1| en senill<br>1E-006 1E-005 0.0001 0.001 0.01 0.1<br>t1 , Rectangular Pulse Duration (sec)<br>Fig 13.   Maximum Effective Transient Thermal Impedance, Junction-to-Case<br>1000<br>Pa Duty Cycle = Single Pulse PPEE<br>ee Allowed avalanche Current vs avalanche  Hl<br>|SSS i pea | 4 pulsewidth, tav, assuming  ∆ Tj = 150°C and  TT<br>0.01 Tstart =25°C (Single Pulse)<br>100<br>P SS RY<br>P 0.05 OSTE<br>0.10<br>O T EEE tt<br>10 A RSTS| =<br>| Allowed avalanche Current vs avalanche  a a OC 8<br>pulsewidth, tav, assuming  ∆Τ j = 25°C and<br>Tstart = 150°C.<br>AE  Een<br>1<br>1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01<br>tav (sec)<br>Fig 14.   Typical Avalanche Current vs.Pulsewidth<br>320<br>e l Notes on Repetitive Avalanche Curves , Figures 14, 15:<br>TOP          Single Pulse<br>Gil (For further info, see AN-1005 at www.irf.com)<br>280 BOTTOM   1.0% Duty Cycle<br>I N 1. Avalanche failures assumption:<br>RN ID = 240A Purely a thermal phenomenon and failure occurs at a temperature far in<br>240 N EN 2. Safe operation in Avalanche is allowed as long asTexcess of Tjmax. This is validated for every part type.jmax<br>200 P N OINEIDLTE Et 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.<br>160 NR ENNP 4. P5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increaseD (ave) = Average power dissipation per single avalanche pulse.<br>P t;TNINWe| eee| tteeettee during avalanche).<br>120 N N 6. Iav = Allowable avalanche current.<br>e e ee ee eee 7.  ∆ T = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as<br>80 See  NeENEEeeeeNaNEEEe 25°C in Figure 14, 15).<br>n annaND Vn tav = Average time in avalanche.<br>40 e ee eaNaVae D = Duty cycle in avalanche =  tav ·f<br>n ee NaN ZthJC(D, tav) = Transient thermal resistance, see Figures 13)<br>0 P| | TT | tTENN<br>25 50 75 100 125 150 175 PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) = A T/ ZthJCthJC<br>Iav =av == 2 A T/ [1.3·BV·Zth]th]]<br>Starting TJ , Junction Temperature (°C) EAS (AR) = PD (ave)·tav  = PD (ave)·tav ·tav<br>EAR , Avalanche Energy (mJ)<br>Avalanche Current (A)<br>Thermal Response ( Z thJC ) °C/W<br>**----- End of picture text -----**<br>


- Purely a thermal phenomenon and failure occurs at a temperature far in 

- jmax is not exceeded. 

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 

- D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse. 

- during avalanche). 

7. ∆ T = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as 25°C in Figure 14, 15). 

**PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) =** A **T/ ZthJCthJC Iav =av == 2** A **T/ [1.3·BV·Zth]th]] EAS (AR) = PD (ave)·tav** 

**Fig 15.** Maximum Avalanche Energy vs. Temperature 

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4.5 T P LTTITTrLeeelAA<br>4.0 P A A CE<br>3.5 TENE<br>3.0 P ASSERLZ<br>2.5<br>ID = 250µA<br>ID = 1.0mA<br>2.0 ID = 1.0A PEE NN EE<br>rt INN 1<br>1.5<br>EE EEEEEENEEE Ee<br>1.0<br>-75 -50 -25 0 25 50 75 100 125 150 175 200<br>TJ , Temperature ( °C )<br>VGS(th), Gate threshold Voltage (V)<br>**----- End of picture text -----**<br>


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10<br>IF = 96A<br>9 ae a‘<br>VR = 34V<br>8 TJ = 25°C _ |LtA<br>nae Pa<br>TJ = 125°C<br>7<br>e ° t<br>6<br>5<br>e t<br>4 a<br>3<br>2 Pp otoft|<br>100 200 300 400 500<br>diF /dt (A/µs)<br>IRRM (A)<br>**----- End of picture text -----**<br>


**Fig 16.** Threshold Voltage vs. Temperature 

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12<br>11 IF = 144A<br>VR = 34V A<br>10<br>TJ = 25°C<br>9 T J = 125°C Pr ZZ<br>8<br>a ee<br>7<br>6<br>p f<br>5 a a<br>4 ee Zy<br>3<br>F ar<br>2 i<br>100 200 300 400 500<br>diF /dt (A/µs)<br>IRRM (A)<br>**----- End of picture text -----**<br>


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140<br>IF = 96A<br>120 VR = 34V TT<br>TJ = 25°C<br>100 TJ = 125°C an ee.<br>80 tH<br>B aZa<br>60<br>LT<br>e p<br>40<br>| |<br>E t<br>20<br>100 200 300 400 500<br>diF /dt (A/µs)<br>QRR (nC)<br>**----- End of picture text -----**<br>


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180<br>IF = 144A<br>160<br>VR = 34V<br>140 TJ = 25°C<br>TJ = 125°C<br>120<br>100 | Ee<br>YL<br>80 F t AVA<br>60<br>i<br>40<br>20 Rep ||<br>100 200 300 400 500<br>diF /dt (A/µs)<br>QRR (nC)<br>**----- End of picture text -----**<br>


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**==> picture [413 x 344] intentionally omitted <==**

**----- Start of picture text -----**<br>
Driver Gate Drive<br>P.W.<br>D.U.T + {+ P.W. Period ——— — D = —— Period<br>VGS=10<br>)    •  | t<br> •   Ground lane<br>Pp ©) - Circuit •   Low Layout Leakage ConsiderationsInductance @ D.U.T. ISD Waveform t<br>+<br>Reverse<br>Recovery Body Diode Forward<br>oi - [1] Current Transformer - ® + Current r Current di/dt AN<br>® D.U.T. VDS Waveform Diode Recoverydv/dt ‘<br>00 a VDD<br>ma<br>•   Re-Applied<br>•   Driver same type as D.U.T. + Voltage Body Diode  Forward Drop<br>Re ( 4 •   dv/dt controlled by Rg Vpp -<br>•<br>D.U.T. - Device Under Test SOO |<br>Ripple  ≤ 5% ISD<br>Isp controlled by Duty Factor "D" @| t<br>* Vg = 5V for Logic Level Devices<br>Fig 21.  Peak Diode Recovery dv/dt Test Circuit for N-Channel<br>HEXFET ® Power MOSFETs<br>V(BR)DSS<br>15V —_ tp -><br>VDS L DRIVER<br>RG D.U.T +<br>- [V][DD]<br>IAS A<br>¢ 20VVGS dt<br>tp 0.01 Ω IAS<br>**----- End of picture text -----**<br>


**Fig 22a.** Unclamped Inductive Test Circuit 

**Fig 22b.** Unclamped Inductive Waveforms 

**==> picture [130 x 58] intentionally omitted <==**

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+<br>-<br>≤ 1  ys<br>≤ 0.1 %<br>**----- End of picture text -----**<br>


## **Fig 23a.** Switching Time Test Circuit 

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Current Regulator<br>Same Type as D.U.T.<br>50K Ω<br>12V .2 µ F .3 µ F ||<br>+<br>D.U.T. -VDS<br>VGS<br>3mA<br>WAV IG ID<br>Current Sampling Resistors<br>**----- End of picture text -----**<br>


**Fig 24a.** Gate Charge Test Circuit 

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VDS<br>90%<br>\<br>10% /\<br>VGS |«le ys| |<br>td(on) tr td(off) tf<br>**----- End of picture text -----**<br>


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Fig 23b.   Switching Time Waveforms<br>**----- End of picture text -----**<br>


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Id<br>Vds<br>fl Vgs<br>i<br>Vgs(th)<br>a plag [p] [l] [e] w i e » !<br>Qgs1 Qgs2 Qgd Qgodr<br>**----- End of picture text -----**<br>


**Fig 24b.** Gate Charge Waveform 

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D[2] Pak - 7 Pin Package Outline Dimensions are shown in millimeters (inches) 

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## D[2] Pak - 7 Pin Part Marking Information 

## D[2] Pak - 7 Pin Tape and Reel 

Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. 

**IR WORLD HEADQUARTERS:** 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information **.** 04/2010 

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## Links

- [View this product on Novapart](https://novapart.co/products/IRFS3004TRL7PP/power-mosfet-n-channel-40-v-240-a-1250-ohm-to-263)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/infineon/irfs3004trl7pp/mosfet-n-ch-100v-240a-to-263/dp/2725977)
---

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