# Power MOSFET, N Channel, 75 V, 350 A, 1850 µohm, TO-247AC, Through Hole

![Product image](https://novapart.co/image/farnell:1684529/)

**URL**: https://novapart.co/products/IRFP4368PBF/mosfet-75v-350a-to-247ac
**SKU**: IRFP4368PBF
**Manufacturer**: INFINEON
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €3.3200
**Stock**: 10+

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:350A; Drain Source Voltage Vds:75V; On Resistance Rds(on):0.00146ohm; Rds(on) Test Voltage Vgs:20V; Threshold Voltage Vgs:4V; Power Di

## Specifications

| Parameter | Value |
|---|---|
| Msl | - |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 520W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 20V |
| Transistor Case Style | TO-247AC |
| Drain Source Voltage Vds | 75V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 350A |
| Drain Source On State Resistance | 1850µohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:1684529/)

## IRFP4368PbF 

## **Applications** 

High Efficiency Synchronous Rectification in SMPS 

Uninterruptible Power Supply 

High Speed Power Switching Hard Switched and High Frequency Circuits 

## **Benefits** 

Improved  Gate, Avalanche and Dynamic dv/dt Ruggedness Fully Characterized Capacitance and Avalanche SOA Enhanced body diode dV/dt and dI/dt Capability 

## HEXFET Power MOSFET 

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D VDSS 75V<br>ee<br>RDS(on)   typ. PF 1.46m Ω<br>              max. 1.85m Ω<br>G ID (Silicon Limited) 350A<br>eePF Oe<br>S ID (Package Limited) 195A<br>ee ee<br>**----- End of picture text -----**<br>


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D<br>S<br>D<br>G<br>TO-247AC<br>**----- End of picture text -----**<br>


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|||||||||
|---|---|---|---|---|---|---|---|
|G|D|S|
|Gate|Drain|Source|
|Absolute Maximum Ratings|
|LD|Symbol|Parameter|Max.|Units|
|ef|ID @ TC = 25°C|Continuous Drain Current, VGS @ 10V (Silicon Limited)|350|
|ID @ TC = 100°C|Continuous Drain Current, VGS @ 10V (Silicon Limited)|250|A|
|ee©|
|ID @ TC = 25°C|Continuous Drain Current, VGS @ 10V (Wire Bond Limited)|195|
|ee(OO|
|PO|IDM|Pulsed Drain Current|1280|
|PD @TC = 25°C|Maximum Power Dissipation|520|W|
|ee|nn|
|Linear Derating Factor|3.4|W/°C|
|eeRD|
|a|VGS|Gate-to-Source Voltage|(O|± 20|V|
|dv/dt|Peak Diode Recovery|13|V/ns|
|eeS(OPe|
|TJ|Operating Junction and|-55  to + 175|°C|
|TSTG|Storage Temperature Range|
|Soldering Temperature, for 10 seconds|300|
|(1.6mm from case)|
|a|nS|Mounting torque, 6-32 or M3 screw|(OO|10lb|in (1.1N|m)|
|Avalanche Characteristics|
|||EAS (Thermally limited)|Single Pulse Avalanche Energy|430|mJ|
|IAR|Avalanche Current|See Fig. 14, 15, 22a, 22b|A|
|9ee|EAR|Repetitive Avalanche Energy|Oe|irT|mJ|
|Thermal Resistance|
|a|Symbol|Parameter|Typ.|Max.|Units|
|||RθJC|Junction-to-Case|–––|0.29|
|a|RθCS|nn|Case-to-Sink, Flat Greased Surface|Oe|0.24|–––|°C/W|
|a|RθJA|a|Junction-to-Ambient|–––|40|

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www.irf.com 

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06/02/08 

**Static @ TJ = 25°C (unless otherwise specified)** 

|**Symbol**<br>**Parameter**<br>**Min. Typ. Max. Units**<br>V(BR)DSS<br>Drain-to-Source Breakdown Voltage<br>75<br>–––<br>–––<br>V<br>∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient<br>–––<br>0.077<br>–––<br>V/°C<br>RDS(on)<br>Static Drain-to-Source On-Resistance<br>–––<br>1.46<br>1.85<br>mΩ<br>VGS(th)<br>Gate Threshold Voltage<br>2.0<br>–––<br>4.0<br>V<br>IDSS<br>Drain-to-Source Leakage Current<br>–––<br>–––<br>20<br>µA<br>–––<br>–––<br>250<br>IGSS<br>Gate-to-Source Forward Leakage<br>–––<br>–––<br>100<br>nA<br>Gate-to-Source Reverse Leakage<br>–––<br>–––<br>-100<br>**Dynamic @ TJ = 25°C (unless otherwise specified)**<br>**Conditions**<br>VGS= 0V, ID= 250µA<br>Reference to 25°C, ID= 5mA<br>VGS= 10V, ID= 195A<br>VDS= VGS, ID= 250µA<br>VDS= 75V, VGS= 0V<br>VDS= 75V, VGS= 0V, TJ= 125°C<br>VGS= 20V<br>VGS= -20V<br>~~aeGD~~<br>~~GO~~<br>~~as ee~~<br>~~GD U~~~~**D**GO GO~~<br>~~asG GO GO~~<br>~~rs~~<br>~~GD O~~~~**D**Q~~~~**O**~~<br>~~©~~<br>~~as ee~~<br>~~GD U~~<br>~~G~~<br>~~GO~~<br>~~|~~<br>~~Pt ee~~<br>~~_————————————_———~~~~**e**EE~~<br>~~es~~<br>~~e~~|
|---|
|S<br>D<br>G<br>**Symbol**<br>**Parameter**<br>**Min. Typ. Max. Units**<br>gfs<br>Forward Transconductance<br>650<br>–––<br>–––<br>S<br>Qg<br>Total Gate Charge<br>–––<br>380<br>570<br>nC<br>Qgs<br>Gate-to-Source Charge<br>–––<br>79<br>–––<br>Qgd<br>Gate-to-Drain("Miller")Charge<br>–––<br>105<br>–––<br>Qsync<br>Total Gate Charge Sync. (Qg- Qgd)<br>–––<br>275<br>–––<br>RG(int)<br>Internal Gate Resistance<br>–––<br>0.80<br>–––<br>Ω<br>td(on)<br>Turn-On DelayTime<br>–––<br>43<br>–––<br>ns<br>tr<br>Rise Time<br>–––<br>220<br>–––<br>td(off)<br>Turn-Off DelayTime<br>–––<br>170<br>–––<br>tf<br>Fall Time<br>–––<br>260<br>–––<br>Ciss<br>Input Capacitance<br>–––<br>19230<br>–––<br>pF<br>Coss<br>Output Capacitance<br>–––<br>1670<br>–––<br>Crss<br>Reverse Transfer Capacitance<br>–––<br>770<br>–––<br>Cosseff.(ER)<br>Effective Output Capacitance(EnergyRelated)<br>–––<br>1700<br>–––<br>Cosseff.(TR)<br>Effective Output Capacitance(Time Related)<br>–––<br>1410<br>–––<br>**Diode Characteristics**<br>**Symbol**<br>**Parameter**<br>**Min. Typ. Max. Units**<br>IS<br>Continuous Source Current<br>–––<br>–––<br>350<br>A<br>(BodyDiode)<br>ISM<br>Pulsed Source Current<br>–––<br>–––<br>1280<br>(BodyDiode)<br>VSD<br>Diode Forward Voltage<br>–––<br>–––<br>1.3<br>V<br>trr<br>Reverse Recovery Time<br>–––<br>130<br>200<br>ns<br>TJ= 25°C<br>VR= 64V,<br>–––<br>140<br>210<br>TJ= 125°C<br>IF= 195A<br>Qrr<br>Reverse Recovery Charge<br>–––<br>450<br>680<br>nC<br>TJ= 25°C<br>di/dt = 100A/µs<br>–––<br>530<br>800<br>TJ= 125°C<br>IRRM<br>Reverse RecoveryCurrent<br>–––<br>9.1<br>–––<br>A<br>TJ= 25°C<br>ton<br>Forward Turn-On Time<br>Intrinsic turn-on time is negligible(turn-on is dominated byLS+LD)<br>ID= 195A<br>RG= 2.7Ω<br>VGS= 10V<br>VDD= 49V<br>ID= 195A, VDS=0V, VGS= 10V<br>TJ= 25°C,IS= 195A,VGS= 0V<br>integral reverse<br>p-njunction diode.<br>MOSFET symbol<br>showing  the<br>VDS= 38V<br>**Conditions**<br>VGS= 10V<br>VGS= 0V<br>VDS= 50V<br>ƒ= 100kHz<br>VGS= 0V,VDS= 0V to 60V<br>VGS= 0V,VDS= 0V to 60V<br>**Conditions**<br>VDS= 50V, ID= 195A<br>ID= 195A<br>~~aeGD~~<br>~~GO~~<br>~~as ee~~<br>~~GD UDGO GO~~<br>~~esee~~<br>~~es~~<br>~~esee~~<br>~~es~~<br>~~esee~~<br>~~es ee~~<br>~~es~~<br>~~ee~~<br>~~as ee~~<br>~~GD UDGO GO~~<br>~~esee~~<br>~~es~~<br>~~esee~~<br>~~es~~<br>~~eeen~~<br>~~eea~~<br>~~eea~~<br>~~eea~~<br>~~eea~~<br>~~ee”~~<br>~~Reee~~<br>~~Seo~~<br>~~|~~<br>~~a QD~~<br>~~GO~~<br>~~PEE~~<br>~~PT~~<br>~~a ee ee~~<br>~~PT~~<br>~~ae~~<br>~~aQR~~|



Notes: ~~©~~ Calculated continuous current based on maximum allowable junction ~~®~~ ISD ≤ 195A, di/dt ≤ 1740A/µs, V 195A, di/dt ≤ 1740A/µs, V≤ 1740A/µs, V 1740A/µs, VDD ≤ VV(BR)DSS, TJ ≤ 175°C. 175°C. ≤ 195A, di/dt ≤ 1740A/µs, V 195A, di/dt ≤ 1740A/µs, V≤ 1740A/µs, V 1740A/µs, VDD ≤ VV(BR)DSS, TJ ≤ 175°C. 175°C. ≤ VV(BR)DSS, TJ ≤ 175°C. 175°C. , TJ ≤ 175°C. 175°C. ≤ 175°C. 175°C. 

~~©~~ Calculated continuous current based on maximum allowable junction ~~®~~ ISD ≤ 195A, di/dt ≤ 1740A/µs, V 195A, di/dt ≤ 1740A/µs, V≤ 1740A/µs, V 1740A/µs, VDD ≤ VV(BR)DSS, TJ ≤ 175°C. 175°C. temperature. Bond wire current limit is 195A. Note that current ~~©~~ Pulse width ≤ 400µs; duty cycle ≤ 2%. limitations arising from heating of the device leads may occur with © Coss eff. (TR) is a fixed capacitance that gives the same charging time some lead mounting arrangements. Refer to App Notes (AN-1140). as Coss while VDS is rising from 0 to 80% VDSS. 

@ Repetitive rating;  pulse width limited by max. junction @ temperature. 

Coss eff. (ER) is a fixed capacitance that gives the same energy as 

Coss while VDS is rising from 0 to 80% VDSS. 

Limited by TJmax, starting TJ = 25°C, L = 0.022mH 

When mounted on 1" square PCB (FR-4 or G-10 Material).  For recom mended footprint and soldering techniques refer to application note #AN-994. Rθ is measured at TJ approximately 90°C. 

RG = 25Ω, IAS = 195A, VGS =10V. Part not recommended for use above this value. 

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1000<br>VGS<br>TOP           15V fe<br>10V<br>8.0V<br>7.0V<br>6.0V<br>5.5V<br>4.8V<br>BOTTOM 4.5V<br>100 4 a<br>_— aad<br>4.5V —<br>≤60µs PULSE WIDTH60µs PULSE WIDTH<br>Tj = 25°C<br>aii<br>10<br>0.1 1 10 100<br>tiie<br>VDS, Drain-to-Source Voltage (V)<br>ID, Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


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1000 1000<br>VGS VGS<br>TOP           15V fe TOP           15V Fo<br>10V 10V<br>8.0V 8.0V<br>7.0V 7.0V<br>6.0V 6.0V<br>5.5V 5.5V<br>4.8V 4.8V<br>BOTTOM 4.5V BOTTOM 4.5V<br>4.5V<br>100 4 a 100 a t<br>_— aad a Za<br>4.5V — 7<br>≤60µs PULSE WIDTH60µs PULSE WIDTH ≤60µs PULSE WIDTH<br>Tj = 25°C Tj = 175°C<br>aii<br>10 10<br>0.1 1 10 100 0.1 1 10 100<br>tiie =|<br>VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)<br>Fig 1.   Typical Output Characteristics Fig 2.   Typical Output Characteristics<br>1000 2.5<br>e VDS  r = 25V a ID = 195A<br>≤60µs PULSE WIDTH VGS = 10V<br>2.0<br>100 TT ] =  C an<br>oa T TT<br>1.5<br>Pt PT APY YY T ITEL<br>TJ = 175°C TJ = 25°C<br>10 ot EM LL<br>c Pys ee Oryp| ee | 1.0 LO TTTEWA  TTT<br>1.0 ei ye yy 0.5 aT EEE<br>1 2 3 4 5 6 7 -60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Junction Temperature (°C)<br>VGS, Gate-to-Source Voltage (V)<br>Fig 4.   Normalized On-Resistance vs. Temperature<br>Fig 3.   Typical Transfer Characteristics<br>1E+006 12.0<br>VGS   = 0V,       f = 1 MHZ<br>Ciss    = Cgs + Cgd,  Cds SHORTED ID= 195A<br>Crss    = Cgd  10.0 VDS= 60V<br>100000 Coss   = Cds + Cgd VDS= 38V<br>fo 8.0 Py<br>F ETA ETT A.<br>Ciss<br>10000 6.0<br>Coss<br>4.0<br>Crss<br>1000<br>ee ee ee eee ee eee 2.0 /|<br>100 PEE EHH 0.0 Vit iit ti<br>1 10 100 0 50 100 150 200 250 300 350 400<br>VDS, Drain-to-Source Voltage (V)  QG,  Total Gate Charge (nC)<br>ID, Drain-to-Source Current (A)<br>ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A)<br>RDS(on) , Drain-to-Source On Resistance                        (Normalized)<br>C, Capacitance (pF)<br>VGS, Gate-to-Source Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 4.** Normalized On-Resistance vs. Temperature 

**Fig 5.** Typical Capacitance vs. Drain-to-Source Voltage 

**Fig 6.** Typical Gate Charge vs. Gate-to-Source Voltage 

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1000 e e a ee<br>TJ = 175°C<br>100 a e =<br>10 TJ = 25°C<br>| ffi ft P|<br>1 ee ee oeee eeee ed<br>S S ee<br>ee<br>VGS = 0V<br>Pe ee ee pe<br>0.1<br>0.0 0.4 0.8 1.2 1.6 2.0<br>VSD, Source-to-Drain Voltage (V)<br>ISD, Reverse Drain Current (A)<br>**----- End of picture text -----**<br>


**Fig 7.** Typical Source-Drain Diode Forward Voltage 

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350<br>300 Limited By Package<br>250 t ty ) po<br>o y<br>200<br>vo n<br>150 PPT<br>100<br>+++<br>50 e w<br>T EN<br>0<br>25 50 75 100 125 150 175<br> TC , Case Temperature (°C)<br>ID,  Drain Current (A)<br>**----- End of picture text -----**<br>


**Fig 9.** Maximum Drain Current vs. Case Temperature 

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6.0<br>5.0<br>4.0<br>3.0 r o y<br>2.0<br>Y Y<br>1.00.0 |<br>10 20 30 40 50 60 70 80<br>VDS, Drain-to-Source Voltage (V)<br>Energy (µJ)<br>**----- End of picture text -----**<br>


**Fig 11.** Typical COSS Stored Energy 

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10000<br>OPERATION IN THIS AREA  7]<br>LIMITED BY RDS(on)<br>1000<br>100µsec<br>ot ted<br>100<br>1msec<br>Pege ar s enf e e<br>1 0 msec<br>10 peee o AN QA |<br>Tc = 25°C e e ee Il<br>Tj = 175°C ee e ies<br>Single Pulse DC<br>1 eee se ece im<br>1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 8.   Maximum Safe Operating Area<br>95<br>Id = 5.0mA<br>90<br>S o LLEL ELLE<br>A T<br>85<br>La<br>ALLEL.<br>80 V AL LLL.<br>75<br>)<br>E LLE<br>70 ELELEL<br>-60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Temperature ( °C )<br>ID,  Drain-to-Source Current (A)<br>V(BR)DSS, Drain-to-Source Breakdown Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 10.** Drain-to-Source Breakdown Voltage 

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2000<br>ID<br>TOP         33A<br>53A<br>1500<br>BOTTOM 195A<br>A NULLCT<br>1000<br>500 N ANO TELEE<br>0 S S SS<br>25 50 75 100 125 150 175<br>Starting TJ , Junction Temperature (°C)<br>EAS , Single Pulse Avalanche Energy (mJ)<br>**----- End of picture text -----**<br>


**Fig 12.** Maximum Avalanche Energy vs. DrainCurrent 

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1<br>D = 0.50 ee e | ee |ae<br>0.1 Se e—— tl<br>0.20<br>0.10<br>0.05<br>0.01 a es 0.010.02 eenieree I τJ τJτ1τ1 o R o 1 R 1 τ2τR22 R 2 ea Rτ33 R τ . 3 3 τR4τ4R4 4 τCτ ee Ri (°C/W)   0.0145       0.0000240.0661       0.0001480.1257       0.002766 e  τi (sec) ee<br>0.001 P oe Ci= τi/Ri 0.0838       0.017517<br>SINGLE PULSE Ci i/Ri<br>iA OT PP Notes:<br>( THERMAL RESPONSE )<br>EE<br>1. Duty Factor D = t1/t2<br>2. Peak Tj = P dm x Zthjc + Tc<br>0.0001 F eet FALE EEE an ill<br>1E-006 1E-005 0.0001 0.001 0.01 0.1<br>t1 , Rectangular Pulse Duration (sec)<br>Fig 13.   Maximum Effective Transient Thermal Impedance, Junction-to-Case<br>1000<br>FT TTT o T OTES<br>P Duty Cycle = Single Pulse oEFEE Allowed avalanche Current vs avalanche  EE<br>pulsewidth, tav, assuming  ∆Tj = 150°C and<br>0.01 Tstart =25°C (Single Pulse)<br>100 a<br>0.05<br>0.10<br>10 seerOTT meeNOESa ScatooEl<br>F assc<br>Allowed avalanche Current vs avalanche<br>eeEennneEeneneennnn Gn EAD] | tame TTI<br>pulsewidth, tav, assuming  ∆Τj = 25°C and<br>Tstart = 150°C.<br>1 eaS 0eee0 eel<br>1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01<br>tav (sec)<br>Fig 14.   Typical Avalanche Current vs.Pulsewidth<br>500 Notes on Repetitive Avalanche Curves , Figures 14, 15:<br>| |ft | TOP          Single Pulse                 (For further info, see AN-1005 at www.irf.com)<br>BOTTOM   1.0% Duty Cycle 1. Avalanche failures assumption:<br>400 ID = 195A Purely a thermal phenomenon and failure occurs at a temperature far in<br>excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type.<br>K e 2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded.<br>3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.<br>300 W NOTOL 4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse.<br>5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase<br>during avalanche).<br>200 N NONEEL 6. Iav = Allowable avalanche current.<br>7. ∆T = Allowable rise in junction temperature, not to exceed∆T = Allowable rise in junction temperature, not to exceedT = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as<br>25°C in Figure 14, 15).<br>100 ELNNI aS tav = Average time in avalanche.<br>D = Duty cycle in avalanche =  tav ·f<br>ZthJC(D, tav) = Transient thermal resistance, see Figures 13)<br>E LENAana’<br>0<br>PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) = ; T/ ZthJCthJC<br>25 50 75 100 125 150 175<br>Iav =av == 2 A T/ [1.3·BV·Zth]th]]<br>Starting TJ , Junction Temperature (°C) EAS (AR) = PD (ave)·tavAS (AR) = PD (ave)·tav = PD (ave)·tavD (ave)·tav·tavav<br>EAR , Avalanche Energy (mJ)<br> thJC ) °C/W<br>Thermal Response ( Z<br>Avalanche Current (A)<br>**----- End of picture text -----**<br>


- Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type. 

2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded. 

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 

4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse. 

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 

7. ∆T = Allowable rise in junction temperature, not to exceed∆T = Allowable rise in junction temperature, not to exceedT = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as 25°C in Figure 14, 15). 

**PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) =** ; **T/ ZthJCthJC Iav =av == 2** A **T/ [1.3·BV·Zth]th]] EAS (AR) = PD (ave)·tavAS (AR) = PD (ave)·tav = PD (ave)·tavD (ave)·tav·tavav** 

**Fig 15.** Maximum Avalanche Energy vs. Temperature 

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4.0<br>P mtft tt fy ty<br>3.5<br>3.0<br>SC ONSTS ANPRC EL<br>2.5 P t tT | ARAN<br>ID = 250µA Z\|__N<br>2.0 ID = 1.0mA UNNI<br>rT oIN WEL<br>ID = 1.0A<br>1.5<br>FANN<br>1.0<br>S ee<br>0.5 Pott tt | |<br>-75 -50 -25 0 25 50 75 100 125 150 175 200<br>TJ , Temperature ( °C )<br>VGS(th), Gate threshold Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 16.** Threshold Voltage vs. Temperature 

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30<br>IF = 108A<br>VR = 64V<br>25<br>TJ = 25°C<br>TJ = 125° C<br>Bea<br>20 A<br>15<br>A Via<br>10<br>5<br>0 200 400 600 800 1000<br>diF /dt (A/µs)<br>IRR (A)<br>**----- End of picture text -----**<br>


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30<br>IF = 72A<br>VR = 64V<br>25<br>TJ = 25°C<br>TJ = 125° C<br>fa |e<br>20<br>x<br>n e<br>15 "<br>10<br>A | |<br>5 Af | |<br>0 200 400 600 800 1000<br>diF /dt (A/µs)<br>Fig. 17 - Typical Recovery Current vs. di;/dt<br>1000<br>920 IF = 72A<br>VR = 64V a<br>840<br>TJ = 25°C Pt<br>760 T J = 125° C<br>a<br>680 s/n<br>600<br>520<br>T Z<br>440 = o<br>360 p oetA _<br>280<br>r e<br>200<br>0 200 400 600 800 1000<br>diF /dt (A/µs)<br>IRR (A)<br>QRR (A)<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
1000<br>920 IF = 108A |<br>VR = 64V a<br>840 a ed<br>TJ = 25°C oi<br>760 T J = 125° C<br>680<br>re peee |<br>600<br>p ot<br>520<br>440 p ot<br>360 e e ee<br>a e<br>280<br>200 Pp? tT |ht<br>0 200 400 600 800 1000<br>diF /dt (A/µs)<br>QRR (A)<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Driver Gate Drive<br>P.W.<br>Period D =<br>D.U.T + [{ P.W. n d — Period<br>) [©)]    •  Circuit Layout Considerations lt V | GS=10V<br> •<br>| —| - LowGround Stray Pla I n eductance<br> •   Low Leakage Inductance 2) D.U.T. ISD Waveform<br>+<br>Reverse<br>Recovery Body Diode Forward<br>oH - [1] Current Transformer - ® + Current r Current di/dt NN<br>1) D.U.T. VDS Waveform Diode Recoverydv/dt ‘<br>00 = VDD<br>ma<br>•   Re-Applied<br>•   Driver same type as D.U.T. + Voltage Body Diode  Forward Drop<br>Re ( aA •   dv/dt controlled by Rg Vpp -<br>•<br>D.U.T. - Device Under Test er ae<br>Isp controlled by Duty Factor "D" @ t Ripple  ≤ 5% ISD<br>* Veg = 5V for Logic Level Devices<br>Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel<br>HEXFET ® Power MOSFETs<br>V(BR)DSS<br>15V < tp ><br>VDS L DRIVER<br>RG D.U.T +<br>- [V][DD]<br>IAS A<br>20VVGS<br>tp 0.01Ω IAS<br>**----- End of picture text -----**<br>


**Fig 21a.** Unclamped Inductive Test Circuit 

**Fig 21b.** Unclamped Inductive Waveforms 

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**----- Start of picture text -----**<br>
LD<br>VDS<br>+<br>VDD -<br>D.U.T<br>VGS<br>Pulse Width < 1µs<br>Duty Factor < 0.1%<br>Fig 22a.   Switching Time Test Circuit<br>L<br>VCC<br>DUT<br>0<br>1K<br>a:<br>**----- End of picture text -----**<br>


**Fig 22a.** Switching Time Test Circuit 

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**----- Start of picture text -----**<br>
V<br>DS<br>90%<br>10%<br>V<br>GS<br>1<br>yay<br>td(on) tr td(off) tf<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Fig 22b.   Switching Time Waveforms<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Id<br>Vds<br>Vgs<br>Vgs(th)<br>Qgs1 l ey! Qgs2 Qgd Qgodr<br>**----- End of picture text -----**<br>


**Fig 23b.** Gate Charge Waveform 

**Fig 23a.** Gate Charge Test Circuit 

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TO-247AC package is not recommended for Surface Mount Application. 

Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. 

**IR WORLD HEADQUARTERS:** 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information **.** 06/08 

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8 

## **IMPORTANT NOTICE** 

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) . 

With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. 

In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. 

The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. 

For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office ( **www.infineon.com** ). 

## **WARNINGS** 

Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. 

Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. 



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---

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