# Power MOSFET, N Channel, 100 V, 2.3 A, 0.2 ohm, SOT-223, Surface Mount

![Product image](https://novapart.co/image/farnell:2453922RL/)

**URL**: https://novapart.co/products/IRFM120ATF/power-mosfet-n-channel-100-v-23-a-02-ohm-sot-223
**SKU**: IRFM120ATF
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.2430
**Stock**: 200+
**Lead Time**: 2 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:2.3A; Drain Source Voltage Vds:100V; On Resistance Rds(on):0.2ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; P

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 2.4W |
| Transistor Mounting | Surface Mount |
| Transistor Polarity | N Channel |
| Power Dissipation Pd | 2.4W |
| Rds(On) Test Voltage | 10V |
| On Resistance Rds(On) | 0.2ohm |
| Transistor Case Style | SOT-223 |
| Drain Source Voltage Vds | 100V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 2.3A |
| Drain Source On State Resistance | 0.2ohm |
| Automotive Qualification Standard | - |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2453922RL/)

**IRFM120A** 

**Advanced  Power  MOSFET** 

## **IEEE802.3af Compatible** 

## **FEATURES** 

- ! Avalanche  Rugged  Technology 

- ! Rugged  Gate  Oxide  Technology 

- ! Lower  Input  Capacitance 

- ! Improved  Gate  Charge 

- ! Extended  Safe  Operating  Area 

- ! Lower  Leakage  Current  :  10 #A (Max.)  @  VDS = 100V 

- ! Lower  RDS(ON) :  0.155 ! (Typ.) 

**==> picture [86 x 124] intentionally omitted <==**

**----- Start of picture text -----**<br>
BVDSS =  100 V<br>R =  0.2 !<br>DS(on)<br>ID =  2.3 A<br>SOT-223<br>2<br>1<br>3<br>**----- End of picture text -----**<br>


**1. Gate  2. Drain  3. Source** 

## **Absolute  Maximum  Ratings** 

**==> picture [407 x 229] intentionally omitted <==**

**----- Start of picture text -----**<br>
a Symbol Ge Characteristic Value Units<br>VDSS Drain-to-Source Voltage 100 V<br>a ID  ee Continuous  Drain  Current  (TContinuous  Drain  Current  (TAA=25=70%%)) 1.842.3 A<br>a IDM Drain  Current-Pulsed                              & eee 18 ee A<br>a VGS a Gate-to-Source  Voltage "20 V<br>a EAS Single  Pulsed  Avalanche  Energy          ' 123 mJ<br>a IAR Avalanche  Current                                  & 2.3 A<br>a EAR DG Repetitive  Avalanche  Energy                 & 0.24 mJ<br>dv/dt Peak  Diode  Recovery dv/dt                ( 6.5 V/ns<br>PD LinearTotal  Power  Dissipation  (TDerating  Factor * A=25%) * 0.0192.4 W/W%<br>a ee ee ee<br>Operating  Junction  and<br>TJ  , TSTG Storage  Temperature  Range - 55  to  +150<br>%<br>Maximum  Lead  Temp.  for  Soldering<br>TL Purposes,  1/8” from  case  for  5-seconds 300<br>**----- End of picture text -----**<br>


## **Thermal  Resistance** 

|R$JA<br>**Symbol**|Junction-to-Ambient<br>**Characteristic**<br>*|--<br>**Typ.**|52<br>**Max.**|%/W<br>**Units**|
|---|---|---|---|---|



* When  mounted  on  the  minimum  pad  size  recommended (PCB  Mount). 

Rev. C 

**N-CHANNEL POWER MOSFET** 

**IRFM120A** 

## **Electrical Characteristics** (TA=25% unless  otherwise  specified) 

|**Electrical Characteristics**(TA=25%A=25%=25%% unless  otherwise  specified)<br>a|**Electrical Characteristics**(TA=25%A=25%=25%% unless  otherwise  specified)<br>a|**Electrical Characteristics**(TA=25%A=25%=25%% unless  otherwise  specified)<br>a|**Electrical Characteristics**(TA=25%A=25%=25%% unless  otherwise  specified)<br>a|**Electrical Characteristics**(TA=25%A=25%=25%% unless  otherwise  specified)<br>a|**Electrical Characteristics**(TA=25%A=25%=25%% unless  otherwise  specified)<br>a|**Electrical Characteristics**(TA=25%A=25%=25%% unless  otherwise  specified)<br>a|
|---|---|---|---|---|---|---|
|**Characteristic**<br>**Symbol**<br>**Max. Units**<br>**Typ.**<br>**Min.**<br>**Test  Condition**<br>a|||||||
|BVDSS<br>a<br>aOO|Drain-Source  Breakdown  Voltage<br>OO|100<br>OO|--<br>OO|--<br>OO|V<br>OO|VGS=0V,ID=250#A<br>OO|
|.BV/.TJ<br>LO|Drain-Source  Breakdown  Voltage<br>Breakdown  Voltage  Temp. Coeff.<br>LO|--<br>LO|0.12<br>LO|--<br>LO|V/%<br>LO|ID=250#A**_See Fig 7_**<br>LO|
|VGS(th)<br>LO|Gate  Threshold  Voltage<br>LO<br>ee|2.0<br>LO<br>ee<br>|--<br>LO<br>ee<br>|4.0<br>LO<br>ee<br>|V<br>LO<br><br>|VDS=5V,ID=250#A<br>LO<br>ee<br>|
|IGSS<br>ee|Gate-Source  Leakage ,  Forward<br>ee<br>ee|--<br>ee<br>ee<br>|--<br>ee<br>ee<br>|100<br>ee<br>ee<br>|nA<br>ee<br><br>|VGS=20V<br>ee<br>ee<br>|
||Gate-Source  Leakage ,  Forward<br>Gate-Source  Leakage ,  Reverse<br>ee<br>ee|--<br>ee<br>ee<br>|--<br>ee<br>ee<br>|-100<br>ee<br>ee<br>||VGS=-20V<br>ee<br>ee<br>|
|IDSS|Drain-to-Source  Leakage  Current<br>eeOe|--<br>ee<br>Oe|--<br>ee<br>Oe|1<br>ee <br>Oe|#A<br> <br>|VDS=30V-<br> ee<br>|
|||--<br>|--<br>|10<br>||VDS=100V<br>|
|||--<br>|--<br>|100<br>||VDS=80V,TA=125%<br> po|
|RDS(on)|Static  Drain-Source<br>On-State  Resistance|--|--|0.2|)|VGS=10V,ID=1.15A+|
|gfs<br>a|Forward  Transconductance<br>OO|--<br>OO|3.12<br>OO|--<br>OO|S<br>OO|VDS=40V,ID=1.15A<br>+<br>OO|
|Ciss<br>Coss<br>a<br>Ls|Input  Capacitance<br>Output  Capacitance<br>|--<br>--<br>|95<br>370<br>|480<br>110<br>|pF|VGS=0V,VDS=25V,f =1MHz<br>**_See Fig 5_**|
|Crss<br>LsLO|Reverse  Transfer  Capacitance<br>LO|--<br>LO|38<br>LO|45<br>LO|||
|td(on)<br>a|Turn-On  Delay  Time<br>|--<br>|14<br>|40<br>|ns|VDD=50V,ID=9.2A,<br>RG=18)<br>**_See Fig 13_**+ ,|
|d(on)<br>tr<br>LO|Rise  Time<br>LO|--<br>LO|14<br>LO|40<br>LO|||
|td(off)<br>aOe|Turn-Off  Delay  Time<br>Oe|--<br>Oe|36<br>Oe|90<br>Oe|||
|d(off)<br>tf<br>a|Fall  Time<br>a|--|28|70|||
|Qg<br>a|Total  Gate  Charge<br>a|--|16|22|nC|VDS=80V,VGS=10V,<br>ID=9.2A<br>**_See Fig 6 & Fig 12_**+ ,|
|g<br>Qgs<br>a|Gate-Source  Charge<br>a|--|2.7|--|||
|gs<br>Qgd|Gate-Drain(“Miller”)  Charge|--|7.8|--|||



## **Source-Drain  Diode  Ratings  and  Characteristics** 

|**Symbol**|**Characteristic**|**Min.**|**Typ.**|**Max. **|**Units**|**Test  Condition**|
|---|---|---|---|---|---|---|
|IS|Continuous  Source  Current|--|--|2.3|A|Integral reverse pn-diode<br>in the MOSFET|
|ISM|Pulsed-Source  Current&|--|--|18|||
|VSD|Diode  Forward  Voltage+|--|--|1.5|V|TJ=25%,IS=2.3A,VGS=0V|
|trr|Reverse  Recovery  Time|--|98|--|ns|TJ=25%,IF=9.2A<br>diF/dt=100A/#s+|
|Qrr|Reverse  Recovery  Charge|--|0.34|--|#C||



## **Notes ;** 

- & Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature 

- ' L=35mH, IAS=2.3A, VDD=25V, RG=27), Starting TJ =25% 

- ( ISD*9.2A, di/dt*300A/#s, VDD*BVDSS , Starting TJ =25% 

- + Pulse Test : Pulse Width = 250#s, Duty Cycle * 2% 

- , Essentially Independent of Operating Temperature 

- Adjusted for Cisco 

**N-CHANNEL POWER MOSFET** 

**IRFM120A** 

**==> picture [428 x 531] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig 1.  Output Characteristics Fig 2.  Transfer Characteristics<br>                     VGS<br>Top  :          1 5 V<br>                    1 0 V<br>                   8.0 V<br>10 [1]                    7.0 V 10 [1]<br>                   6.0 V<br>                   5.5 V<br>                   5.0 V<br>Bottom  :  4.5 V<br>150 oC<br>10 [0]<br>10 [0] 25 oC @ Notes :<br>L— i f   1. VGS = 0 V<br>@ Notes :  1. 250   2. TA = 25  " s Pulse TestoC - 55 oC   2. V  3. 250 DS = 40 V " s Pulse Test<br>P TT) 10 [-1] U b—<br>10 [-1] 10 [0] 10 [1] 2 4 6 8 10<br>VDS , Drain-Source Voltage  [V] VGS , Gate-Source Voltage  [V]<br>Fig 3.  On-Resistance vs. Drain Current  Fig 4.  Source-Drain Diode Forward Voltage<br>0.4<br>10 [1]<br>0.3 VGS = 10 V<br>ane anne<br>0.2<br>10 [0]<br>VGS = 20 V<br>0.1<br>@ Notes :<br>150 oC   1. VGS = 0 V<br>@ Note : TJ = 25  [o] C 25 oC   2. 250  " s Pulse Test<br>0.0 10 [-1] H ii<br>0 10 20 30 40 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2<br>ID , Drain Current  [A] VSD , Source-Drain Voltage  [V]<br>Fig 5.  Capacitance vs. Drain-Source Voltage Fig 6.  Gate Charge vs. Gate-Source Voltage<br>600<br>Ciss= Cgs+ Cgd ( Cds= shorted )<br>C iss Coss= Cds+ Cgd 10 VDS = 20 V<br>Crss= Cgd VDS = 50 V<br>400 VDS = 80 V<br>C oss<br>5<br>@ Notes :<br>200 C rss   1. V  2. f = 1 MHzGS = 0 V<br>@ Notes : ID = 9.2 A<br>0 = 0<br>10 [0] 10 [1] 0 5 10 15 20<br>VDS , Drain-Source Voltage [V] QG , Total Gate Charge  [nC]<br> , Drain Current  [A]ID  , Drain Current  [A]ID<br>]<br>#<br> , [<br>DS(on)<br>R<br>Drain-Source On-Resistance  , Reverse Drain Current  [A]<br>DR<br>I<br>Capacitance  [pF]<br> , Gate-Source Voltage  [V]<br>GS<br>V<br>**----- End of picture text -----**<br>


**N-CHANNEL POWER MOSFET** 

**IRFM120A** 

**==> picture [437 x 530] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig 7.  Breakdown Voltage vs. Temperature Fig 8.  On-Resistance vs. Temperature<br>1.2 3.0<br>2.5<br>1.1<br>2.0<br>1.0 1.5<br>1.0<br>0.9 @ Notes : @ Notes :<br>  1. VGS = 0 V 0.5   1. VGS = 10 V<br>  2. ID = 250  " A   2. ID = 4.6 A<br>0.8 0.0<br>-75 -50 -25 0 25 50 75 100 125 150 175 -75 -50 -25 0 25 50 75 100 125 150 175<br>TJ , Junction Temperature  [ [o] C] TJ , Junction Temperature  [ [o] C]<br>Fig 9.  Max. Safe Operating Area  Fig 10.  Max. Drain Current vs. Ambient Temperature<br>2.5<br>10 [2] Poe Dee<br>Operation in This Area<br>is Limited by R DS(on) 2.0<br>10 [1] 100  " s 10  " s<br>1 ms 1.5<br>10 ms<br>100 ms<br>10 [0]<br>DC 1.0<br>@ Notes :<br>10 [-1]   1. TA = 25  [o] C 0.5<br>  2. TJ = 150  [o] C<br>  3. Single Pulse<br>10 [-2] a S 0.0 NN<br>10 [-1] 10 [0] 10 [1] 10 [2] 25 50 75 100 125 150<br>SS Ea<br>VDS , Drain-Source Voltage  [V] TA , Ambient Temperature  [ [o] C]<br>Fig 11.  Thermal Response<br>10 [2]<br>D=0.5<br>10 [1] 0.2<br>0.1 Bef LSS @ Notes :  1. Z ! JA(t)=52 oC/W Max.<br>0.05   2. Duty Factor, D=t1/t2<br>0.02   3. TJM-TA=PDM*Z ! JA(t)<br>10 [0]<br>0.01 => SP [gl] [err.] BlBe<br>PDM<br>t1<br>single pulse t2<br>10 [-1] ceie<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1] 10 [2] 10 [3]<br>t1 , Square Wave Pulse Duration  [sec]<br> , (Normalized)  , (Normalized)<br>DSS<br>BV DS(on)<br>R<br>Drain-Source On-Resistance<br>Drain-Source Breakdown Voltage<br> , Drain Current  [A]ID  , Drain Current  [A]ID<br>(t) ,  Thermal Response<br>! JA<br>Z<br>**----- End of picture text -----**<br>


**N-CHANNEL POWER MOSFET** 

**IRFM120A** 

**Fig 12.  Gate Charge Test Circuit  &  Waveform** 

**==> picture [437 x 515] intentionally omitted <==**

**----- Start of picture text -----**<br>
* Current Regulator ”<br>Same Type VGS<br>50K ! as DUT<br>Qg<br>12V 200nF<br>300nF 10V<br>VDS<br>VGS Qgs Qgd<br>DUT<br>3mA<br>R1 R2<br>a | |<br>Charge<br>Current Sampling (IG) Current Sampling (ID)<br>Resistor Resistor<br>Fig 13.  Resistive Switching Test Circuit  &  Waveforms<br>RL<br>Vout Vout 90%<br>Vin VDD<br>( 0.5 rated VDS )<br>RG<br>DUT<br>10%<br>Vin<br>10V<br>td(on) tr td(off) tf<br>eS oe t on t off<br>Fig 14.  Unclamped Inductive Switching Test Circuit  &  Waveforms<br>VDS LL EAS = ----12 LL IAS2 --------------------BVBVDSS -- VDSS DD<br>Vary tp to obtain ID BVDSS<br>required peak ID of IAS So<br>RG C VDD ID (t)<br>DUT<br>VDD VDS (t)<br>10V<br>ei t p ma—— t p ——e l| Time<br>**----- End of picture text -----**<br>


**N-CHANNEL POWER MOSFET** 

**IRFM120A** 

## **Fig 15.  Peak Diode Recovery dv/dt Test Circuit  &  Waveforms** 

**==> picture [304 x 474] intentionally omitted <==**

**----- Start of picture text -----**<br>
DUT +<br>VDS<br>--<br>I S<br>L<br>Driver<br>VGS<br>RG Same Type as DUT VDD<br>VGS • dv/dt controlled by  / G<br>• IS controlled by Duty Factor  0 ?<br>Gate Pulse Width<br>VGS D = --------------------------Gate Pulse Period 10V<br>( Driver )<br>ff<br>IFM , Body Diode Forward Current<br>I S<br>( DUT ) di/dt<br>IRM<br>Yo N e<br>Body Diode Reverse Current<br>VDS<br>( DUT ) Body Diode Recovery dv/dt<br>Ne<br>Vf VDD<br>$ t<br>Body Diode<br>Forward Voltage Drop<br>**----- End of picture text -----**<br>


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TRADEMARKS<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is<br>not intended to be an exhaustive list of all such trademarks.<br>ACEx™ FACT™ ImpliedDisconnect™ PACMAN™ SPM™<br>ActiveArray™ FACT Quiet Series™ ISOPLANAR™ POP™ Stealth™<br>Bottomless™ FAST® LittlkeFET™ Power247™ SuperSOT™-3<br>CoolFET™ FASTr™ MicroFET™ PowerTrench® SuperSOT™-6<br>CROSSVOLT™ FRFET™ MicroPak™ QFET™ SuperSOT ™-8<br>DOME™ GlobalOptoisolator™ MICROWIRE™ qas™ SyncFET™<br>EcoSPARK™ GTOo™ MSX™ QT Optoelectronics™ TinyLogic™<br>E?CMOS™ HiSeC™ MSXPro™ Quiet Series™ TruTranslation™<br>EnSigna™ 2co™ OCX™ RapidConfigure™ UHC™<br>Across the board. Around the world.™ OCXPro™ RapidConnect™ UltraFET®<br>The Power Franchise™ OPTOLOGIC® SILENT SWITCHER® VCX™<br>Programmable Active Droop™ OPTOPLANAR™ SMART START™<br>DISCLAIMER<br>FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER<br>NOTICE TOANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD<br>DOES NOTASSUMEANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT<br>OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT<br>RIGHTS, NOR THE RIGHTS OF OTHERS.<br>LIFE SUPPORT POLICY<br>FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT<br>DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTENAPPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.<br>As used herein:<br>1. Life support devices or systems are devices or 2. A critical component is any component of a life<br>systems which, (a) are intended for surgical implant into support device or system whose failure to perform can<br>the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life<br>failure to perform when properly used in accordance support device or system, or to affect its safety or<br>with instructions for use provided in the labeling, can be effectiveness.<br>reasonably expected to result in significant injury to the<br>user.<br>PRODUCT STATUS DEFINITIONS<br>Definition of Terms<br>Advance Information Formative or This datasheet contains the design specifications for<br>In Design product development. Specifications may change in<br>any manner without notice.<br>Preliminary First Production This datasheet contains preliminary data, and<br>supplementary data will be published at a later date.<br>Fairchild Semiconductor reserves the right to make<br>changes at any time without notice in order to improve<br>design.<br>No Identification Needed Full Production This datasheet contains final specifications. Fairchild<br>Semiconductor reserves the right to make changes at<br>any time without notice in order to improve design.<br>Obsolete Not In Production This datasheet contains specifications on a product<br>that has been discontinued by Fairchild semiconductor.<br>The datasheet is printed for reference information only.<br>Rev. I1<br>**----- End of picture text -----**<br>




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