# Power MOSFET, N Channel, 200 V, 25 A, 0.0725 ohm, TO-220AB, Through Hole

![Product image](https://novapart.co/image/farnell:1704511/)

**URL**: https://novapart.co/products/IRFB5620PBF/power-mosfet-n-channel-200-v-25-a-00725-ohm-to
**SKU**: IRFB5620PBF
**Manufacturer**: INFINEON
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.6320
**Stock**: 500+
**Lead Time**: 2 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:25A; Drain Source Voltage Vds:200V; On Resistance Rds(on):0.06ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:5V; Power

## Specifications

| Parameter | Value |
|---|---|
| Msl | - |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 144W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-220AB |
| Drain Source Voltage Vds | 200V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 25A |
| Drain Source On State Resistance | 0.0725ohm |
| Gate Source Threshold Voltage Max | 5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:1704511/)

## IRFB5620PbF 

## **Features** 

- Key Parameters Optimized for Class-D Audio Amplifier Applications 

- Low RDSON for Improved Efficiency 

- Low QG and QSW for Better THD and Improved Efficiency 

- Low QRR for Better THD and Lower EMI 

## **Key Parameters** 

|**Key Parametersy Parameters Parameters**|**Key Parametersy Parameters Parameters**|**Key Parametersy Parameters Parameters**|
|---|---|---|
|VDS|200<br>~~ee~~|V<br>~~ee~~|
|RDS(ON)typ. @ 10V|60<br>~~ee~~|m<br>~~ee~~<br>~~ee~~|
|Qgtyp.|25<br>~~ee ~~<br>~~ee~~|nC<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|Qswtyp.|9.8<br>~~ee~~|nC<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|RG(int)typ.|2.6<br>~~ee~~<br>~~ee~~|Ω<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|TJmax|175<br>~~ee~~|°C<br>~~ee~~<br>~~ee~~<br>~~ee~~|



- 175°C Operating Junction Temperature for 

- Ruggedness 

- Can Deliver up to 300W per Channel into Ω oad in 

- Half-Bridge Configuration Amplifier 

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D<br>D<br>G<br>S<br>D<br>G<br>S<br>TO-220AB<br>G D S<br>Gate Drain Source<br>**----- End of picture text -----**<br>


## **Description** 

This Digital Audio MOSFET is specifically designed for Class-D audio amplifier applications. This MOSFET utilizes the latest processing techniques to achieve low on-resistance per silicon area. Furthermore, Gate charge, body-diode reverse recovery and internal Gate resistance are optimized to improve key Class-D audio amplifier performance factors such as efficiency, THD and EMI. Additional features of this MOSFET are 175°C operating junction temperature and repetitive avalanche capability. These features combine to make this MOSFET a highly efficient, robust and reliable device for ClassD audio amplifier applications. 

## **Absolute Maximum Ratings** 

||**Parameter**|**Max.**|**Units**|
|---|---|---|---|
|VDS|Drain-to-Source Voltage<br>~~a~~<br>~~ee~~|200<br>~~a~~<br>~~ee~~|V<br>~~ee~~<br>~~ne~~|
|VGS|Gate-to-Source Voltage<br>~~ee~~<br>~~es~~|±20<br>~~ee~~<br>~~ne~~||
|ID@ TC= 25°C|Continuous Drain Current, VGS@ 10V<br>~~ee~~<br>~~es~~<br>~~es~~|25<br>~~ee~~<br>~~es~~<br>~~ne~~|A<br>~~ee~~<br>~~ne~~|
|ID@ TC= 100°C|Continuous Drain Current, VGS@ 10V<br>~~es~~<br>~~es~~|18<br>~~es~~<br>~~ne~~||
|IDM<br>~~a~~|Pulsed Drain Current<br>~~es~~<br>~~a~~<br>~~so~~|100<br>~~ne~~||
|PD@TC= 25°C<br>~~a~~|Power Dissipation<br>~~es~~<br>~~a~~<br>~~so~~|144<br>~~ne~~|W<br>~~ne~~|
|PD@TC= 100°C<br>~~a~~|Power Dissipation<br>~~a~~<br>~~so~~|72||
||Linear DeratingFactor<br>~~so~~|0.96|W/°C|
|TJ<br>TSTG|Operating Junction and<br>Storage Temperature Range|-55  to + 175|°C<br>~~_~~|
||Soldering Temperature, for 10 seconds<br>(1.6mm from case)|300||
||Mountingtorque,6-32 or M3 screw<br>~~es~~|10lb n(1.1N m)<br>~~es~~|~~_~~<br>~~es~~|



> Notes ® hrough ©) are on page 2 

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**Electrical Characteristics @ TJ = 25°C (unless otherwise specified)** 

||**Parameter**|**Min.**|**Typ.**|**Max. **|**Units**|**Conditions**|
|---|---|---|---|---|---|---|
|BVDSS<br>~~Pp~~|Drain-to-Source Breakdown Voltage<br>~~Pp~~|200|–––<br>~~GO~~|–––<br>~~GO G~~|V<br>~~G~~|VGS= 0V, ID= 250µA<br>~~GQ~~|
|∆ΒVDSS/∆TJ<br>~~Pp~~|Breakdown Voltage Temp. Coefficient<br>~~ee~~<br>~~Pp~~<br>~~rr—“—t‘is‘“s‘“‘“‘i‘“iP~~|–––<br>~~ee~~<br>~~rr—“—t‘is‘“s‘“‘“‘i‘“iPrl~~|0.22<br>~~ee~~<br>~~GO~~<br>~~rl~~|–––<br>~~ee~~<br>~~GO G~~<br>~~rl~~|V/°C<br>~~ee~~<br>~~G~~<br>~~rl~~|Reference to 25°C, ID= 1mA<br>~~ee~~<br>~~GQ~~|
|RDS(on)<br>~~Pp~~|Static Drain-to-Source On-Resistance<br>~~ee~~<br>~~Pp~~<br>~~rr—“—t‘is‘“s‘“‘“‘i‘“iP~~<br>~~ee~~|–––<br>~~ee~~<br>~~rr—“—t‘is‘“s‘“‘“‘i‘“iPrl~~<br>~~ee~~|60<br>~~ee~~<br>~~GO~~<br>~~rl~~<br>~~ee~~|72.5<br>~~ee~~<br>~~GO G~~<br>~~rl~~|mΩ<br>~~ee~~<br>~~G~~<br>~~rl~~|VGS= 10V, ID= 15A<br>~~ee~~<br>~~GQ~~|
|VGS(th)<br>~~Pp~~|Gate Threshold Voltage<br>~~Pp~~<br>~~rr—“—t‘is‘“s‘“‘“‘i‘“iP~~<br>~~ee~~|3.0<br>~~rr—“—t‘is‘“s‘“‘“‘i‘“iP rl~~<br>~~ee~~|–––<br>~~GO~~<br>~~rl~~<br>~~ee~~|5.0<br>~~GO G~~<br>~~rl~~|V<br>~~G~~<br>~~rl~~|VDS= VGS, ID= 100µA<br>~~GQ~~<br>~~|~~|
|∆VGS(th)/∆TJ|Gate Threshold Voltage Coefficient<br>~~ee~~<br><br>~~a~~|–––<br>~~ee~~<br>~~**|**~~<br>|-14<br>~~ee~~<br>~~**|**~~<br>|–––<br>|mV/°C<br>||
|IDSS|Drain-to-Source Leakage Current<br>~~ee ~~<br>~~OE~~<br>~~a~~|–––<br> ~~ee~~<br>~~**|**~~<br>~~OE~~|–––<br>~~ee~~<br>~~**|**~~<br>~~OE~~|20<br>~~OE~~|µA<br>~~OE~~|VDS= 200V, VGS= 0V<br>~~OE|~~|
|||–––<br>~~**|**~~<br>~~OE~~|–––<br>~~**|**~~<br>~~OE~~|250<br>~~OE~~||VDS= 200V, VGS= 0V, TJ= 125°C<br>~~OE|~~|
|IGSS|Gate-to-Source Forward Leakage<br>~~OE~~<br>~~a~~|–––<br>~~OE~~|–––<br>~~OE~~<br>~~a~~|100<br>~~OE~~|nA<br>~~OE~~|VGS= 20V<br>~~OE|~~|
||Gate-to-Source Reverse Leakage<br><br>~~a~~|–––<br><br>~~a~~|–––<br><br>~~a~~<br>~~a~~|-100<br><br>~~a~~||VGS= -20V<br>~~|~~|
|gfs|Forward Transconductance<br><br>~~a~~<br>~~eG~~|37<br><br>~~a~~<br>~~eG~~|–––<br><br>~~a~~<br>~~a~~<br>~~eG~~|–––<br><br>~~a~~<br>~~eG~~|S<br><br>~~GQ~~|VDS= 50V, ID= 15A<br>~~|~~<br>~~GQ~~|
|Qg|Total Gate Charge<br>~~eG~~<br>~~a~~|–––<br>~~eG~~<br>~~a~~<br>~~ee~~|25<br>~~eG~~<br>~~a~~|38<br>~~eG ~~<br>~~a~~|nC<br> ~~GQ~~<br>~~GN~~|See Fig. 6 and 19<br>VGS= 10V<br>ID= 15A<br>VDS= 100V<br>~~GQ~~|
|Qgs1|Pre-Vth Gate-to-Source Charge<br>~~es~~|–––<br>~~es~~<br>~~ee~~|6.3<br>~~es~~|–––<br>~~es~~|||
|Qgs2|Post-Vth Gate-to-Source Charge<br>~~ee~~|–––<br>~~ee~~<br>~~ee~~|1.9<br>~~ee~~|–––<br>~~ee~~|||
|Qgd|Gate-to-Drain Charge|–––|7.9|–––|||
|Qgodr|Gate Charge Overdrive<br>~~ee~~|–––<br>~~ee~~<br>~~ee~~|9.3<br>~~ee~~|–––<br>~~ee~~|||
|Qsw|Switch Charge (Qgs2+ Qgd)<br>~~es~~<br>~~es~~|–––<br>~~es~~<br>~~ee~~<br>|9.8<br>~~es~~|–––<br>~~es~~|||
|RG(int)|Internal Gate Resistance<br>~~Gs~~<br>~~es~~|–––<br>~~ee~~<br>~~Gs~~<br>~~ee~~|2.6<br>~~Gs~~|5.0<br>~~Gs~~|Ω<br>~~Gs~~<br>~~GN~~|~~Gs~~<br>@|
|td(on)|Turn-On DelayTime<br>~~es~~|–––<br>~~ee~~|8.6|–––|ns<br>~~GN~~|ID= 15A<br>RG= 2.4Ω<br>VDD= 100V, VGS= 10V<br>@|
|tr|Rise Time<br>~~es ~~<br>~~ee~~|–––<br> ~~ee~~<br>~~ee~~|14.6<br>~~ee~~|–––<br>~~ee~~|||
|td(off)|Turn-Off DelayTime|–––|17.1|–––|||
|tf|Fall Time<br>~~es~~|–––<br>~~es~~|9.9<br>~~es~~|–––<br>~~es~~|||
|Ciss|Input Capacitance<br>~~es~~<br>~~es~~|–––<br>~~es~~<br>~~es~~|1710<br>~~es~~<br>~~es~~|–––<br>~~es~~<br>~~es~~|pF<br>~~————+4,]~~|ƒ= 1.0MHz,          See Fig.5<br>VGS= 0V<br>VDS= 50V|
|Coss|Output Capacitance<br>~~ee~~|–––<br>~~ee~~|125<br>~~ee~~|–––<br>~~ee~~|||
|Crss|Reverse Transfer Capacitance|–––|30|–––|||
|Coss|Effective Output Capacitance<br>~~es~~<br>~~————+4,]~~|–––<br>~~es~~<br>~~————+4,]~~|138<br>~~es~~<br>~~————+4,]~~|–––<br>~~es~~<br>~~————+4,]~~||VGS= 0V, VDS= 0V to 160V<br>~~————+4,]~~<br>~~«&~~|
|LD|Internal Drain Inductance<br>~~es~~<br>~~————+4,]~~|–––<br>~~es~~<br>~~————+4,]~~|4.5<br>~~es~~<br>~~————+4,]~~|–––<br>~~es~~<br>~~————+4,]~~|nH<br>~~————+4,]~~|S<br>D<br>G<br>Between  lead,<br>6mm (0.25in.)<br>from package<br>and center of die contact<br>~~————+4,]~~<br>~~«&~~|
|LS|Internal Source Inductance<br>~~————+4,]~~|–––<br>~~————+4,]~~|7.5<br>~~————+4,]~~|–––<br>~~————+4,]~~|||



> ~~a~~ Repetitive rating;  pulse width limited by max. junction temperature. ~~5~~ Rθ is measured at TJ of approximately 90°C. ~~@~~ Starting TJ = 25°C, L = 1.00mH, RG = 25Ω, IAS = 15A. © Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive 6) Pulse width ≤ 400µs; duty cycle ≤ 2%. avalanche information 

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1000<br>VGS<br>TOP           15V<br>12V<br>100 10V8.0V<br>7.0V<br>6.0V<br>5.5V<br>10 BOTTOM 5.0V<br>1<br>os 5.0V 7 =<br>0.1<br>≤60µs PULSE WIDTH<br>Tj = 25°C<br>0.01 P| mail<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 1.   Typical Output Characteristics<br>1000<br>a ee ee ee ee ee<br>100<br>e TJ = 175°C e ee<br>Fy n Uf/a<br>10 s /o<br>a pee TJ = 25°C<br>on<br>1 i<br>4 VDS = 50V<br>0.1 P AP,E ≤60µs PULSE WIDTH EY<br>2 4 6 8 10 12 14 16<br>VGS, Gate-to-Source Voltage (V)<br>Fig 3.   Typical Transfer Characteristics<br>100000<br>VGS   = 0V,       f = 1 MHZ<br>Ciss   = C gs + Cgd,  C ds SHORTED<br>C  = C<br>rss   gd<br>C = C + C<br>10000 oss   ds  gd<br>a<br>1000 Ciss LUTI<br>SNOT Coss EAI ETH<br>100 N UM SS<br>C<br>rss<br>PI<br>10<br>1 10 100 1000<br>VDS, Drain-to-Source Voltage (V)<br>ID, Drain-to-Source Current (A)<br>C, Capacitance (pF)<br>ID, Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 5.** Typical Capacitance vs.Drain-to-Source Voltage 

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1000<br>VGS<br>TOP           15V<br>12V<br>10V<br>8.0V<br>100 7.0V<br>6.0V<br>5.5V<br>BOTTOM 5.0V<br>10<br>5.0V<br>Z<br>1<br>≤60µs PULSE WIDTH<br>0.1 eR elie Tj = 175°C ill<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>ID, Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 2.** Typical Output Characteristics 

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3.5<br>ID = 15A<br>3.0 V GS = 10V Tey<br>2.5<br>P ETE<br>Sea eeeeeeen<br>T_T TTT] A<br>2.0 S GSeeRRe?Y/<br>1.5 P EPE<br>455<br>Seeger denen<br>1.0 P i tt et<br>»-4GneeeeeeeEn ene<br>0.5<br>-60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Junction Temperature (°C)<br>RDS(on) , Drain-to-Source On Resistance                        (Normalized)<br>**----- End of picture text -----**<br>


**Fig 4.** Normalized On-Resistance vs. Temperature 

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14.0<br>ID= 15A<br>12.0 VDS= 160V<br>VDS= 100V<br>10.0 VDS= 40V<br>le<br>8.0<br>6.0<br>4.0<br>- ~iiit | |<br>2.0 A laa<br>0.0<br>0 5 10 15 20 25 30 35<br> QG,  Total Gate Charge (nC)<br>VGS, Gate-to-Source Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 6.** Typical Gate Charge vs.Gate-to-Source Voltage 

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100 T T ”™”™™m,<br>aa 4.<br>ee Ae<br>T = 175°C<br>J<br>Pt FE] TJ = 25°C |<br>10 P y |[| | |<br>p i [ff.] fo f<br>HF} } +<br>a ee ee<br>VGS = 0V<br>1.0<br>0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6<br>VSD, Source-to-Drain Voltage (V)<br>Fig 7.   Typical Source-Drain Diode Forward Voltage<br>30<br>25<br>=<br>~<br>20<br>SI<br>15 “<br>10 \<br>\<br>5<br>\<br>0<br>25 50 75 100 125 150 175<br> TC , Case Temperature (°C)<br>ID,  Drain Current (A)<br>ISD, Reverse Drain Current (A)<br>**----- End of picture text -----**<br>


**Fig 7.** Typical Source-Drain Diode Forward Voltage 

**Fig 9.** Maximum Drain Current vs. Case Temperature 

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1000 a<br>OPERATION IN THIS AREA<br>LIMITED BY R DS(on)<br>ao tt<br>100 a<br>100µsec<br>=e 1msec eae<br>10 e C s e<br>ery 1 0m sec T H |coo<br>| DC<br>1<br>ll<br>Tc = 25°C<br>Tj = 175°C<br>Single Pulse<br>a A<br>0.1<br>1 10 100 1000<br>VDS, Drain-to-Source Voltage (V)<br>Fig 8.   Maximum Safe Operating Area<br>6.0<br>S O<br>5.5<br>a<br>i s<br>5.0<br>O a s<br>4.5<br>e e ee<br>P SSST<br>4.0 S S<br>a a a a a<br>3.5<br>3.0 __ IIDD  = 100µA= 250uA LAANPNTI<br>2.5 ID = 1.0mA<br>_= ID = 1.0A f—T_T_TtANR<br>2.0<br>_a eeeSA<br>1.5<br>aa<br>AP N<br>1.0<br>-75 -50 -25 0 25 50 75 100 125 150 175<br>TJ , Temperature ( °C )<br>VGS(th), Gate threshold Voltage (V)<br>ID,  Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 10.** Threshold Voltage vs. Temperature 

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10<br>Po EE<br>1 e e<br>D = 0.50<br>SSS er ee ee<br>po r e<br>| EE 0.20 ereer ty A HH<br>0.1 0.100.05 R1 R1 R2 R2 Ri (°C/W)    τi (sec)<br>a 0.02 PS 2S eee τJ τJ 2 iL τCτ 0.456      0.000311 Ty<br>0.01 τ1 τ1 τ2τ2 0.589      0.003759<br>o e eM rh<br>0.01<br>Ci= τi/Ri<br>Ci i/Ri Notes:<br>SINGLE PULSE<br>1. Duty Factor D = t1/t2<br>( THERMAL RESPONSE )<br>2. Peak Tj = P dm x Zthjc + Tc<br>tt HEE ER LI<br>0.001 PF ain il<br>1E-006 1E-005 0.0001 0.001 0.01 0.1<br>t1 , Rectangular Pulse Duration (sec)<br>Fig 11.   Maximum Effective Transient Thermal Impedance, Junction-to-Case<br>Thermal Response ( Z thJC ) °C/W<br>**----- End of picture text -----**<br>


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0.5 500<br>ID = 15A 450 P itt] ID<br>TOP          2.05A<br>N ESE<br>0.4 400  2.94A<br>NETET Tt BOTTOM  15A<br>350<br>B NE<br>0.3 300<br>250 P IN | TTT ETT Ty<br>0.2 200 S OREL<br>TJ = 125°C<br>150<br>S SPXCEETET<br>0.1 100<br>TJ = 25°C S N<br>50 P TESSSS 0 0<br>0 0 Pii tT Ty |PPS}PPS}<br>4 6 8 10 12 14 16 25 50 75 100 125 150<br>Starting TJ , Junction Temperature (°C)<br>VGS, Gate -to -Source Voltage  (V)<br>   On-Resistance Vs. Gate Voltage Fig 13.<br>100<br>Duty Cycle = Single Pulse<br>eg 9 Allowed avalanche Current vs avalanche<br>pulsewidth, tav, assuming ∆Tj = 150°C and ∆Tj = 150°C and Tj = 150°C and<br>PEER RNP ntl<br>10 0.01 Tstart =25°C (Single Pulse)<br>gg Se<br>PT 0.05 SS IE S<br>0.10<br>P T mRNA UE LL<br>1 E e:Oe<br>Allowed avalanche Current vs avalanche<br>el TE<br>pulsewidth, tav, assuming ∆Τ j = 25°C and<br>Tstart = 150°C.<br>PE I<br>0.1 Po T T<br>1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02<br>tav (sec)<br>Fig 14.   Typical Avalanche Current Vs.Pulsewidth<br>Notes on Repetitive Avalanche Curves , Figures 14, 15:<br>120 (For further info, see AN-1005 at www.irf.com)<br>1. Avalanche failures assumption:<br>TOP          Single Pulse<br>  Purely a thermal phenomenon and failure occurs at a<br>BOTTOM   1.0% Duty Cycle<br>100 ID = 15A     temperature far in excess of Tjmax. This is validated forjmax. This is validated for. This is validated for<br>    every part type.<br>2. Safe operation in Avalanche is allowed as long as neither<br>80    Tjmax nor Iav (max) is exceeded<br>S SN 3. Equation below based on circuit and waveforms shown in<br>  Figures 17a, 17b.<br>60 4. PD (ave) = Average power dissipation per single<br>B ESNNGHEEEEE<br>    avalanche pulse.<br>5. BV = Rated breakdown voltage (1.3 factor accounts forV = Rated breakdown voltage (1.3 factor accounts for = Rated breakdown voltage (1.3 factor accounts for<br>40<br>    voltage increase during avalanche).<br>B UREN NUEREE 6. Iav = Allowable avalanche current.<br>20 7. ∆T = Allowable rise in junction temperature, not to exceed∆T = Allowable rise in junction temperature, not to exceedT = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed<br>    Tjmax (assumed as 25°C in Figure 14, 15).<br>P ENNE<br>  tav = Average time in avalanche.<br>0   D = Duty cycle in avalanche =  tav ·f<br>T TT EAN<br>25 50 75 100 125 150 175   ZthJC(D, tav) = Transient thermal resistance, see figure 11)thJC(D, tav) = Transient thermal resistance, see figure 11)(D, tav) = Transient thermal resistance, see figure 11)av) = Transient thermal resistance, see figure 11)) = Transient thermal resistance, see figure 11)<br>Starting TJ , Junction Temperature (°C) PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) = A T/ ZthJCthJC<br>)Ω<br>RDS(on),  Drain-to -Source On Resistance (<br>EAS , Single Pulse Avalanche Energy (mJ)<br>EAR , Avalanche Energy (mJ)<br>Avalanche Current (A)<br>**----- End of picture text -----**<br>


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500<br>450 P itt] ID<br>TOP          2.05A<br>N ESE<br>400  2.94A<br>NETET Tt BOTTOM  15A<br>350<br>B NE<br>300<br>250 P IN | TTT ETT Ty<br>200 S OREL<br>150<br>S SPXCEETET<br>100<br>S N EE<br>50 P TESSSS 0 0<br>0 Pii tT Ty |PPS}PPS}<br>25 50 75 100 125 150 175<br>Starting TJ , Junction Temperature (°C)<br>EAS , Single Pulse Avalanche Energy (mJ)<br>**----- End of picture text -----**<br>


## **Fig 12.** On-Resistance Vs. Gate Voltage 

**Fig 13.** Maximum Avalanche Energy Vs. Drain Current 

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Allowed avalanche Current vs avalanche<br>pulsewidth, tav, assuming ∆Tj = 150°C and ∆Tj = 150°C and Tj = 150°C and<br>ntl<br>Tstart =25°C (Single Pulse)<br>IE S<br>UE LL<br>TE<br>I<br>T<br>1.0E-03 1.0E-02 1.0E-01<br>**----- End of picture text -----**<br>


**Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com)** 

- Purely a thermal phenomenon and failure occurs at a 

- temperature far in excess of Tjmax. This is validated forjmax. This is validated for. This is validated for every part type. 

2. Safe operation in Avalanche is allowed as long as neither Tjmax nor Iav (max) is exceeded 

3. Equation below based on circuit and waveforms shown in Figures 17a, 17b. 

5. BV = Rated breakdown voltage (1.3 factor accounts forV = Rated breakdown voltage (1.3 factor accounts for = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 

7. ∆T = Allowable rise in junction temperature, not to exceed∆T = Allowable rise in junction temperature, not to exceedT = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed 

ZthJC(D, tav) = Transient thermal resistance, see figure 11)thJC(D, tav) = Transient thermal resistance, see figure 11)(D, tav) = Transient thermal resistance, see figure 11)av) = Transient thermal resistance, see figure 11)) = Transient thermal resistance, see figure 11) 

**PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) =** A **T/ ZthJCthJC Iav = 2** A **T/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav** 

**Fig 15.** Maximum Avalanche Energy Vs. Temperature 

www.irf.com 

5 

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Driver Gate Drive<br>P.W.<br>D.U.T + {+ P.W. Period ——— — D = —— Period<br>) [©)] Circuit    • Low StrayLayoutInductConsiderations ) t V | GS=10V<br>•<br>-<br>+ CurrentowLeakageTransformerInductance 2) D.U.T. ISD Waveform<br>= ReverseRecovery Body Diode Forward \<br>- a - ® + Current r Current di/dt /<br>® D.U.T. VDS Waveform Diode Recoverydv/dt ‘<br>00 _ VDD<br>ma<br>•  Re-Applied<br>•  riversame type as D.U.T. + Voltage Body Diode  Forward Drop<br>Re ( 4) •  vidtcontrolled by Rg VDD -<br>•  D.U.T. - Device Under Test ee ee<br>Ripple  ≤ 5% ISD<br>o” sp controlled by Duty Factor"D" ®<br>* Vgg = 5V for Logic Level Devices<br>Fig 16. eak Diode Recovery dv/dt Test Circuit or N-Channel<br>HEXFET ® ower MOSFETs<br>V(BR)DSS<br>15V ~—— tp -><br>VDS L DRIVER<br>RG D.U.T +<br>- [V][DD]<br>IAS A<br>¢ 20V ab<br>tp 0.01 A Ω IAS —<br>**----- End of picture text -----**<br>


**Fig 17a.** Unclamped Inductive Test Circuit 

**Fig 17b.** Unclamped Inductive Waveforms 

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VDS<br>90%<br>\<br>10% /\<br>VGS ele ns<br>td(on) tr td(off) tf<br>**----- End of picture text -----**<br>


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+<br>-<br> 1<br> 0.1 %<br>**----- End of picture text -----**<br>


## **Fig 18a.** Switching Time Test Circuit 

## **Fig 18b.** Switching Time Waveforms 

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Id<br>**----- End of picture text -----**<br>


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Current Regulator<br>Same Type as D.U.T. Vds<br>| 50KΩ fl<br>12V .2µF<br>| .3µF<br>|[| ii) +<br>D.U.T. -VDS<br>Vgs(th)<br>VGS<br>fi 3mA i} |<br>se IG ID la g pl e v v i s a p , !<br>Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr<br>**----- End of picture text -----**<br>


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Vds<br>fl Vgs<br>Vgs(th)<br>i} |<br>la g pl e v v i s a p , !<br>Qgs1 Qgs2 Qgd Qgodr<br>**----- End of picture text -----**<br>


**Fig 19a.** Gate Charge Test Circuit 

**Fig 19b.** Gate Charge Waveform 

www.irf.com 

6 

TO-220AB packages are not recommended for Surface Mount Application. 

**Note: For the most current drawing please refer to IR website at http://www.irf.com/package/** 

Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. 

**IR WORLD HEADQUARTERS:** 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information **.** 09/2008 

www.irf.com 

7 

## **IMPORTANT NOTICE** 

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) . 

With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. 

In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. 

The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. 

For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office ( **www.infineon.com** ). 

## **WARNINGS** 

Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. 

Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. 



## Links

- [View this product on Novapart](https://novapart.co/products/IRFB5620PBF/power-mosfet-n-channel-200-v-25-a-00725-ohm-to)
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---

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